SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

24.6 SPI Registers

Table 24-2 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 24-2 should be considered as reserved locations and the register contents should not be modified.

Table 24-2 SPI Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionSection 24.6.1
44hIMASKInterrupt maskSection 24.6.2
48hRISRaw interrupt statusSection 24.6.3
4ChMISMasked interrupt statusSection 24.6.4
50hISETInterrupt setSection 24.6.5
54hICLRInterrupt clearSection 24.6.6
58hIMSETInterrupt mask setSection 24.6.7
5ChIMCLRInterrupt mask clearSection 24.6.8
60hEMUEmulationSection 24.6.9
100hCTL0Control 0Section 24.6.10
104hCTL1Control 1Section 24.6.11
108hCLKCFG0Clock configuration 0Section 24.6.12
10ChCLKCFG1Clock configuration 1Section 24.6.13
110hIFLSInterrupt FIFO Level SelectSection 24.6.14
114hDMACRDMA controlSection 24.6.15
118hRXCRCReceive CRCSection 24.6.16
11ChTXCRCTransmit CRCSection 24.6.17
120hTXFHDR32Header write for 32bitsSection 24.6.18
124hTXFHDR24Header write for 24bitsSection 24.6.19
128hTXFHDR16Header write for 16bitsSection 24.6.20
12ChTXFHDR8Header write for 8bitsSection 24.6.21
130hTXFHDRCAtomic header controlSection 24.6.22
140hRXDATAReceive dataSection 24.6.23
150hTXDATATransmit dataSection 24.6.24
160hSTAStatusSection 24.6.25

Complex bit access types are encoded to fit into small table cells. Table 24-3 shows the codes that are used for access types in this section.

Table 24-3 SPI Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

24.6.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 24-4.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 24-4 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR604DhModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

24.6.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 24-5.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 24-5 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hDMA Done TX event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
7DMARXR/W0hDMA Done RX event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
6IDLER/W0hSPI Idle event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5TXEMPTYR/W0hTransmit FIFO Empty event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
4TXR/W0hTransmit FIFO event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
3RXR/W0hReceive FIFO event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
2RTOUTR/W0h SPI Receive Time-Out event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
1PERR/W0hParity error event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0RXOVFR/W0hRXFIFO overflow event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask

24.6.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 24-6.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 24-6 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR0hDMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the TX DMA event inside SPI.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7DMARXR0hDMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows handling of the DMA RX event inside SPI.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
6IDLER0hSPI has completed transfers and moved to IDLE mode. This bit is set when STA.BUSY goes low.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5TXEMPTYR0hTransmit FIFO Empty interrupt mask. This interrupt is set when all data in the Transmit FIFO has been moved to the shift register.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4TXR0hTransmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3RXR0hReceive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2RTOUTR0hSPI Receive Time-Out event. This interrupt is set if no activity is detected on the input clock line within the time period dictated by CTL1.RTOUT value. This is applicable only in peripheral mode.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1PERR0hParity error event. This bit is set if a Parity error has been detected
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0RXOVFR0hRXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

24.6.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 24-7.

Return to the Summary Table.

Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 24-7 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR0hMasked DMA Done event for TX.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7DMARXR0hMasked DMA Done event for RX.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
6IDLER0hMasked SPI IDLE event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5TXEMPTYR0hMasked Transmit FIFO Empty event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4TXR0hMasked Transmit FIFO event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3RXR0hMasked Receive FIFO event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2RTOUTR0hMasked SPI Receive Time-Out event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1PERR0hMasked Parity error event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0RXOVFR0hMasked RXFIFO overflow event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

24.6.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 24-8.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 24-8 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hSet DMA Done event for TX.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
7DMARXW0hSet DMA Done event for RX.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
6IDLEW0hSet SPI IDLE event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
5TXEMPTYW0hSet Transmit FIFO Empty event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
4TXW0hSet Transmit FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
3RXW0hSet Receive FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
2RTOUTW0hSet SPI Receive Time-Out Event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
1PERW0hSet Parity error event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
0RXOVFW0hSet RXFIFO overflow event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt

24.6.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 24-9.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 24-9 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hClear DMA Done event for TX.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
7DMARXW0hClear DMA Done event for RX.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
6IDLEW0hClear SPI IDLE event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
5TXEMPTYW0hClear Transmit FIFO Empty event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
4TXW0hClear Transmit FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
3RXW0hClear Receive FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
2RTOUTW0hClear SPI Receive Time-Out Event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
1PERW0hClear Parity error event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
0RXOVFW0hClear RXFIFO overflow event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt

24.6.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 24-10.

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Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 24-10 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hSet DMA Done for TX event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
7DMARXW0hSet DMA Done for RX event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
6IDLEW0hSet SPI IDLE event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
5TXEMPTYW0hSet Transmit FIFO Empty event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
4TXW0hSet Transmit FIFO event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
3RXW0hSet Receive FIFO event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
2RTOUTW0hSet SPI Receive Time-Out event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
1PERW0hSet Parity error event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
0RXOVFW0hSet RXFIFO overflow event mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask

24.6.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 24-11.

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Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 24-11 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hClear DMA Done for TX event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
7DMARXW0hClear DMA Done for RX event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
6IDLEW0hClear SPI IDLE event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
5TXEMPTYW0hClear Transmit FIFO Empty event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
4TXW0hClear Transmit FIFO event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
3RXW0hClear Receive FIFO event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
2RTOUTW0hClear SPI Receive Time-Out event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
1PERW0hClear Parity error event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
0RXOVFW0hClear RXFIFO overflow event mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask

24.6.9 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 24-12.

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Emulation control register. This register controls the behavior of the IP related to core halted input.

Table 24-12 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hHalt control
  • 0h = Free run option. The IP ignores the state of the core halted input.
  • 1h = Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary (end of word boundary, based on DSS configuration) from where it can resume without corruption.

24.6.10 CTL0 Register (Offset = 100h) [Reset = 00000000h]

CTL0 is shown in Table 24-13.

Return to the Summary Table.

SPI control register 0

Table 24-13 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17IDLEPOCIR/W0hThe Idle value of POCI - when TXFIFO is empty and before data is written into TXFIFO - can be controlled by this field.
  • 0h = POCI output idle value of '0'
  • 1h = POCI outputs idle value of '1'
16GPCRCENR/W0hGeneral purpose CRC enable. This bit enables transmit side CRC unit for general purpose use by software when SPI is disabled (CTL1.EN = 0). This bit must be 0 when SPI is enabled.
  • 0h = Transmit side CRC unit is not available for general purpose software use
  • 1h = Transmit side CRC unit is available for general purpose software use
15CRCPOLYR/W0hCRC polynomial selection.
  • 0h = Selects 8-bit CCITT CRC polynomial
  • 1h = Selects 16-bit CCITT CRC polynomial
14AUTOCRCR/W0hAuto insert CRC
  • 0h = Do not insert CRC into TXFIFO upon TXFIFO underflow
  • 1h = Insert CRC into TXFIFO upon TXFIFO underflow
13CRCENDR/W0hCRC16 Endianness
  • 0h = Auto-insertion of CRC16 is most-significant byte first
  • 1h = Auto-insertion of CRC16 is least-significant byte first
12CSCLRR/W0hClear shift register counter on CS inactive.
This bit is relevant only in the peripheral mode, when CTL1.MS=0.
  • 0h = Disable automatic clear of shift register when CS goes inactive.
  • 1h = Enable automatic clear of shift register when CS goes inactive.
11FIFORSTR/W0hThis bit is used to reset transmit and receive FIFO pointers. This bit is auto cleared once the FIFO pointer reset operation is completed.
  • 0h = FIFO pointers reset completed when 0 is read
  • 1h = Trigger FIFO pointers reset when written to 1.
10HWCSNR/W0hHardware controlled chip select (CS) value. When set CS is zero till TX FIFO is empty, as in -
a. CS is de-asserted
b. All data bytes are transmitted
c. CS is asserted
  • 0h = HWCSN Disable
  • 1h = HWCSN Enable
9SPHR/W0hSCLK phase (Motorola SPI frame format only).
This bit selects the clock edge that captures data and enables it to change state.
It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture clock edge.
  • 0h = Data is captured on the first clock edge transition.
  • 1h = Data is captured on the second clock edge transition.
8SPOR/W0hSCLK polarity (Motorola SPI frame format only).
  • 0h = SPI produces a steady state LO value on the SCLK
  • 1h = SPI produces a steady state HI value on the SCLK
7RESERVEDR0hReserved
6-5FRFR/W0hFrame format select
  • 0h = Motorola SPI frame format (3-wire mode)
  • 1h = Motorola SPI frame format (4-wire mode)
  • 2h = TI synchronous serial frame format
  • 3h = MICROWIRE frame format
4RESERVEDR0hReserved
3-0DSSR/W0hData size select. The applicable DSS values for controller mode operation are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 0x0 to 0x2 are reserved and must not be used.
  • 3h = 4-bits data size
  • 4h = 5-bits data size
  • 5h = 6-bits data size
  • 6h = 7-bits data size
  • 7h = 8-bits data size
  • 8h = 9-bits data size
  • 9h = 10-bits data size
  • Ah = 11-bits data size
  • Bh = 12-bits data size
  • Ch = 13-bits data size
  • Dh = 14-bits data size
  • Eh = 15-bits data size
  • Fh = 16-bits data size

24.6.11 CTL1 Register (Offset = 104h) [Reset = 00000000h]

CTL1 is shown in Table 24-14.

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SPI control register 1

Table 24-14 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-24RTOUTR/W0hReceive Timeout (only for Peripheral mode)
Defines the number of CLKSVT clock cycles after which the Receive Timeout flag RIS.RTOUT is set.
A value of 0 disables this function.
23-16REPTXR/W0hCounter to repeat last transfer (only in controller mode)
0: repeat last transfer is disabled.
x: repeat the last transfer with the provided value.
The transfer will be started with writing a data into the TX FIFO. Sending the data will be repeated REPTX number of times, so the data will be transferred x+1 times in total.
It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
15-12CDMODER/W0hCommand Data Mode. This bit field value determines the behavior of C/D or CS signal when CDEN = 1. CS pin held low indicates command phase and CS pin held high indicates data phase.
When CDMODE = 0x0, the CS pin is always held high during transfer indicating data phase only operation (manual mode).
When CDMODE = 0xF, the CS pin is always held low during transfer indicating command phase only operation (manual mode).
When CDMODE = 0x1 to 0xE, the CS pin is held low for the number of bytes indicated by CDMODE value for the command phase and held high for the remaining transfers in the data phase (automatic mode).
When CDMODE is set to value 0x1 to 0xE, reading CDMODE during operation indicates the remaining bytes to be transferred in the command phase.
  • 0h = Manual mode: Data
  • Fh = Manual mode: Command
11CDENR/W0hCommand/Data mode enable. This feature is applicable only in controller mode and for 8-bit transfers (CTL0.DSS = 7). The chip select pin is used for command/data signaling in Motorola SPI frame format (3-wire) operation.
  • 0h = C/D Mode Disable
  • 1h = C/D Mode Enable
10-8RESERVEDR0hReserved
7PBSR/W0hParity bit select
  • 0h = Bit 0 is used for Parity
  • 1h = Bit 1 is used for Parity, Bit 0 is ignored
6PESR/W0hEven parity select.
  • 0h = Odd Parity mode
  • 1h = Even Parity mode
5PENR/W0hParity enable. If enabled the last bit will be used as parity to evaluate the correct reception of the previous bits.
In case of parity mismatch the parity error flag RIS.PER will be set. This feature is available only in SPI controller mode.
  • 0h = Disable Parity function
  • 1h = Enable Parity function
4MSBR/W0hMSB first select. Controls the direction of receive and transmit shift register. MSB first configuration (MSB = 1) must be selected when CRC feature is used for SPI communication.
  • 0h = LSB first
  • 1h = MSB first
3PODR/W0hPeripheral data output disable.
This bit is relevant only in the peripheral mode, MS=1. In multiple-peripheral systems, it is possible for a SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the POCI lines from multiple peripherals could be tied together. To operate in such systems, this bit field can be set if the SPI peripheral is not supposed to drive the POCI output.
  • 0h = SPI can drive the POCI output in peripheral mode.
  • 1h = SPI cannot drive the POCI output in peripheral mode.
2MSR/W1hController or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.EN=0.
  • 0h = Select Peripheral mode
  • 1h = Select Controller mode
1LBMR/W0hLoop back mode control
  • 0h = Disable loopback mode. Normal serial port operation enabled.
  • 1h = Enable loopback mode. Output of transmit serial shifter is connected to input of receive serial shifter internally.
0ENR/W0hSPI enable.
NOTE: This bit field must be set to 1 using a separate write access, after the other bit fields have been configured.
  • 0h = SPI is disabled
  • 1h = SPI Enabled and released for operation.

24.6.12 CLKCFG0 Register (Offset = 108h) [Reset = 00000000h]

CLKCFG0 is shown in Table 24-15.

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Clock configuration register 0. This register is used to configure the clock prescaler.

Table 24-15 CLKCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0PRESCR/W0hPrescaler configuration
  • 0h = Do not divide clock source
  • 1h = Divide clock source by 2
  • 2h = Divide clock source by 3
  • 3h = Divide clock source by 4
  • 4h = Divide clock source by 5
  • 5h = Divide clock source by 6
  • 6h = Divide clock source by 7
  • 7h = Divide clock source by 8

24.6.13 CLKCFG1 Register (Offset = 10Ch) [Reset = 00000000h]

CLKCFG1 is shown in Table 24-16.

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Clock configuration register 1. This register is used to configure serial clock rate and clock count for delayed sampling in controller mode.

Table 24-16 CLKCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16DSAMPLER/W0hDelayed sampling. In controller mode the data on the POCI pin will be delayed sampled by the defined CLKSVT clock cycles. DSAMPLE values can range from 0 to SCR+1. Typically, values of 1 or 2 would suffice.
15-10RESERVEDR0hReserved
9-0SCRR/W0hSerial clock divider. This is used to generate the transmit and receive bit rate of the SPI.
The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*PRESC). SCR value can be from 0 to 1023.

24.6.14 IFLS Register (Offset = 110h) [Reset = 00000000h]

IFLS is shown in Table 24-17.

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Interrupt FIFO level select register. This register can be used to define the levels at which the RIS.TX, RIS.RX flags are triggered. The interrupts are generated based on FIFO level. Out of reset, the IFLS.TXSEL and IFLS.RXSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Table 24-17 IFLS Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8RXSELR/W2hReceive FIFO Level Select. The trigger points for the receive interrupt are as follows:
  • 0h = Reserved
  • 1h = RX FIFO >= 1/4 full
  • 2h = RX FIFO >= 1/2 full (default)
  • 3h = RX FIFO >= 3/4 full
  • 4h = Reserved
  • 5h = RX FIFO is full
  • 6h = Reserved
  • 7h = Trigger when RX FIFO contains >= 1 byte
7-3RESERVEDR0hReserved
2-0TXSELR/W2hTransmit FIFO Level Select. The trigger points for the transmit interrupt are as follows:
  • 0h = Reserved
  • 1h = TX FIFO <= 3/4 empty
  • 2h = TX FIFO <= 1/2 empty (default)
  • 3h = TX FIFO <= 1/4 empty
  • 4h = Reserved
  • 5h = TX FIFO is empty
  • 6h = Reserved
  • 7h = Trigger when TX FIFO has >= 1 byte free

24.6.15 DMACR Register (Offset = 114h) [Reset = 00000000h]

DMACR is shown in Table 24-18.

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uDMA Control Register

Table 24-18 DMACR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8TXENR/W0hTransmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
  • 0h = Disable TX DMA
  • 1h = Enable TX DMA
7-1RESERVEDR0hReserved
0RXENR/W0hReceive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
  • 0h = Disable RX DMA
  • 1h = Enable RX DMA

24.6.16 RXCRC Register (Offset = 118h) [Reset = 00000000h]

RXCRC is shown in Table 24-19.

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Receive CRC register. Reading this register provides the computed CRC value from the receive side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CTL0.CRCPOLY = 0 and 0xFFFF when CTL0.CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are don't care when CTL0.CRCPOLY = 0.

Table 24-19 RXCRC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hCRC value
SW should read RXCRC register at the end of data transmission to reinitialize the seed value to all ones

24.6.17 TXCRC Register (Offset = 11Ch) [Reset = 00000000h]

TXCRC is shown in Table 24-20.

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Transmit CRC register. Reading this register provides the computed CRC value from the transmit side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CTL0.CRCPOLY = 0 and 0xFFFF when CTL0.CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are don't care when CTL0.CRCPOLY = 0.

Table 24-20 TXCRC Register Field Descriptions
BitFieldTypeResetDescription
31AUTOCRCINSR0hStatus to indicate if Auto CRC has been inserted into TXFIFO.
This is applicable only if CTL0.AUTOCRC enable bit is set.
SW should read TXCRC register to clear auto inserted CRC at the end of the transfer.
  • 0h = Auto CRC not yet inserted
  • 1h = Auto CRC inserted
30-16RESERVEDR0hReserved
15-0DATAR/W0hCRC value

24.6.18 TXFHDR32 Register (Offset = 120h) [Reset = 00000000h]

TXFHDR32 is shown in Table 24-21.

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Header update register for 32 bits of header data into the TXFIFO.

Table 24-21 TXFHDR32 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write four bytes of header data into the TXFIFO

24.6.19 TXFHDR24 Register (Offset = 124h) [Reset = 00000000h]

TXFHDR24 is shown in Table 24-22.

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Header update register for 24 bits of header data into the TXFIFO.

Table 24-22 TXFHDR24 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write three bytes of header data into the TXFIFO.

24.6.20 TXFHDR16 Register (Offset = 128h) [Reset = 00000000h]

TXFHDR16 is shown in Table 24-23.

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Header update register for 16 bits of data into the TXFIFO.

Table 24-23 TXFHDR16 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write two bytes of header data into the TXFIFO.

24.6.21 TXFHDR8 Register (Offset = 12Ch) [Reset = 00000000h]

TXFHDR8 is shown in Table 24-24.

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Header update register for 8 bits of header data into the TXFIFO.

Table 24-24 TXFHDR8 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write one byte of header data into the TXFIFO.

24.6.22 TXFHDRC Register (Offset = 130h) [Reset = 00000000h]

TXFHDRC is shown in Table 24-25.

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Atomic Header Control register

Table 24-25 TXFHDRC Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CSGATER/W0hChip Select Gating control register. If this bit is set, header update register writes are blocked when chip select (CS) is active low, and HDRIGN bit is set.
This bit resets to 0.
  • 0h = The first header update register write is not blocked based on CS active status (low). ;If no header update occurred when CS was high (inactive), the first header update is allowed when CS is low (active), and the HDRCMT bit is set. The use case is for the external controller to ensure that the SCLK is not driven during this header update.;If the header is already updated when CS is high and inactive, HDRCMT is set immediately when CS drops to active low state, and header writes when CS is low are ignored even if this UNBLK bit is set.
  • 1h = Header update register writes are blocked when CS is active (low)
2HDRCMTR/W0hHeader Committed field. This bit is set when the HDREN bit is set and CS is sampled low. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
  • 0h = Header update is not committed
  • 1h = Header update is committed
1HDRIGNR/W0hHeader Ignored field. When CSGATE is set to BLK, this bit is set when the last Header update register TXFHDRn is written when CS is low or HDRCMT is already set. When CSGATE is set to UNBLK, this bit is set only when the header update register is written when HDRCMT is already set. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
  • 0h = Header update is not ignored
  • 1h = Header update is ignored
0HDRENR/W0hHeader enable field. When CSGATE is set to BLK, this bit has to be set by software to enable atomic header feature. When CSGATE is set to UNBLK, this field is set automatically whenever a write to header update registers TXFHDRn occurs.
  • 0h = Atomic header update feature disable
  • 1h = Atomic header update feature enable

24.6.23 RXDATA Register (Offset = 140h) [Reset = 00000000h]

RXDATA is shown in Table 24-26.

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RXDATA Register. Reading this register returns first value in the RX FIFO. If the FIFO is empty the last read value is returned. Writing has no effect and is ignored.

Table 24-26 RXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hReceived Data. When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer is accessed. As data values are read by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current RX FIFO write pointer.
Received data less than 16 bits is automatically right-justified in the receive buffer.

24.6.24 TXDATA Register (Offset = 150h) [Reset = 00000000h]

TXDATA is shown in Table 24-27.

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TXDATA Register. Writing a value in this register puts the data into the TX FIFO. Reading this register returns the last written value.

Table 24-27 TXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hTransmit Data. When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer is accessed.
When written, the entry in the TX FIFO pointed to by the write pointer, is written to. Data values are read from the transmit FIFO by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the output pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.

24.6.25 STA Register (Offset = 160h) [Reset = 00000000h]

STA is shown in Table 24-28.

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Status Register

Table 24-28 STA Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8TXFIFOLVLR0hIndicates how many locations of TXFIFO are currently filled with data
7RESERVEDR0hReserved
6TXDONER/W0hTransmit done. Indicates whether the last bit has left the Shift register after a transmission
  • 0h = Last bit has not yet left the Shift register, and the transmission is ongoing.
  • 1h = Last bit has been shifted out, and the transmission is done
5CSDR/W0hDetection of CS deassertion in the middle of a data frame transmission results in this error being set. This feature is only available in the peripheral mode.
  • 0h = No CS posedge is detected before the entire data frame has been transmitted.
  • 1h = An error is generated when CS posedge (deassertion) is detected before the entire data frame is transmitted.
4BUSYR0hSPI Busy status
  • 0h = SPI is in idle mode.
  • 1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
3RNFR1hReceive FIFO not full status.
  • 0h = Receive FIFO is full.
  • 1h = Receive FIFO is not full.
2RFER1hReceive FIFO empty status.
  • 0h = Receive FIFO is not empty.
  • 1h = Receive FIFO is empty.
1TNFR1hTransmit FIFO not full status.
  • 0h = Transmit FIFO is full.
  • 1h = Transmit FIFO is not full.
0TFER1hTransmit FIFO empty status.
  • 0h = Transmit FIFO is not empty.
  • 1h = Transmit FIFO is empty.