SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

8.9 HSMCRYPTO Registers

Table 8-7 lists the memory-mapped registers for the HSMCRYPTO registers. All register offset addresses not listed in Table 8-7 should be considered as reserved locations and the register contents should not be modified.

Table 8-7 HSMCRYPTO Registers
OffsetAcronymRegister NameSection
0hMB1INInput Mailbox 1Section 8.9.1
0hMB1OUTOutput Mailbox 1Section 8.9.2
400hMB2INInput Mailbox 2Section 8.9.3
400hMB2OUTOutput Mailbox 2Section 8.9.4
3E00hAICPOLAIC Polarity Control RegisterSection 8.9.5
3E04hAICTYPEAIC Type Control RegisterSection 8.9.6
3E08hAICENAIC Enable Control RegisterSection 8.9.7
3E0ChAICRSTAAIC Raw Source Status RegisterSection 8.9.8
3E0ChAICENSETAIC Enable Set RegistersSection 8.9.9
3E10hAICENSTAAIC Enabled Status RegisterSection 8.9.10
3E10hAICACKAIC Acknowledge RegisterSection 8.9.11
3E14hAICENCLRAIC Enable Clear RegisterSection 8.9.12
3E18hAICOPTAIC Options RegisterSection 8.9.13
3E1ChAICVERAIC Version RegisterSection 8.9.14
3F00hMBSTAMailbox Status RegisterSection 8.9.15
3F00hMBCTLMailbox Control RegisterSection 8.9.16
3F04hMBRSTARaw Mailbox Status RegisterSection 8.9.17
3F04hMBRSTMailbox Reset Register. Only Master Host can write into this registerSection 8.9.18
3F08hMBLNKIDMailbox Status - linked Host IDs RegisterSection 8.9.19
3F0ChMBOUTIDMailbox Status - output Host IDs RegisterSection 8.9.20
3F10hMBLCKOUTHost or Mailbox lockout control RegisterSection 8.9.21
3FE0hMODSTAModule Status RegisterSection 8.9.22
3FF4hOPTIONS2Configured options(2)Section 8.9.23
3FF8hOPTIONSConfigured options(1)Section 8.9.24
3FFChVERSIONVersion registerSection 8.9.25

Complex bit access types are encoded to fit into small table cells. Table 8-8 shows the codes that are used for access types in this section.

Table 8-8 HSMCRYPTO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.9.1 MB1IN Register (Offset = 0h) [Reset = 00000000h]

MB1IN is shown in Table 8-9.

Return to the Summary Table.

Input Mailbox 1

Table 8-9 MB1IN Register Field Descriptions
BitFieldTypeResetDescription
31-0MEMR0hInput Mailbox Memory

8.9.2 MB1OUT Register (Offset = 0h) [Reset = 00000000h]

MB1OUT is shown in Table 8-10.

Return to the Summary Table.

Output Mailbox 1

Table 8-10 MB1OUT Register Field Descriptions
BitFieldTypeResetDescription
31-0MEMW0hOutput Mailbox Memory

8.9.3 MB2IN Register (Offset = 400h) [Reset = 00000000h]

MB2IN is shown in Table 8-11.

Return to the Summary Table.

Input Mailbox 2

Table 8-11 MB2IN Register Field Descriptions
BitFieldTypeResetDescription
31-0MEMR0hInput Mailbox Memory

8.9.4 MB2OUT Register (Offset = 400h) [Reset = 00000000h]

MB2OUT is shown in Table 8-12.

Return to the Summary Table.

Output Mailbox 2

Table 8-12 MB2OUT Register Field Descriptions
BitFieldTypeResetDescription
31-0MEMW0hOutput Mailbox Memory

8.9.5 AICPOL Register (Offset = 3E00h) [Reset = 00000000h]

AICPOL is shown in Table 8-13.

Return to the Summary Table.

AIC Polarity Control Register

Table 8-13 AICPOL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Polarity
  • 0h = Low level/falling edge
  • 1h = High level/rising edge
3MB2DONER/W0hMailbox 2 Token Done Interrupt Polarity
  • 0h = Low level/falling edge
  • 1h = High level/rising edge
2MB2FREER/W0hMailbox 2 Free Interrupt Polarity
  • 0h = Low level/falling edge
  • 1h = High level/rising edge
1MB1DONER/W0hMailbox 1 Token done Interrupt Polarity
  • 0h = Low level/falling edge
  • 1h = High level/rising edge
0MB1FREER/W0hMailbox 1 Free Interrupt Polarity
  • 0h = Low level/falling edge
  • 1h = High level/rising edge

8.9.6 AICTYPE Register (Offset = 3E04h) [Reset = 00000000h]

AICTYPE is shown in Table 8-14.

Return to the Summary Table.

AIC Type Control Register

Table 8-14 AICTYPE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Type
  • 0h = Level
  • 1h = Edge
3MB2DONER/W0hMailbox 2 Token Done Interrupt Type
  • 0h = Level
  • 1h = Edge
2MB2FREER/W0hMailbox 2 Free Interrupt Type
  • 0h = Level
  • 1h = Edge
1MB1DONER/W0hMailbox 1 Token Done Interrupt Type
  • 0h = Level
  • 1h = Edge
0MB1FREER/W0hMailbox 1 Free Interrupt Type
  • 0h = Level
  • 1h = Edge

8.9.7 AICEN Register (Offset = 3E08h) [Reset = 00000000h]

AICEN is shown in Table 8-15.

Return to the Summary Table.

AIC Enable Control Register

Table 8-15 AICEN Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Enable. Indicates one or more mailbox can be linked
  • 0h = Disable
  • 1h = Enable
3MB2DONER/W0hMailbox 2 Token Done Interrupt Enable
  • 0h = Disable
  • 1h = Enable
2MB2FREER/W0hMailbox 2 Free Interrupt Enable
  • 0h = Disable
  • 1h = Enable
1MB1DONER/W0hMailbox 1 Token done Interrupt Enable
  • 0h = Disable
  • 1h = Enable
0MB1FREER/W0hMailbox 1 Free Interrupt Enable
  • 0h = Disable
  • 1h = Enable

8.9.8 AICRSTA Register (Offset = 3E0Ch) [Reset = 00000000h]

AICRSTA is shown in Table 8-16.

Return to the Summary Table.

AIC Raw Source Status Register

Table 8-16 AICRSTA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR1hMailbox Linkable Interrupt Status. Indicates one or more mailbox can be linked
3MB2DONER1hMailbox 2 Token Done Interrupt Status
2MB2FREER1hMailbox 2 Free Interrupt Status
1MB1DONER1hMailbox 1 Token done Interrupt Status
0MB1FREER1hMailbox 1 Free Interrupt Status

8.9.9 AICENSET Register (Offset = 3E0Ch) [Reset = 00000000h]

AICENSET is shown in Table 8-17.

Return to the Summary Table.

AIC Enable Set Registers

Table 8-17 AICENSET Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Enable Set
  • 1h = Set Enable
3MB2DONER/W0hMailBox 2 Token Done Interrupt Enable Set
  • 1h = Set Enable
2MB2FREER/W0hMailBox 2 Free Interrupt Enable Set
  • 1h = Set Enable
1MB1DONER/W0hMailBox 1 Token Done Interrupt Enable Set
  • 1h = Set Enable
0MB1FREER/W0hMailBox 1 Free Interrupt Enable Set
  • 1h = Set Enable

8.9.10 AICENSTA Register (Offset = 3E10h) [Reset = 00000000h]

AICENSTA is shown in Table 8-18.

Return to the Summary Table.

AIC Enabled Status Register

Table 8-18 AICENSTA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Enable Status
3MB2DONER/W0hMailbox 2 Done Interrupt Enable Status
2MB2FREER/W0hMailBox 2 Free Interrupt Enable Status
1MB1DONER/W0hMailBox 1 Token Done Interrupt Enable Status
0MB1FREER/W0hMailbox 1 Free Interrupt Enable Status

8.9.11 AICACK Register (Offset = 3E10h) [Reset = 00000000h]

AICACK is shown in Table 8-19.

Return to the Summary Table.

AIC Acknowledge Register

Table 8-19 AICACK Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Acknowledge
  • 1h = Interrupt Ack
3MB2DONER/W0hMailbox 2 Done Interrupt Acknowledge
  • 1h = Interrupt Ack
2MB2FREER/W0hMailBox 2 Free Interrupt Acknowledge
  • 1h = Interrupt Ack
1MB1DONER/W0hMailBox 1 Token Done Interrupt Acknowledge
  • 1h = Interrupt Ack
0MB1FREER/W0hMailbox 1 Free Interrupt Acknowledge
  • 1h = Interrupt Ack

8.9.12 AICENCLR Register (Offset = 3E14h) [Reset = 00000000h]

AICENCLR is shown in Table 8-20.

Return to the Summary Table.

AIC Enable Clear Register

Table 8-20 AICENCLR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4MBLNKABLR/W0hMailbox Linkable Interrupt Enable Clear
  • 1h = Clear Enable
3MB2DONER/W0hMailbox 2 Done Interrupt Enable Clear
  • 1h = Clear Enable
2MB2FREER/W0hMailBox 2 Free Interrupt Enable Clear
  • 1h = Clear Enable
1MB1DONER/W0hMailBox 1 Token Done Interrupt Enable Clear
  • 1h = Clear Enable
0MB1FREER/W0hMailbox 1 Free Interrupt Enable Clear
  • 1h = Clear Enable

8.9.13 AICOPT Register (Offset = 3E18h) [Reset = 00000000h]

AICOPT is shown in Table 8-21.

Return to the Summary Table.

AIC Options Register

Table 8-21 AICOPT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MINRMAPR0hMini register map.
7EXTRMAPR0hExtended register map.
6RESERVEDR0hReserved
5-0INPUTSR5hThe number of interrupt request inputs.

8.9.14 AICVER Register (Offset = 3E1Ch) [Reset = 00000000h]

AICVER is shown in Table 8-22.

Return to the Summary Table.

AIC Version Register

Table 8-22 AICVER Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24MAJORVERR1hThese bits encode the major version number for the AIC module.
23-20MINORVERR4hThese bits encode the minor version number for the AIC module.
19-16PATCHLVLR0hThese bits encode the hardware patch level for the AIC module, starting at value 0 on the first release.
15-8NUMCMPLR36hThese bits simply contain the complement of bits [7:0], used by a driver to ascertain that this version register is indeed read.
7-0NUMRC9hThese bits encode the AIC number.

8.9.15 MBSTA Register (Offset = 3F00h) [Reset = 00000000h]

MBSTA is shown in Table 8-23.

Return to the Summary Table.

Mailbox Status Register

Table 8-23 MBSTA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7MB2AVAILR0hInput Mailbox 2 available status
  • 0h = Input Mailbox is linked to a Host or is filled
  • 1h = Input Mailbox is available for linking by this Host
6MB2LNKDR0hMailbox 2 Link Status
  • 0h = This Host is not linked to Mailbox
  • 1h = This Host is linked to Mailbox
5MB2OUTR0hOutput Mailbox 2 Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full
4MB2INR0hInput Mailbox 2 Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full
3MB1AVAILR0hInput Mailbox 1 available status
  • 0h = Input Mailbox is linked to a Host or is filled
  • 1h = Input Mailbox is available for linking by this Host
2MB1LNKDR0hMailbox 1 Link Status
  • 0h = This Host is not linked to Mailbox
  • 1h = This Host is linked to Mailbox
1MB1OUTR0hOutput Mailbox 1 Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full
0MB1INR0hInput Mailbox 1 Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full

8.9.16 MBCTL Register (Offset = 3F00h) [Reset = 00000000h]

MBCTL is shown in Table 8-24.

Return to the Summary Table.

Mailbox Control Register

Table 8-24 MBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7MB2ULNKW0hUnlink the Mailbox from this host
  • 1h = unlink Mailbox 2
6MB2LNKW0hLink Mailbox to this Host. Host can link to a mailbox only if it is not filled and not linked to another host
  • 1h = Link Mailbox 2
5MB2OUTW0hThe Host for whom the token is in Output Mailbox 1 can clear the status
  • 1h = Set output mailbox empty
4MB2INW0hThe Host linked to input mailbox 2 can set after placing a token into Input Mailbox 2
  • 1h = Set Input Mailbox full
3MB1UNLNKW0hUnlink the Mailbox from this host
  • 1h = Unlink Mailbox 1
2MB1LNKW0hLink Mailbox to this Host. Host can link to a mailbox only if it is not filled and not linked to another host
  • 1h = Link Mailbox 1
1MB1OUTW0hThe Host for whom the token is in Output Mailbox 1 can clear the status
  • 1h = Set output mailbox empty
0MB1INW0hThe Host linked to input mailbox 1 can set after placing a token into Input Mailbox 1
  • 1h = Set Input Mailbox full

8.9.17 MBRSTA Register (Offset = 3F04h) [Reset = 00000000h]

MBRSTA is shown in Table 8-25.

Return to the Summary Table.

Raw Mailbox Status Register

Table 8-25 MBRSTA Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6MB2LNKDR0hMailbox 2 Linked Raw Status
  • 0h = This Host is not linked to Mailbox
  • 1h = This Host is linked to Mailbox
5MB2OUTR0hOutput Mailbox 2 Raw Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full
4MB2INR0hInput Mailbox 2 Raw Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full
3RESERVEDR0hReserved
2MB1LNKDR0hMailbox 1 Linked Raw Status
  • 0h = This Host is not linked to Mailbox
  • 1h = This Host is linked to Mailbox
1MB1OUTR0hOutput Mailbox 1 Raw Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full
0MB1INR0hInput Mailbox 1 Raw Status
  • 0h = Mailbox is Empty
  • 1h = Mailbox is Full

8.9.18 MBRST Register (Offset = 3F04h) [Reset = 00000000h]

MBRST is shown in Table 8-26.

Return to the Summary Table.

Mailbox Reset Register. Only Master Host can write into this register

Table 8-26 MBRST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7MB2ULNKW0hSet only - Master Host can unlink mbx from current Host by writing 1b here.
  • 1h = Unlink Mailbox
6RESERVEDR0hReserved
5MB2OUTW0hSet only - Master Host can clear mbx_out_full bit in MBSTA by writing 1b here.
  • 1h = Set Mailbox Empty
4RESERVEDR0hReserved
3MB1UNLNKW0hSet only - Master Host can unlink mbx from current Host by writing 1b here.
  • 1h = Unlink Mailbox
2RESERVEDR0hReserved
1MB1OUTW0hSet only - Master Host can clear mbx_out_full bit in MBSTA by writing 1b here.
  • 1h = Set Mailbox Empty
0RESERVEDR0hReserved

8.9.19 MBLNKID Register (Offset = 3F08h) [Reset = 00000000h]

MBLNKID is shown in Table 8-27.

Return to the Summary Table.

Mailbox Status - linked Host IDs Register

Table 8-27 MBLNKID Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7MB2PACCR0h0: Mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Mailbox 2 is only accessible if the Host uses protected access.
6-4MB2LNKIDR0hHost cpu_id of the Host linked to the Mailbox 2
3MB1PACCR0h0: Mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Mailbox 1 is only accessible if the Host uses protected access.
2-0MB1LNKIDR0hHost cpu_id of the Host linked to the Mailbox 1

8.9.20 MBOUTID Register (Offset = 3F0Ch) [Reset = 00000000h]

MBOUTID is shown in Table 8-28.

Return to the Summary Table.

Mailbox Status - output Host IDs Register

Table 8-28 MBOUTID Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7MB2PACCR0h0: Output mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 2 is only accessible if the Host uses protected access.
6-4MB2IDR0hHost cpu_id of the Host allowed to read a result from the Mailbox 2
3MB1PACCR0h0: Output mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 1 is only accessible if the Host uses protected access.
2-0MB1IDR0hHostID of the Host allowed to read a result from the Mailbox 1

8.9.21 MBLCKOUT Register (Offset = 3F10h) [Reset = 00000000h]

MBLCKOUT is shown in Table 8-29.

Return to the Summary Table.

Host or Mailbox lockout control Register

Table 8-29 MBLCKOUT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8MB2LKOUTR/W2hBit map indicates which Hosts are blocked from accessing mailbox 2
7-0MB1LKOUTR/W2hBit map indicates which Hosts are blocked from accessing mailbox 1

8.9.22 MODSTA Register (Offset = 3FE0h) [Reset = 00000000h]

MODSTA is shown in Table 8-30.

Return to the Summary Table.

Module Status Register

Table 8-30 MODSTA Register Field Descriptions
BitFieldTypeResetDescription
31FATALR0hSet if fatal error occured
30-24RESERVEDR0hReserved
23FWACPTDR0hSet if firmware is to be executed
22FWCKDONER0hSet if firmware checks complete
21-11RESERVEDR0hReserved
10CRC24ERRR0hSet if CRC on ProgramROM is fails
9CRC24OKR0hSet if CRC on ProgramROM is passes
8CRC24BSYR1hSet if CRC on ProgramROM is busy
7-0RESERVEDR0hReserved

8.9.23 OPTIONS2 Register (Offset = 3FF4h) [Reset = 00000000h]

OPTIONS2 is shown in Table 8-31.

Return to the Summary Table.

Configured options(2)

Table 8-31 OPTIONS2 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25ADDCE10R0hAn additional crypto engine is available in hardware as custom engine10
24ADDCE9R0hAn additional crypto engine is available in hardware as custom engine9
23ADDCE8R0hAn additional crypto engine is available in hardware as custom engine8
22ADDCE7R0hAn additional crypto engine is available in hardware as custom engine7
21ADDCE6R1hAn additional crypto engine is available in hardware as custom engine6
20ADDCE5R0hAn additional crypto engine is available in hardware as custom engine5
19ADDCE4R0hAn additional crypto engine is available in hardware as custom engine4
18ADDCE3R0hAn additional crypto engine is available in hardware as custom engine3
17ADDCE2R0hAn additional crypto engine is available in hardware as custom engine2
16ADDCE1R0hAn additional crypto engine is available in hardware as custom engine1
15-13RESERVEDR0hReserved
12BUSIFCR0hBus interface type, 0b = 32-bit AHB, 1b = 32-bit AXI
11-10RESERVEDR0hReserved
9PROGRAMR0hDownloadable RAM based firmware program memory.
8CCPUR0hC capable local cpu available
7RESERVEDR0hReserved
6CRNGR1hCRNG engine available
5PKCPR1hPKCP Engine available
4CRCR1hCRC calculation available
3TRNGR1hTRNG engine available
2SHAR1hSHA1/SHA2 combination core available
1RESERVEDR0hReserved
0DESAESR0hDES/AES combination crypto core available

8.9.24 OPTIONS Register (Offset = 3FF8h) [Reset = 00000000h]

OPTIONS is shown in Table 8-32.

Return to the Summary Table.

Configured options(1)

Table 8-32 OPTIONS Register Field Descriptions
BitFieldTypeResetDescription
31-24SHOSTR3hBits to indicate which of the 8 possible HOSTID codes on the bus interface are active Hosts with secure access
23MYIDSECR1hIndicates the current protection bit values of the Host actually reading the register
22-20MYIDR1hHost ID code for the Host that is reading this register
19RESERVEDR0hReserved
18-16MASTERIDR0hValue of the HOSTID that designates the Master Host
15-8HOSTIDR3hBits to indicate which of the 8 possible HOSTID codes on the bus interface are active
7-6RESERVEDR0hReserved
5-4MBSIZER1hMailbox pair Size
  • 0h = 128 Bytes
  • 1h = 256 Bytes
  • 2h = 512 Bytes
  • 3h = 1024 Bytes
3-0NMBR2hNumber of Input/Output Mailbox pairs

8.9.25 VERSION Register (Offset = 3FFCh) [Reset = 00000000h]

VERSION is shown in Table 8-33.

Return to the Summary Table.

Version register

Table 8-33 VERSION Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24MAJORR4hMajor Version release number for this module
23-20MINORR3hMinor Version release number for this module
19-16PATCHLVLR1hHardware Patch Level for this module
15-8NUMCMPLR7DhBit by Bit compliment of IP Number
7-0NUMR82hIP number