SWCU195A December   2024  â€“ May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

22.10 GPIO Registers

Table 22-45 lists the memory-mapped registers for the GPIO registers. All register offset addresses not listed in Table 22-45 should be considered as reserved locations and the register contents should not be modified.

Table 22-45 GPIO Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionSection 22.10.1
4hDESCEXModule Description ExtendedSection 22.10.2
44hIMASKInterrupt MaskSection 22.10.3
4ChRISRaw interrupt statusSection 22.10.4
54hMISMasked interrupt statusSection 22.10.5
5ChISETInterrupt setSection 22.10.6
64hICLRInterrupt clearSection 22.10.7
6ChIMSETInterrupt mask setSection 22.10.8
74hIMCLRInterrupt mask clearSection 22.10.9
100hDOUT3_0Alias for Data out 3 to 0Section 22.10.10
104hDOUT7_4Alias for Data out 7 to 4Section 22.10.11
108hDOUT11_8Alias for Data out 11 to 8Section 22.10.12
10ChDOUT15_12Alias for Data out 15 to 12Section 22.10.13
110hDOUT19_16Alias for Data out 19 to 16Section 22.10.14
114hDOUT23_20Alias for Data out 23 to 20Section 22.10.15
118hDOUT27_24Alias for Data out 27 to 24Section 22.10.16
11ChDOUT31_28Alias for Data out 31 to 28Section 22.10.17
200hDOUT31_0Data out 31 to 0Section 22.10.18
210hDOUTSET31_0Data out set 31 to 0Section 22.10.19
220hDOUTCLR31_0Data out clear 31 to 0Section 22.10.20
230hDOUTTGL31_0Data out toggle 31 to 0Section 22.10.21
300hDOUTTGL3_0Alias for Data out toggle 3 to 0Section 22.10.22
304hDOUTTGL7_4Alias for Data out toggle 7 to 4Section 22.10.23
308hDOUTTGL11_8Alias for Data out toggle 11 to 8Section 22.10.24
30ChDOUTTGL15_12Alias for Data out toggle 15 to 12Section 22.10.25
310hDOUTTGL19_16Alias for Data out toggle 19 to 16Section 22.10.26
314hDOUTTGL23_20Alias for Data out toggle 23 to 20Section 22.10.27
318hDOUTTGL27_24Alias for Data out toggle 27 to 24Section 22.10.28
31ChDOUTTGL31_28Alias for Data out toggle 31 to 28Section 22.10.29
400hDOE3_0Alias for Data out enable 3 to 0Section 22.10.30
404hDOE7_4Alias for Data out enable 7 to 4Section 22.10.31
408hDOE11_8Alias for Data out enable 11 to 8Section 22.10.32
40ChDOE15_12Alias for Data out enable 15 to 12Section 22.10.33
410hDOE19_16Alias for Data out enable 19 to 16Section 22.10.34
414hDOE23_20Alias for Data out enable 23 to 20Section 22.10.35
418hDOE27_24Alias for Data out enable 27 to 24Section 22.10.36
41ChDOE31_28Alias for Data out enable 31 to 28Section 22.10.37
500hDOE31_0Data out enable 31 to 0Section 22.10.38
510hDOESET31_0Data out enable set 31 to 0Section 22.10.39
520hDOECLR31_0Data out enable clear 31 to 0Section 22.10.40
530hDOETGL31_0Data out enable toggle 31 to 0Section 22.10.41
600hDIN3_0Alias for Data input 3 to 0Section 22.10.42
604hDIN7_4Alias for Data input 7 to 4Section 22.10.43
608hDIN11_8Alias for Data input 11 to 8Section 22.10.44
60ChDIN15_12Alias for Data input 15 to 12Section 22.10.45
610hDIN19_16Alias for Data input 19 to 16Section 22.10.46
614hDIN23_20Alias for Data input 23 to 20Section 22.10.47
618hDIN27_24Alias for Data input 27 to 24Section 22.10.48
61ChDIN31_28Alias for Data input 31 to 28Section 22.10.49
700hDIN31_0Data input 31 to 0Section 22.10.50
800hEVTCFGEvent configuration 0Section 22.10.51
810hEVTCFG1Event configuration 1Section 22.10.52

Complex bit access types are encoded to fit into small table cells. Table 22-46 shows the codes that are used for access types in this section.

Table 22-46 GPIO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

22.10.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 22-47.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 22-47 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR7C49hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

22.10.2 DESCEX Register (Offset = 4h) [Reset = 00000000h]

DESCEX is shown in Table 22-48.

Return to the Summary Table.

Provide IP-specific instance information

Table 22-48 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0NUMDIOR1EhThis provides the total number of DIOs supported by GPIO. The number of DIOs supprted is NUMDIO + 1

22.10.3 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 22-49.

Return to the Summary Table.

Interrupt mask for DIO pins

Table 22-49 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30R/W0hInterrupt mask for DIO30
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
29DIO29R/W0hInterrupt mask for DIO29
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
28DIO28R/W0hInterrupt mask for DIO28
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
27DIO27R/W0hInterrupt mask for DIO27
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
26DIO26R/W0hInterrupt mask for DIO26
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
25DIO25R/W0hInterrupt mask for DIO25
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
24DIO24R/W0hInterrupt mask for DIO24
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
23DIO23R/W0hInterrupt mask for DIO23
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
22DIO22R/W0hInterrupt mask for DIO22
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
21DIO21R/W0hInterrupt mask for DIO21
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
20DIO20R/W0hInterrupt mask for DIO20
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
19DIO19R/W0hInterrupt mask for DIO19
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
18DIO18R/W0hInterrupt mask for DIO18
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
17DIO17R/W0hInterrupt mask for DIO17
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
16DIO16R/W0hInterrupt mask for DIO16
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
15DIO15R/W0hInterrupt mask for DIO15
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
14DIO14R/W0hInterrupt mask for DIO14
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
13DIO13R/W0hInterrupt mask for DIO13
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
12DIO12R/W0hInterrupt mask for DIO12
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
11DIO11R/W0hInterrupt mask for DIO11
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
10DIO10R/W0hInterrupt mask for DIO10
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
9DIO9R/W0hInterrupt mask for DIO9
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
8DIO8R/W0hInterrupt mask for DIO8
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
7DIO7R/W0hInterrupt mask for DIO7
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
6DIO6R/W0hInterrupt mask for DIO6
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5DIO5R/W0hInterrupt mask for DIO5
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
4DIO4R/W0hInterrupt mask for DIO4
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
3DIO3R/W0hInterrupt mask for DIO3
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
2DIO2R/W0hInterrupt mask for DIO2
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
1DIO1R/W0hInterrupt mask for DIO1
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0DIO0R/W0hInterrupt mask for DIO0
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask

22.10.4 RIS Register (Offset = 4Ch) [Reset = 00000000h]

RIS is shown in Table 22-50.

Return to the Summary Table.

Raw interrupt flag for DIO pins

Table 22-50 RIS Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30R0hRaw interrupt flag for DIO30
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
29DIO29R0hRaw interrupt flag for DIO29
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
28DIO28R0hRaw interrupt flag for DIO28
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
27DIO27R0hRaw interrupt flag for DIO27
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
26DIO26R0hRaw interrupt flag for DIO26
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
25DIO25R0hRaw interrupt flag for DIO25
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
24DIO24R0hRaw interrupt flag for DIO24
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
23DIO23R0hRaw interrupt flag for DIO23
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
22DIO22R0hRaw interrupt flag for DIO22
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
21DIO21R0hRaw interrupt flag for DIO21
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
20DIO20R0hRaw interrupt flag for DIO20
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
19DIO19R0hRaw interrupt flag for DIO19
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
18DIO18R0hRaw interrupt flag for DIO18
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
17DIO17R0hRaw interrupt flag for DIO17
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
16DIO16R0hRaw interrupt flag for DIO16
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
15DIO15R0hRaw interrupt flag for DIO15
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
14DIO14R0hRaw interrupt flag for DIO14
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
13DIO13R0hRaw interrupt flag for DIO13
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
12DIO12R0hRaw interrupt flag for DIO12
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
11DIO11R0hRaw interrupt flag for DIO11
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
10DIO10R0hRaw interrupt flag for DIO10
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
9DIO9R0hRaw interrupt flag for DIO9
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
8DIO8R0hRaw interrupt flag for DIO8
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
7DIO7R0hRaw interrupt flag for DIO7
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6DIO6R0hRaw interrupt flag for DIO6
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5DIO5R0hRaw interrupt flag for DIO5
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4DIO4R0hRaw interrupt flag for DIO4
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3DIO3R0hRaw interrupt flag for DIO3
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2DIO2R0hRaw interrupt flag for DIO2
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1DIO1R0hRaw interrupt flag for DIO1
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0DIO0R0hRaw interrupt flag for DIO0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

22.10.5 MIS Register (Offset = 54h) [Reset = 00000000h]

MIS is shown in Table 22-51.

Return to the Summary Table.

Masked interrupt flag for DIO pins

Table 22-51 MIS Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30R0hMasked interrupt flag for DIO30
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
29DIO29R0hMasked interrupt flag for DIO29
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
28DIO28R0hMasked interrupt flag for DIO28
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
27DIO27R0hMasked interrupt flag for DIO27
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
26DIO26R0hMasked interrupt flag for DIO26
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
25DIO25R0hMasked interrupt flag for DIO25
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
24DIO24R0hMasked interrupt flag for DIO24
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
23DIO23R0hMasked interrupt flag for DIO23
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
22DIO22R0hMasked interrupt flag for DIO22
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
21DIO21R0hMasked interrupt flag for DIO21
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
20DIO20R0hMasked interrupt flag for DIO20
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
19DIO19R0hMasked interrupt flag for DIO19
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
18DIO18R0hMasked interrupt flag for DIO18
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
17DIO17R0hMasked interrupt flag for DIO17
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
16DIO16R0hMasked interrupt flag for DIO16
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
15DIO15R0hMasked interrupt flag for DIO15
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
14DIO14R0hMasked interrupt flag for DIO14
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
13DIO13R0hMasked interrupt flag for DIO13
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
12DIO12R0hMasked interrupt flag for DIO12
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
11DIO11R0hMasked interrupt flag for DIO11
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
10DIO10R0hMasked interrupt flag for DIO10
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
9DIO9R0hMasked interrupt flag for DIO9
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
8DIO8R0hMasked interrupt flag for DIO8
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
7DIO7R0hMasked interrupt flag for DIO7
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6DIO6R0hMasked interrupt flag for DIO6
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5DIO5R0hMasked interrupt flag for DIO5
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4DIO4R0hMasked interrupt flag for DIO4
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3DIO3R0hMasked interrupt flag for DIO3
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2DIO2R0hMasked interrupt flag for DIO2
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1DIO1R0hMasked interrupt flag for DIO1
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0DIO0R0hMasked interrupt flag for DIO0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

22.10.6 ISET Register (Offset = 5Ch) [Reset = 00000000h]

ISET is shown in Table 22-52.

Return to the Summary Table.

Set interrupt flag in RIS by writing a one

Table 22-52 ISET Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hSet DIO30 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
29DIO29W0hSet DIO29 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
28DIO28W0hSet DIO28 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
27DIO27W0hSet DIO27 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
26DIO26W0hSet DIO26 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
25DIO25W0hSet DIO25 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
24DIO24W0hSet DIO24 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
23DIO23W0hSet DIO23 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
22DIO22W0hSet DIO22 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
21DIO21W0hSet DIO21 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
20DIO20W0hSet DIO20 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
19DIO19W0hSet DIO19 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
18DIO18W0hSet DIO18 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
17DIO17W0hSet DIO17 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
16DIO16W0hSet DIO16 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
15DIO15W0hSet DIO15 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
14DIO14W0hSet DIO14 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
13DIO13W0hSet DIO13 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
12DIO12W0hSet DIO12 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
11DIO11W0hSet DIO11 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
10DIO10W0hSet DIO10 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
9DIO9W0hSet DIO9 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
8DIO8W0hSet DIO8 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
7DIO7W0hSet DIO7 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
6DIO6W0hSet DIO6 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
5DIO5W0hSet DIO5 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
4DIO4W0hSet DIO4 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
3DIO3W0hSet DIO3 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
2DIO2W0hSet DIO2 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
1DIO1W0hSet DIO1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
0DIO0W0hSet DIO0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt

22.10.7 ICLR Register (Offset = 64h) [Reset = 00000000h]

ICLR is shown in Table 22-53.

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Clear interrupt flag in RIS by writing a one

Table 22-53 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hClears DIO30 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
29DIO29W0hClears DIO29 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
28DIO28W0hClears DIO28 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
27DIO27W0hClears DIO27 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
26DIO26W0hClears DIO26 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
25DIO25W0hClears DIO25 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
24DIO24W0hClears DIO24 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
23DIO23W0hClears DIO23 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
22DIO22W0hClears DIO22 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
21DIO21W0hClears DIO21 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
20DIO20W0hClears DIO20 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
19DIO19W0hClears DIO19 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
18DIO18W0hClears DIO18 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
17DIO17W0hClears DIO17 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
16DIO16W0hClears DIO16 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
15DIO15W0hClears DIO15 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
14DIO14W0hClears DIO14 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
13DIO13W0hClears DIO13 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
12DIO12W0hClears DIO12 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
11DIO11W0hClears DIO11 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
10DIO10W0hClears DIO10 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
9DIO9W0hClears DIO9 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
8DIO8W0hClears DIO8 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
7DIO7W0hClears DIO7 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
6DIO6W0hClears DIO6 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
5DIO5W0hClears DIO5 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
4DIO4W0hClears DIO4 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
3DIO3W0hClears DIO3 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
2DIO2W0hClears DIO2 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
1DIO1W0hClears DIO1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
0DIO0W0hClears DIO0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt

22.10.8 IMSET Register (Offset = 6Ch) [Reset = 00000000h]

IMSET is shown in Table 22-54.

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Set interrupt mask in IMASK by writing a one

Table 22-54 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hSets DIO30 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
29DIO29W0hSets DIO29 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
28DIO28W0hSets DIO28 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
27DIO27W0hSets DIO27 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
26DIO26W0hSets DIO26 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
25DIO25W0hSets DIO25 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
24DIO24W0hSets DIO24 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
23DIO23W0hSets DIO23 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
22DIO22W0hSets DIO22 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
21DIO21W0hSets DIO21 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
20DIO20W0hSets DIO20 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
19DIO19W0hSets DIO19 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
18DIO18W0hSets DIO18 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
17DIO17W0hSets DIO17 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
16DIO16W0hSets DIO16 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
15DIO15W0hSets DIO15 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
14DIO14W0hSets DIO14 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
13DIO13W0hSets DIO13 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
12DIO12W0hSets DIO12 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
11DIO11W0hSets DIO11 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
10DIO10W0hSets DIO10 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
9DIO9W0hSets DIO9 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
8DIO8W0hSets DIO8 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
7DIO7W0hSets DIO7 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
6DIO6W0hSets DIO6 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
5DIO5W0hSets DIO5 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
4DIO4W0hSets DIO4 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
3DIO3W0hSets DIO3 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
2DIO2W0hSets DIO2 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
1DIO1W0hSets DIO1 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
0DIO0W0hSets DIO0 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask

22.10.9 IMCLR Register (Offset = 74h) [Reset = 00000000h]

IMCLR is shown in Table 22-55.

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Clear interrupt mask in IMASK by writing a one

Table 22-55 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hClears DIO30 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
29DIO29W0hClears DIO29 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
28DIO28W0hClears DIO28 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
27DIO27W0hClears DIO27 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
26DIO26W0hClears DIO26 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
25DIO25W0hClears DIO25 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
24DIO24W0hClears DIO24 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
23DIO23W0hClears DIO23 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
22DIO22W0hClears DIO22 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
21DIO21W0hClears DIO21 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
20DIO20W0hClears DIO20 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
19DIO19W0hClears DIO19 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
18DIO18W0hClears DIO18 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
17DIO17W0hClears DIO17 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
16DIO16W0hClears DIO16 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
15DIO15W0hClears DIO15 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
14DIO14W0hClears DIO14 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
13DIO13W0hClears DIO13 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
12DIO12W0hClears DIO12 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
11DIO11W0hClears DIO11 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
10DIO10W0hClears DIO10 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
9DIO9W0hClears DIO9 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
8DIO8W0hClears DIO8 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
7DIO7W0hClears DIO7 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
6DIO6W0hClears DIO6 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
5DIO5W0hClears DIO5 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
4DIO4W0hClears DIO4 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
3DIO3W0hClears DIO3 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
2DIO2W0hClears DIO2 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
1DIO1W0hClears DIO1 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
0DIO0W0hClears DIO0 in IMASK
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask

22.10.10 DOUT3_0 Register (Offset = 100h) [Reset = 00000000h]

DOUT3_0 is shown in Table 22-56.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[3:0] bits.

Table 22-56 DOUT3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3R/W0hData output for DIO3
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO2R/W0hData output for DIO2
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO1R/W0hData output for DIO1
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO0R/W0hData output for DIO0
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.11 DOUT7_4 Register (Offset = 104h) [Reset = 00000000h]

DOUT7_4 is shown in Table 22-57.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[7:4] bits

Table 22-57 DOUT7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7R/W0hData output for DIO7
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO6R/W0hData output for DIO6
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO5R/W0hData output for DIO5
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO4R/W0hData output for DIO4
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.12 DOUT11_8 Register (Offset = 108h) [Reset = 00000000h]

DOUT11_8 is shown in Table 22-58.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[11:8] bits

Table 22-58 DOUT11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11R/W0hData output for DIO11
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO10R/W0hData output for DIO10
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO9R/W0hData output for DIO9
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO8R/W0hData output for DIO8
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.13 DOUT15_12 Register (Offset = 10Ch) [Reset = 00000000h]

DOUT15_12 is shown in Table 22-59.

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Alias register for byte access to DOUT31_0[15:12] bits

Table 22-59 DOUT15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15R/W0hData output for DIO15
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO14R/W0hData output for DIO14
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO13R/W0hData output for DIO13
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO12R/W0hData output for DIO12
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.14 DOUT19_16 Register (Offset = 110h) [Reset = 00000000h]

DOUT19_16 is shown in Table 22-60.

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Alias register for byte access to DOUT31_0[19:16] bits

Table 22-60 DOUT19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19R/W0hData output for DIO19
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO18R/W0hData output for DIO18
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO17R/W0hData output for DIO17
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO16R/W0hData output for DIO16
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.15 DOUT23_20 Register (Offset = 114h) [Reset = 00000000h]

DOUT23_20 is shown in Table 22-61.

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Alias register for byte access to DOUT31_0[23:20] bits

Table 22-61 DOUT23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23R/W0hData output for DIO23
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO22R/W0hData output for DIO22
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO21R/W0hData output for DIO21
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO20R/W0hData output for DIO20
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.16 DOUT27_24 Register (Offset = 118h) [Reset = 00000000h]

DOUT27_24 is shown in Table 22-62.

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Alias register for byte access to DOUT31_0[27:24] bits

Table 22-62 DOUT27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO27R/W0hData output for DIO27
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO26R/W0hData output for DIO26
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO25R/W0hData output for DIO25
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO24R/W0hData output for DIO24
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.17 DOUT31_28 Register (Offset = 11Ch) [Reset = 00000000h]

DOUT31_28 is shown in Table 22-63.

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Alias register for byte access to DOUT31_0[31:28] bits

Table 22-63 DOUT31_28 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16DIO30R/W0hData output for DIO30
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO29R/W0hData output for DIO29
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO28R/W0hData output for DIO28
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.18 DOUT31_0 Register (Offset = 200h) [Reset = 00000000h]

DOUT31_0 is shown in Table 22-64.

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Data Output for DIO 31 to 0 pins.

Table 22-64 DOUT31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30R/W0hData output for DIO30
  • 0h = Output is set to 0
  • 1h = Output is set to 1
29DIO29R/W0hData output for DIO29
  • 0h = Output is set to 0
  • 1h = Output is set to 1
28DIO28R/W0hData output for DIO28
  • 0h = Output is set to 0
  • 1h = Output is set to 1
27DIO27R/W0hData output for DIO27
  • 0h = Output is set to 0
  • 1h = Output is set to 1
26DIO26R/W0hData output for DIO26
  • 0h = Output is set to 0
  • 1h = Output is set to 1
25DIO25R/W0hData output for DIO25
  • 0h = Output is set to 0
  • 1h = Output is set to 1
24DIO24R/W0hData output for DIO24
  • 0h = Output is set to 0
  • 1h = Output is set to 1
23DIO23R/W0hData output for DIO23
  • 0h = Output is set to 0
  • 1h = Output is set to 1
22DIO22R/W0hData output for DIO22
  • 0h = Output is set to 0
  • 1h = Output is set to 1
21DIO21R/W0hData output for DIO21
  • 0h = Output is set to 0
  • 1h = Output is set to 1
20DIO20R/W0hData output for DIO20
  • 0h = Output is set to 0
  • 1h = Output is set to 1
19DIO19R/W0hData output for DIO19
  • 0h = Output is set to 0
  • 1h = Output is set to 1
18DIO18R/W0hData output for DIO18
  • 0h = Output is set to 0
  • 1h = Output is set to 1
17DIO17R/W0hData output for DIO17
  • 0h = Output is set to 0
  • 1h = Output is set to 1
16DIO16R/W0hData output for DIO16
  • 0h = Output is set to 0
  • 1h = Output is set to 1
15DIO15R/W0hData output for DIO15
  • 0h = Output is set to 0
  • 1h = Output is set to 1
14DIO14R/W0hData output for DIO14
  • 0h = Output is set to 0
  • 1h = Output is set to 1
13DIO13R/W0hData output for DIO13
  • 0h = Output is set to 0
  • 1h = Output is set to 1
12DIO12R/W0hData output for DIO12
  • 0h = Output is set to 0
  • 1h = Output is set to 1
11DIO11R/W0hData output for DIO11
  • 0h = Output is set to 0
  • 1h = Output is set to 1
10DIO10R/W0hData output for DIO10
  • 0h = Output is set to 0
  • 1h = Output is set to 1
9DIO9R/W0hData output for DIO9
  • 0h = Output is set to 0
  • 1h = Output is set to 1
8DIO8R/W0hData output for DIO8
  • 0h = Output is set to 0
  • 1h = Output is set to 1
7DIO7R/W0hData output for DIO7
  • 0h = Output is set to 0
  • 1h = Output is set to 1
6DIO6R/W0hData output for DIO6
  • 0h = Output is set to 0
  • 1h = Output is set to 1
5DIO5R/W0hData output for DIO5
  • 0h = Output is set to 0
  • 1h = Output is set to 1
4DIO4R/W0hData output for DIO4
  • 0h = Output is set to 0
  • 1h = Output is set to 1
3DIO3R/W0hData output for DIO3
  • 0h = Output is set to 0
  • 1h = Output is set to 1
2DIO2R/W0hData output for DIO2
  • 0h = Output is set to 0
  • 1h = Output is set to 1
1DIO1R/W0hData output for DIO1
  • 0h = Output is set to 0
  • 1h = Output is set to 1
0DIO0R/W0hData output for DIO0
  • 0h = Output is set to 0
  • 1h = Output is set to 1

22.10.19 DOUTSET31_0 Register (Offset = 210h) [Reset = 00000000h]

DOUTSET31_0 is shown in Table 22-65.

Return to the Summary Table.

Alias regiser to set the corresponding bits of DOUT31_0 register.

Table 22-65 DOUTSET31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hSet bit DOUT31_0.DIO30
  • 0h = No effect
  • 1h = Set
29DIO29W0hSet bit DOUT31_0.DIO29
  • 0h = No effect
  • 1h = Set
28DIO28W0hSet bit DOUT31_0.DIO28
  • 0h = No effect
  • 1h = Set
27DIO27W0hSet bit DOUT31_0.DIO27
  • 0h = No effect
  • 1h = Set
26DIO26W0hSet bit DOUT31_0.DIO26
  • 0h = No effect
  • 1h = Set
25DIO25W0hSet bit DOUT31_0.DIO25
  • 0h = No effect
  • 1h = Set
24DIO24W0hSet bit DOUT31_0.DIO24
  • 0h = No effect
  • 1h = Set
23DIO23W0hSet bit DOUT31_0.DIO23
  • 0h = No effect
  • 1h = Set
22DIO22W0hSet bit DOUT31_0.DIO22
  • 0h = No effect
  • 1h = Set
21DIO21W0hSet bit DOUT31_0.DIO21
  • 0h = No effect
  • 1h = Set
20DIO20W0hSet bit DOUT31_0.DIO20
  • 0h = No effect
  • 1h = Set
19DIO19W0hSet bit DOUT31_0.DIO19
  • 0h = No effect
  • 1h = Set
18DIO18W0hSet bit DOUT31_0.DIO18
  • 0h = No effect
  • 1h = Set
17DIO17W0hSet bit DOUT31_0.DIO17
  • 0h = No effect
  • 1h = Set
16DIO16W0hSet bit DOUT31_0.DIO16
  • 0h = No effect
  • 1h = Set
15DIO15W0hSet bit DOUT31_0.DIO15
  • 0h = No effect
  • 1h = Set
14DIO14W0hSet bit DOUT31_0.DIO14
  • 0h = No effect
  • 1h = Set
13DIO13W0hSet bit DOUT31_0.DIO13
  • 0h = No effect
  • 1h = Set
12DIO12W0hSet bit DOUT31_0.DIO12
  • 0h = No effect
  • 1h = Set
11DIO11W0hSet bit DOUT31_0.DIO11
  • 0h = No effect
  • 1h = Set
10DIO10W0hSet bit DOUT31_0.DIO10
  • 0h = No effect
  • 1h = Set
9DIO9W0hSet bit DOUT31_0.DIO9
  • 0h = No effect
  • 1h = Set
8DIO8W0hSet bit DOUT31_0.DIO8
  • 0h = No effect
  • 1h = Set
7DIO7W0hSet bit DOUT31_0.DIO7
  • 0h = No effect
  • 1h = Set
6DIO6W0hSet bit DOUT31_0.DIO6
  • 0h = No effect
  • 1h = Set
5DIO5W0hSet bit DOUT31_0.DIO5
  • 0h = No effect
  • 1h = Set
4DIO4W0hSet bit DOUT31_0.DIO4
  • 0h = No effect
  • 1h = Set
3DIO3W0hSet bit DOUT31_0.DIO3
  • 0h = No effect
  • 1h = Set
2DIO2W0hSet bit DOUT31_0.DIO2
  • 0h = No effect
  • 1h = Set
1DIO1W0hSet bit DOUT31_0.DIO1
  • 0h = No effect
  • 1h = Set
0DIO0W0hSet bit DOUT31_0.DIO0
  • 0h = No effect
  • 1h = Set

22.10.20 DOUTCLR31_0 Register (Offset = 220h) [Reset = 00000000h]

DOUTCLR31_0 is shown in Table 22-66.

Return to the Summary Table.

Alias regiser to clear the corresponding bits of DOUT31_0 register.

Table 22-66 DOUTCLR31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hClear bit DOUT31_0.DIO30
  • 0h = No effect
  • 1h = Clear
29DIO29W0hClear bit DOUT31_0.DIO29
  • 0h = No effect
  • 1h = Clear
28DIO28W0hClear bit DOUT31_0.DIO28
  • 0h = No effect
  • 1h = Clear
27DIO27W0hClear bit DOUT31_0.DIO27
  • 0h = No effect
  • 1h = Clear
26DIO26W0hClear bit DOUT31_0.DIO26
  • 0h = No effect
  • 1h = Clear
25DIO25W0hClear bit DOUT31_0.DIO25
  • 0h = No effect
  • 1h = Clear
24DIO24W0hClear bit DOUT31_0.DIO24
  • 0h = No effect
  • 1h = Clear
23DIO23W0hClear bit DOUT31_0.DIO23
  • 0h = No effect
  • 1h = Clear
22DIO22W0hClear bit DOUT31_0.DIO22
  • 0h = No effect
  • 1h = Clear
21DIO21W0hClear bit DOUT31_0.DIO21
  • 0h = No effect
  • 1h = Clear
20DIO20W0hClear bit DOUT31_0.DIO20
  • 0h = No effect
  • 1h = Clear
19DIO19W0hClear bit DOUT31_0.DIO19
  • 0h = No effect
  • 1h = Clear
18DIO18W0hClear bit DOUT31_0.DIO18
  • 0h = No effect
  • 1h = Clear
17DIO17W0hClear bit DOUT31_0.DIO17
  • 0h = No effect
  • 1h = Clear
16DIO16W0hClear bit DOUT31_0.DIO16
  • 0h = No effect
  • 1h = Clear
15DIO15W0hClear bit DOUT31_0.DIO15
  • 0h = No effect
  • 1h = Clear
14DIO14W0hClear bit DOUT31_0.DIO14
  • 0h = No effect
  • 1h = Clear
13DIO13W0hClear bit DOUT31_0.DIO13
  • 0h = No effect
  • 1h = Clear
12DIO12W0hClear bit DOUT31_0.DIO12
  • 0h = No effect
  • 1h = Clear
11DIO11W0hClear bit DOUT31_0.DIO11
  • 0h = No effect
  • 1h = Clear
10DIO10W0hClear bit DOUT31_0.DIO10
  • 0h = No effect
  • 1h = Clear
9DIO9W0hClear bit DOUT31_0.DIO9
  • 0h = No effect
  • 1h = Clear
8DIO8W0hClear bit DOUT31_0.DIO8
  • 0h = No effect
  • 1h = Clear
7DIO7W0hClear bit DOUT31_0.DIO7
  • 0h = No effect
  • 1h = Clear
6DIO6W0hClear bit DOUT31_0.DIO6
  • 0h = No effect
  • 1h = Clear
5DIO5W0hClear bit DOUT31_0.DIO5
  • 0h = No effect
  • 1h = Clear
4DIO4W0hClear bit DOUT31_0.DIO4
  • 0h = No effect
  • 1h = Clear
3DIO3W0hClear bit DOUT31_0.DIO3
  • 0h = No effect
  • 1h = Clear
2DIO2W0hClear bit DOUT31_0.DIO2
  • 0h = No effect
  • 1h = Clear
1DIO1W0hClear bit DOUT31_0.DIO1
  • 0h = No effect
  • 1h = Clear
0DIO0W0hClear bit DOUT31_0.DIO0
  • 0h = No effect
  • 1h = Clear

22.10.21 DOUTTGL31_0 Register (Offset = 230h) [Reset = 00000000h]

DOUTTGL31_0 is shown in Table 22-67.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0 register.

Table 22-67 DOUTTGL31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hToggles bit DOUT31_0.DIO30
  • 0h = No effect
  • 1h = Toggle
29DIO29W0hToggles bit DOUT31_0.DIO29
  • 0h = No effect
  • 1h = Toggle
28DIO28W0hToggles bit DOUT31_0.DIO28
  • 0h = No effect
  • 1h = Toggle
27DIO27W0hToggles bit DOUT31_0.DIO27
  • 0h = No effect
  • 1h = Toggle
26DIO26W0hToggles bit DOUT31_0.DIO26
  • 0h = No effect
  • 1h = Toggle
25DIO25W0hToggles bit DOUT31_0.DIO25
  • 0h = No effect
  • 1h = Toggle
24DIO24W0hToggles bit DOUT31_0.DIO24
  • 0h = No effect
  • 1h = Toggle
23DIO23W0hToggles bit DOUT31_0.DIO23
  • 0h = No effect
  • 1h = Toggle
22DIO22W0hToggles bit DOUT31_0.DIO22
  • 0h = No effect
  • 1h = Toggle
21DIO21W0hToggles bit DOUT31_0.DIO21
  • 0h = No effect
  • 1h = Toggle
20DIO20W0hToggles bit DOUT31_0.DIO20
  • 0h = No effect
  • 1h = Toggle
19DIO19W0hToggles bit DOUT31_0.DIO19
  • 0h = No effect
  • 1h = Toggle
18DIO18W0hToggles bit DOUT31_0.DIO18
  • 0h = No effect
  • 1h = Toggle
17DIO17W0hToggles bit DOUT31_0.DIO17
  • 0h = No effect
  • 1h = Toggle
16DIO16W0hToggles bit DOUT31_0.DIO16
  • 0h = No effect
  • 1h = Toggle
15DIO15W0hToggles bit DOUT31_0.DIO15
  • 0h = No effect
  • 1h = Toggle
14DIO14W0hToggles bit DOUT31_0.DIO14
  • 0h = No effect
  • 1h = Toggle
13DIO13W0hToggles bit DOUT31_0.DIO13
  • 0h = No effect
  • 1h = Toggle
12DIO12W0hToggles bit DOUT31_0.DIO12
  • 0h = No effect
  • 1h = Toggle
11DIO11W0hToggles bit DOUT31_0.DIO11
  • 0h = No effect
  • 1h = Toggle
10DIO10W0hToggles bit DOUT31_0.DIO10
  • 0h = No effect
  • 1h = Toggle
9DIO9W0hToggles bit DOUT31_0.DIO9
  • 0h = No effect
  • 1h = Toggle
8DIO8W0hToggles bit DOUT31_0.DIO8
  • 0h = No effect
  • 1h = Toggle
7DIO7W0hToggles bit DOUT31_0.DIO7
  • 0h = No effect
  • 1h = Toggle
6DIO6W0hToggles bit DOUT31_0.DIO6
  • 0h = No effect
  • 1h = Toggle
5DIO5W0hToggles bit DOUT31_0.DIO5
  • 0h = No effect
  • 1h = Toggle
4DIO4W0hToggles bit DOUT31_0.DIO4
  • 0h = No effect
  • 1h = Toggle
3DIO3W0hToggles bit DOUT31_0.DIO3
  • 0h = No effect
  • 1h = Toggle
2DIO2W0hToggles bit DOUT31_0.DIO2
  • 0h = No effect
  • 1h = Toggle
1DIO1W0hToggles bit DOUT31_0.DIO1
  • 0h = No effect
  • 1h = Toggle
0DIO0W0hToggles bit DOUT31_0.DIO0
  • 0h = No effect
  • 1h = Toggle

22.10.22 DOUTTGL3_0 Register (Offset = 300h) [Reset = 00000000h]

DOUTTGL3_0 is shown in Table 22-68.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[3:0] register.

Table 22-68 DOUTTGL3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3W0hToggles bit DOUT31_0.DIO3
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO2W0hToggles bit DOUT31_0.DIO2
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO1W0hToggles bit DOUT31_0.DIO1
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO0W0hToggles bit DOUT31_0.DIO0
  • 0h = No effect
  • 1h = Toggle

22.10.23 DOUTTGL7_4 Register (Offset = 304h) [Reset = 00000000h]

DOUTTGL7_4 is shown in Table 22-69.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[7:4] register.

Table 22-69 DOUTTGL7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7W0hToggles bit DOUT31_0.DIO7
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO6W0hToggles bit DOUT31_0.DIO6
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO5W0hToggles bit DOUT31_0.DIO5
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO4W0hToggles bit DOUT31_0.DIO4
  • 0h = No effect
  • 1h = Toggle

22.10.24 DOUTTGL11_8 Register (Offset = 308h) [Reset = 00000000h]

DOUTTGL11_8 is shown in Table 22-70.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[11:8] register.

Table 22-70 DOUTTGL11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11W0hToggles bit DOUT31_0.DIO11
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO10W0hToggles bit DOUT31_0.DIO10
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO9W0hToggles bit DOUT31_0.DIO9
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO8W0hToggles bit DOUT31_0.DIO8
  • 0h = No effect
  • 1h = Toggle

22.10.25 DOUTTGL15_12 Register (Offset = 30Ch) [Reset = 00000000h]

DOUTTGL15_12 is shown in Table 22-71.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[15:12] register.

Table 22-71 DOUTTGL15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15W0hToggles bit DOUT31_0.DIO15
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO14W0hToggles bit DOUT31_0.DIO14
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO13W0hToggles bit DOUT31_0.DIO13
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO12W0hToggles bit DOUT31_0.DIO12
  • 0h = No effect
  • 1h = Toggle

22.10.26 DOUTTGL19_16 Register (Offset = 310h) [Reset = 00000000h]

DOUTTGL19_16 is shown in Table 22-72.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[19:16] register.

Table 22-72 DOUTTGL19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19W0hToggles bit DOUT31_0.DIO19
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO18W0hToggles bit DOUT31_0.DIO18
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO17W0hToggles bit DOUT31_0.DIO17
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO16W0hToggles bit DOUT31_0.DIO16
  • 0h = No effect
  • 1h = Toggle

22.10.27 DOUTTGL23_20 Register (Offset = 314h) [Reset = 00000000h]

DOUTTGL23_20 is shown in Table 22-73.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[23:20] register.

Table 22-73 DOUTTGL23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23W0hToggles bit DOUT31_0.DIO23
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO22W0hToggles bit DOUT31_0.DIO22
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO21W0hToggles bit DOUT31_0.DIO21
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO20W0hToggles bit DOUT31_0.DIO20
  • 0h = No effect
  • 1h = Toggle

22.10.28 DOUTTGL27_24 Register (Offset = 318h) [Reset = 00000000h]

DOUTTGL27_24 is shown in Table 22-74.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[27:24] register.

Table 22-74 DOUTTGL27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO27W0hToggles bit DOUT31_0.DIO27
  • 0h = No effect
  • 1h = Toggle
23-17RESERVEDR0hReserved
16DIO26W0hToggles bit DOUT31_0.DIO26
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO25W0hToggles bit DOUT31_0.DIO25
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO24W0hToggles bit DOUT31_0.DIO24
  • 0h = No effect
  • 1h = Toggle

22.10.29 DOUTTGL31_28 Register (Offset = 31Ch) [Reset = 00000000h]

DOUTTGL31_28 is shown in Table 22-75.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[31:28] register.

Table 22-75 DOUTTGL31_28 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16DIO30W0hToggles bit DOUT31_0.DIO30
  • 0h = No effect
  • 1h = Toggle
15-9RESERVEDR0hReserved
8DIO29W0hToggles bit DOUT31_0.DIO29
  • 0h = No effect
  • 1h = Toggle
7-1RESERVEDR0hReserved
0DIO28W0hToggles bit DOUT31_0.DIO28
  • 0h = No effect
  • 1h = Toggle

22.10.30 DOE3_0 Register (Offset = 400h) [Reset = 00000000h]

DOE3_0 is shown in Table 22-76.

Return to the Summary Table.

Alias register for byte access to DOE31_0[3:0] bits.

Table 22-76 DOE3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3R/W0hData output enable for DIO3
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO2R/W0hData output enable for DIO2
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO1R/W0hData output enable for DIO1
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO0R/W0hData output enable for DIO0
  • 0h = Output disabled
  • 1h = Output enabled

22.10.31 DOE7_4 Register (Offset = 404h) [Reset = 00000000h]

DOE7_4 is shown in Table 22-77.

Return to the Summary Table.

Alias register for byte access to DOE31_0[7:4] bits.

Table 22-77 DOE7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7R/W0hData output enable for DIO7
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO6R/W0hData output enable for DIO6
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO5R/W0hData output enable for DIO5
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO4R/W0hData output enable for DIO4
  • 0h = Output disabled
  • 1h = Output enabled

22.10.32 DOE11_8 Register (Offset = 408h) [Reset = 00000000h]

DOE11_8 is shown in Table 22-78.

Return to the Summary Table.

Alias register for byte access to DOE31_0[11:8] bits.

Table 22-78 DOE11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11R/W0hData output enable for DIO11
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO10R/W0hData output enable for DIO10
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO9R/W0hData output enable for DIO9
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO8R/W0hData output enable for DIO8
  • 0h = Output disabled
  • 1h = Output enabled

22.10.33 DOE15_12 Register (Offset = 40Ch) [Reset = 00000000h]

DOE15_12 is shown in Table 22-79.

Return to the Summary Table.

Alias register for byte access to DOE31_0[15:12] bits.

Table 22-79 DOE15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15R/W0hData output enable for DIO15
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO14R/W0hData output enable for DIO14
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO13R/W0hData output enable for DIO13
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO12R/W0hData output enable for DIO12
  • 0h = Output disabled
  • 1h = Output enabled

22.10.34 DOE19_16 Register (Offset = 410h) [Reset = 00000000h]

DOE19_16 is shown in Table 22-80.

Return to the Summary Table.

Alias register for byte access to DOE31_0[19:16] bits.

Table 22-80 DOE19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19R/W0hData output enable for DIO19
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO18R/W0hData output enable for DIO18
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO17R/W0hData output enable for DIO17
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO16R/W0hData output enable for DIO16
  • 0h = Output disabled
  • 1h = Output enabled

22.10.35 DOE23_20 Register (Offset = 414h) [Reset = 00000000h]

DOE23_20 is shown in Table 22-81.

Return to the Summary Table.

Alias register for byte access to DOE31_0[23:20] bits.

Table 22-81 DOE23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23R/W0hData output enable for DIO23
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO22R/W0hData output enable for DIO22
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO21R/W0hData output enable for DIO21
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO20R/W0hData output enable for DIO20
  • 0h = Output disabled
  • 1h = Output enabled

22.10.36 DOE27_24 Register (Offset = 418h) [Reset = 00000000h]

DOE27_24 is shown in Table 22-82.

Return to the Summary Table.

Alias register for byte access to DOE31_0[24:27] bits.

Table 22-82 DOE27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO27R/W0hData output enable for DIO27
  • 0h = Output disabled
  • 1h = Output enabled
23-17RESERVEDR0hReserved
16DIO26R/W0hData output enable for DIO26
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO25R/W0hData output enable for DIO25
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO24R/W0hData output enable for DIO24
  • 0h = Output disabled
  • 1h = Output enabled

22.10.37 DOE31_28 Register (Offset = 41Ch) [Reset = 00000000h]

DOE31_28 is shown in Table 22-83.

Return to the Summary Table.

Alias register for byte access to DOE31_0[31:28] bits.

Table 22-83 DOE31_28 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16DIO30R/W0hData output enable for DIO30
  • 0h = Output disabled
  • 1h = Output enabled
15-9RESERVEDR0hReserved
8DIO29R/W0hData output enable for DIO29
  • 0h = Output disabled
  • 1h = Output enabled
7-1RESERVEDR0hReserved
0DIO28R/W0hData output enable for DIO28
  • 0h = Output disabled
  • 1h = Output enabled

22.10.38 DOE31_0 Register (Offset = 500h) [Reset = 00000000h]

DOE31_0 is shown in Table 22-84.

Return to the Summary Table.

Data output enable for DIO 31 to 0 pins.

Table 22-84 DOE31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30R/W0hData output enable for DIO30
  • 0h = Output disabled
  • 1h = Output enabled
29DIO29R/W0hData output enable for DIO29
  • 0h = Output disabled
  • 1h = Output enabled
28DIO28R/W0hData output enable for DIO28
  • 0h = Output disabled
  • 1h = Output enabled
27DIO27R/W0hData output enable for DIO27
  • 0h = Output disabled
  • 1h = Output enabled
26DIO26R/W0hData output enable for DIO26
  • 0h = Output disabled
  • 1h = Output enabled
25DIO25R/W0hData output enable for DIO25
  • 0h = Output disabled
  • 1h = Output enabled
24DIO24R/W0hData output enable for DIO24
  • 0h = Output disabled
  • 1h = Output enabled
23DIO23R/W0hData output enable for DIO23
  • 0h = Output disabled
  • 1h = Output enabled
22DIO22R/W0hData output enable for DIO22
  • 0h = Output disabled
  • 1h = Output enabled
21DIO21R/W0hData output enable for DIO21
  • 0h = Output disabled
  • 1h = Output enabled
20DIO20R/W0hData output enable for DIO20
  • 0h = Output disabled
  • 1h = Output enabled
19DIO19R/W0hData output enable for DIO19
  • 0h = Output disabled
  • 1h = Output enabled
18DIO18R/W0hData output enable for DIO18
  • 0h = Output disabled
  • 1h = Output enabled
17DIO17R/W0hData output enable for DIO17
  • 0h = Output disabled
  • 1h = Output enabled
16DIO16R/W0hData output enable for DIO16
  • 0h = Output disabled
  • 1h = Output enabled
15DIO15R/W0hData output enable for DIO15
  • 0h = Output disabled
  • 1h = Output enabled
14DIO14R/W0hData output enable for DIO14
  • 0h = Output disabled
  • 1h = Output enabled
13DIO13R/W0hData output enable for DIO13
  • 0h = Output disabled
  • 1h = Output enabled
12DIO12R/W0hData output enable for DIO12
  • 0h = Output disabled
  • 1h = Output enabled
11DIO11R/W0hData output enable for DIO11
  • 0h = Output disabled
  • 1h = Output enabled
10DIO10R/W0hData output enable for DIO10
  • 0h = Output disabled
  • 1h = Output enabled
9DIO9R/W0hData output enable for DIO9
  • 0h = Output disabled
  • 1h = Output enabled
8DIO8R/W0hData output enable for DIO8
  • 0h = Output disabled
  • 1h = Output enabled
7DIO7R/W0hData output enable for DIO7
  • 0h = Output disabled
  • 1h = Output enabled
6DIO6R/W0hData output enable for DIO6
  • 0h = Output disabled
  • 1h = Output enabled
5DIO5R/W0hData output enable for DIO5
  • 0h = Output disabled
  • 1h = Output enabled
4DIO4R/W0hData output enable for DIO4
  • 0h = Output disabled
  • 1h = Output enabled
3DIO3R/W0hData output enable for DIO3
  • 0h = Output disabled
  • 1h = Output enabled
2DIO2R/W0hData output enable for DIO2
  • 0h = Output disabled
  • 1h = Output enabled
1DIO1R/W0hData output enable for DIO1
  • 0h = Output disabled
  • 1h = Output enabled
0DIO0R/W0hData output enable for DIO0
  • 0h = Output disabled
  • 1h = Output enabled

22.10.39 DOESET31_0 Register (Offset = 510h) [Reset = 00000000h]

DOESET31_0 is shown in Table 22-85.

Return to the Summary Table.

Alias regiser to set the corresponding bits of DOE31_0 register.

Table 22-85 DOESET31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hSets bit DOE31_0.DIO30
  • 0h = No effect
  • 1h = Set
29DIO29W0hSets bit DOE31_0.DIO29
  • 0h = No effect
  • 1h = Set
28DIO28W0hSets bit DOE31_0.DIO28
  • 0h = No effect
  • 1h = Set
27DIO27W0hSets bit DOE31_0.DIO27
  • 0h = No effect
  • 1h = Set
26DIO26W0hSets bit DOE31_0.DIO26
  • 0h = No effect
  • 1h = Set
25DIO25W0hSets bit DOE31_0.DIO25
  • 0h = No effect
  • 1h = Set
24DIO24W0hSets bit DOE31_0.DIO24
  • 0h = No effect
  • 1h = Set
23DIO23W0hSets bit DOE31_0.DIO23
  • 0h = No effect
  • 1h = Set
22DIO22W0hSets bit DOE31_0.DIO22
  • 0h = No effect
  • 1h = Set
21DIO21W0hSets bit DOE31_0.DIO21
  • 0h = No effect
  • 1h = Set
20DIO20W0hSets bit DOE31_0.DIO20
  • 0h = No effect
  • 1h = Set
19DIO19W0hSets bit DOE31_0.DIO19
  • 0h = No effect
  • 1h = Set
18DIO18W0hSets bit DOE31_0.DIO18
  • 0h = No effect
  • 1h = Set
17DIO17W0hSets bit DOE31_0.DIO17
  • 0h = No effect
  • 1h = Set
16DIO16W0hSets bit DOE31_0.DIO16
  • 0h = No effect
  • 1h = Set
15DIO15W0hSets bit DOE31_0.DIO15
  • 0h = No effect
  • 1h = Set
14DIO14W0hSets bit DOE31_0.DIO14
  • 0h = No effect
  • 1h = Set
13DIO13W0hSets bit DOE31_0.DIO13
  • 0h = No effect
  • 1h = Set
12DIO12W0hSets bit DOE31_0.DIO12
  • 0h = No effect
  • 1h = Set
11DIO11W0hSets bit DOE31_0.DIO11
  • 0h = No effect
  • 1h = Set
10DIO10W0hSets bit DOE31_0.DIO10
  • 0h = No effect
  • 1h = Set
9DIO9W0hSets bit DOE31_0.DIO9
  • 0h = No effect
  • 1h = Set
8DIO8W0hSets bit DOE31_0.DIO8
  • 0h = No effect
  • 1h = Set
7DIO7W0hSets bit DOE31_0.DIO7
  • 0h = No effect
  • 1h = Set
6DIO6W0hSets bit DOE31_0.DIO6
  • 0h = No effect
  • 1h = Set
5DIO5W0hSets bit DOE31_0.DIO5
  • 0h = No effect
  • 1h = Set
4DIO4W0hSets bit DOE31_0.DIO4
  • 0h = No effect
  • 1h = Set
3DIO3W0hSets bit DOE31_0.DIO3
  • 0h = No effect
  • 1h = Set
2DIO2W0hSets bit DOE31_0.DIO2
  • 0h = No effect
  • 1h = Set
1DIO1W0hSets bit DOE31_0.DIO1
  • 0h = No effect
  • 1h = Set
0DIO0W0hSets bit DOE31_0.DIO0
  • 0h = No effect
  • 1h = Set

22.10.40 DOECLR31_0 Register (Offset = 520h) [Reset = 00000000h]

DOECLR31_0 is shown in Table 22-86.

Return to the Summary Table.

Alias regiser to clear the corresponding bits of DOE31_0 register.

Table 22-86 DOECLR31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hClears bit DOE31_0.DIO30
  • 0h = No effect
  • 1h = Clear
29DIO29W0hClears bit DOE31_0.DIO29
  • 0h = No effect
  • 1h = Clear
28DIO28W0hClears bit DOE31_0.DIO28
  • 0h = No effect
  • 1h = Clear
27DIO27W0hClears bit DOE31_0.DIO27
  • 0h = No effect
  • 1h = Clear
26DIO26W0hClears bit DOE31_0.DIO26
  • 0h = No effect
  • 1h = Clear
25DIO25W0hClears bit DOE31_0.DIO25
  • 0h = No effect
  • 1h = Clear
24DIO24W0hClears bit DOE31_0.DIO24
  • 0h = No effect
  • 1h = Clear
23DIO23W0hClears bit DOE31_0.DIO23
  • 0h = No effect
  • 1h = Clear
22DIO22W0hClears bit DOE31_0.DIO22
  • 0h = No effect
  • 1h = Clear
21DIO21W0hClears bit DOE31_0.DIO21
  • 0h = No effect
  • 1h = Clear
20DIO20W0hClears bit DOE31_0.DIO20
  • 0h = No effect
  • 1h = Clear
19DIO19W0hClears bit DOE31_0.DIO19
  • 0h = No effect
  • 1h = Clear
18DIO18W0hClears bit DOE31_0.DIO18
  • 0h = No effect
  • 1h = Clear
17DIO17W0hClears bit DOE31_0.DIO17
  • 0h = No effect
  • 1h = Clear
16DIO16W0hClears bit DOE31_0.DIO16
  • 0h = No effect
  • 1h = Clear
15DIO15W0hClears bit DOE31_0.DIO15
  • 0h = No effect
  • 1h = Clear
14DIO14W0hClears bit DOE31_0.DIO14
  • 0h = No effect
  • 1h = Clear
13DIO13W0hClears bit DOE31_0.DIO13
  • 0h = No effect
  • 1h = Clear
12DIO12W0hClears bit DOE31_0.DIO12
  • 0h = No effect
  • 1h = Clear
11DIO11W0hClears bit DOE31_0.DIO11
  • 0h = No effect
  • 1h = Clear
10DIO10W0hClears bit DOE31_0.DIO10
  • 0h = No effect
  • 1h = Clear
9DIO9W0hClears bit DOE31_0.DIO9
  • 0h = No effect
  • 1h = Clear
8DIO8W0hClears bit DOE31_0.DIO8
  • 0h = No effect
  • 1h = Clear
7DIO7W0hClears bit DOE31_0.DIO7
  • 0h = No effect
  • 1h = Clear
6DIO6W0hClears bit DOE31_0.DIO6
  • 0h = No effect
  • 1h = Clear
5DIO5W0hClears bit DOE31_0.DIO5
  • 0h = No effect
  • 1h = Clear
4DIO4W0hClears bit DOE31_0.DIO4
  • 0h = No effect
  • 1h = Clear
3DIO3W0hClears bit DOE31_0.DIO3
  • 0h = No effect
  • 1h = Clear
2DIO2W0hClears bit DOE31_0.DIO2
  • 0h = No effect
  • 1h = Clear
1DIO1W0hClears bit DOE31_0.DIO1
  • 0h = No effect
  • 1h = Clear
0DIO0W0hClears bit DOE31_0.DIO0
  • 0h = No effect
  • 1h = Clear

22.10.41 DOETGL31_0 Register (Offset = 530h) [Reset = 00000000h]

DOETGL31_0 is shown in Table 22-87.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOE31_0 register.

Table 22-87 DOETGL31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30W0hToggles bit DOE31_0.DIO30
  • 0h = No effect
  • 1h = Toggle
29DIO29W0hToggles bit DOE31_0.DIO29
  • 0h = No effect
  • 1h = Toggle
28DIO28W0hToggles bit DOE31_0.DIO28
  • 0h = No effect
  • 1h = Toggle
27DIO27W0hToggles bit DOE31_0.DIO27
  • 0h = No effect
  • 1h = Toggle
26DIO26W0hToggles bit DOE31_0.DIO26
  • 0h = No effect
  • 1h = Toggle
25DIO25W0hToggles bit DOE31_0.DIO25
  • 0h = No effect
  • 1h = Toggle
24DIO24W0hToggles bit DOE31_0.DIO24
  • 0h = No effect
  • 1h = Toggle
23DIO23W0hToggles bit DOE31_0.DIO23
  • 0h = No effect
  • 1h = Toggle
22DIO22W0hToggles bit DOE31_0.DIO22
  • 0h = No effect
  • 1h = Toggle
21DIO21W0hToggles bit DOE31_0.DIO21
  • 0h = No effect
  • 1h = Toggle
20DIO20W0hToggles bit DOE31_0.DIO20
  • 0h = No effect
  • 1h = Toggle
19DIO19W0hToggles bit DOE31_0.DIO19
  • 0h = No effect
  • 1h = Toggle
18DIO18W0hToggles bit DOE31_0.DIO18
  • 0h = No effect
  • 1h = Toggle
17DIO17W0hToggles bit DOE31_0.DIO17
  • 0h = No effect
  • 1h = Toggle
16DIO16W0hToggles bit DOE31_0.DIO16
  • 0h = No effect
  • 1h = Toggle
15DIO15W0hToggles bit DOE31_0.DIO15
  • 0h = No effect
  • 1h = Toggle
14DIO14W0hToggles bit DOE31_0.DIO14
  • 0h = No effect
  • 1h = Toggle
13DIO13W0hToggles bit DOE31_0.DIO13
  • 0h = No effect
  • 1h = Toggle
12DIO12W0hToggles bit DOE31_0.DIO12
  • 0h = No effect
  • 1h = Toggle
11DIO11W0hToggles bit DOE31_0.DIO11
  • 0h = No effect
  • 1h = Toggle
10DIO10W0hToggles bit DOE31_0.DIO10
  • 0h = No effect
  • 1h = Toggle
9DIO9W0hToggles bit DOE31_0.DIO9
  • 0h = No effect
  • 1h = Toggle
8DIO8W0hToggles bit DOE31_0.DIO8
  • 0h = No effect
  • 1h = Toggle
7DIO7W0hToggles bit DOE31_0.DIO7
  • 0h = No effect
  • 1h = Toggle
6DIO6W0hToggles bit DOE31_0.DIO6
  • 0h = No effect
  • 1h = Toggle
5DIO5W0hToggles bit DOE31_0.DIO5
  • 0h = No effect
  • 1h = Toggle
4DIO4W0hToggles bit DOE31_0.DIO4
  • 0h = No effect
  • 1h = Toggle
3DIO3W0hToggles bit DOE31_0.DIO3
  • 0h = No effect
  • 1h = Toggle
2DIO2W0hToggles bit DOE31_0.DIO2
  • 0h = No effect
  • 1h = Toggle
1DIO1W0hToggles bit DOE31_0.DIO1
  • 0h = No effect
  • 1h = Toggle
0DIO0W0hToggles bit DOE31_0.DIO0
  • 0h = No effect
  • 1h = Toggle

22.10.42 DIN3_0 Register (Offset = 600h) [Reset = 00000000h]

DIN3_0 is shown in Table 22-88.

Return to the Summary Table.

Alias register for byte access to DIN31_0[3:0] bits.

Table 22-88 DIN3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3R0hData input from DIO3
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO2R0hData input from DIO2
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO1R0hData input from DIO1
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO0R0hData input from DIO0
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.43 DIN7_4 Register (Offset = 604h) [Reset = 00000000h]

DIN7_4 is shown in Table 22-89.

Return to the Summary Table.

Alias register for byte access to DIN31_0[7:4] bits.

Table 22-89 DIN7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7R0hData input from DIO7
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO6R0hData input from DIO6
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO5R0hData input from DIO5
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO4R0hData input from DIO4
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.44 DIN11_8 Register (Offset = 608h) [Reset = 00000000h]

DIN11_8 is shown in Table 22-90.

Return to the Summary Table.

Alias register for byte access to DIN31_0[11:8] bits.

Table 22-90 DIN11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11R0hData input from DIO11
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO10R0hData input from DIO10
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO9R0hData input from DIO9
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO8R0hData input from DIO8
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.45 DIN15_12 Register (Offset = 60Ch) [Reset = 00000000h]

DIN15_12 is shown in Table 22-91.

Return to the Summary Table.

Alias register for byte access to DIN31_0[15:12] bits.

Table 22-91 DIN15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15R0hData input from DIO15
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO14R0hData input from DIO14
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO13R0hData input from DIO13
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO12R0hData input from DIO12
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.46 DIN19_16 Register (Offset = 610h) [Reset = 00000000h]

DIN19_16 is shown in Table 22-92.

Return to the Summary Table.

Alias register for byte access to DIN31_0[19:16] bits.

Table 22-92 DIN19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19R0hData input from DIO19
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO18R0hData input from DIO18
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO17R0hData input from DIO17
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO16R0hData input from DIO16
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.47 DIN23_20 Register (Offset = 614h) [Reset = 00000000h]

DIN23_20 is shown in Table 22-93.

Return to the Summary Table.

Alias register for byte access to DIN31_0[23:20] bits.

Table 22-93 DIN23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23R0hData input from DIO23
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO22R0hData input from DIO22
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO21R0hData input from DIO21
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO20R0hData input from DIO20
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.48 DIN27_24 Register (Offset = 618h) [Reset = 00000000h]

DIN27_24 is shown in Table 22-94.

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Alias register for byte access to DIN31_0[24:27] bits.

Table 22-94 DIN27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO27R0hData input from DIO27
  • 0h = Input value is 0
  • 1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO26R0hData input from DIO26
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO25R0hData input from DIO25
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO24R0hData input from DIO24
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.49 DIN31_28 Register (Offset = 61Ch) [Reset = 00000000h]

DIN31_28 is shown in Table 22-95.

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Alias register for byte access to DIN31_0[31:28] bits.

Table 22-95 DIN31_28 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16DIO30R0hData input from DIO30
  • 0h = Input value is 0
  • 1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO29R0hData input from DIO29
  • 0h = Input value is 0
  • 1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO28R0hData input from DIO28
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.50 DIN31_0 Register (Offset = 700h) [Reset = 00000000h]

DIN31_0 is shown in Table 22-96.

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Data input from DIO 31 to 0 pins.

Table 22-96 DIN31_0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30DIO30R0hData input from DIO30
  • 0h = Input value is 0
  • 1h = Input value is 1
29DIO29R0hData input from DIO29
  • 0h = Input value is 0
  • 1h = Input value is 1
28DIO28R0hData input from DIO28
  • 0h = Input value is 0
  • 1h = Input value is 1
27DIO27R0hData input from DIO27
  • 0h = Input value is 0
  • 1h = Input value is 1
26DIO26R0hData input from DIO26
  • 0h = Input value is 0
  • 1h = Input value is 1
25DIO25R0hData input from DIO25
  • 0h = Input value is 0
  • 1h = Input value is 1
24DIO24R0hData input from DIO24
  • 0h = Input value is 0
  • 1h = Input value is 1
23DIO23R0hData input from DIO23
  • 0h = Input value is 0
  • 1h = Input value is 1
22DIO22R0hData input from DIO22
  • 0h = Input value is 0
  • 1h = Input value is 1
21DIO21R0hData input from DIO21
  • 0h = Input value is 0
  • 1h = Input value is 1
20DIO20R0hData input from DIO20
  • 0h = Input value is 0
  • 1h = Input value is 1
19DIO19R0hData input from DIO19
  • 0h = Input value is 0
  • 1h = Input value is 1
18DIO18R0hData input from DIO18
  • 0h = Input value is 0
  • 1h = Input value is 1
17DIO17R0hData input from DIO17
  • 0h = Input value is 0
  • 1h = Input value is 1
16DIO16R0hData input from DIO16
  • 0h = Input value is 0
  • 1h = Input value is 1
15DIO15R0hData input from DIO15
  • 0h = Input value is 0
  • 1h = Input value is 1
14DIO14R0hData input from DIO14
  • 0h = Input value is 0
  • 1h = Input value is 1
13DIO13R0hData input from DIO13
  • 0h = Input value is 0
  • 1h = Input value is 1
12DIO12R0hData input from DIO12
  • 0h = Input value is 0
  • 1h = Input value is 1
11DIO11R0hData input from DIO11
  • 0h = Input value is 0
  • 1h = Input value is 1
10DIO10R0hData input from DIO10
  • 0h = Input value is 0
  • 1h = Input value is 1
9DIO9R0hData input from DIO9
  • 0h = Input value is 0
  • 1h = Input value is 1
8DIO8R0hData input from DIO8
  • 0h = Input value is 0
  • 1h = Input value is 1
7DIO7R0hData input from DIO7
  • 0h = Input value is 0
  • 1h = Input value is 1
6DIO6R0hData input from DIO6
  • 0h = Input value is 0
  • 1h = Input value is 1
5DIO5R0hData input from DIO5
  • 0h = Input value is 0
  • 1h = Input value is 1
4DIO4R0hData input from DIO4
  • 0h = Input value is 0
  • 1h = Input value is 1
3DIO3R0hData input from DIO3
  • 0h = Input value is 0
  • 1h = Input value is 1
2DIO2R0hData input from DIO2
  • 0h = Input value is 0
  • 1h = Input value is 1
1DIO1R0hData input from DIO1
  • 0h = Input value is 0
  • 1h = Input value is 1
0DIO0R0hData input from DIO0
  • 0h = Input value is 0
  • 1h = Input value is 1

22.10.51 EVTCFG Register (Offset = 800h) [Reset = 00000000h]

EVTCFG is shown in Table 22-97.

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Event configuration 0. This register is used to select DIO for GPIO to publish event on SVT event fabric. It also contains enable bit that is used to mask the event.

Table 22-97 EVTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8EVTENR/W0hEnables GPIO to publish edge qualified selected DIO event on SVT event fabric.
Design note: The edge detector flop is cleared automatically for the selected DIO once the event is published.
  • 0h = Disable
  • 1h = Enable
7-6RESERVEDR0hReserved
5-0DIOSELR/W0hThis is used to select DIO for event generation. For example, DIOSEL = 0x0 selects DIO0 and DIOSEL = 0x8 selects DIO8.
  • 0h = Minimum value
  • 3Fh = Maximum value

22.10.52 EVTCFG1 Register (Offset = 810h) [Reset = 00000000h]

EVTCFG1 is shown in Table 22-98.

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Event configuration 1. This register is used to select DIO for GPIO to publish event on SVT event fabric. It also contains enable bit that is used to mask the event.

Table 22-98 EVTCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8EVTENR/W0hEnables GPIO to publish edge qualified selected DIO event on SVT event fabric.
Design note: The edge detector flop is cleared automatically for the selected DIO once the event is published.
  • 0h = Disable
  • 1h = Enable
7-6RESERVEDR0hReserved
5-0DIOSELR/W0hThis is used to select DIO for event generation. For example, DIOSEL = 0x0 selects DIO0 and DIOSEL = 0x8 selects DIO8.
  • 0h = Minimum value
  • 3Fh = Maximum value