SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

26.11 I2S Registers

Table 26-1 lists the memory-mapped registers for the I2S registers. All register offset addresses not listed in Table 26-1 should be considered as reserved locations and the register contents should not be modified.

Table 26-1 I2S Registers
OffsetAcronymRegister NameSection
0hWCLKSRCThis register configures the **WCLK** SourceSection 26.11.1
4hDMACFGThis register configures DMA buffer sizeSection 26.11.2
8hDIRCFGThis register configures the direction of data pins(**AD0**/**AD1**)Section 26.11.3
ChFMTCFGThis register configures the serial interface formatSection 26.11.4
10hWMASK0This register configures the word selection dit mask for data pin 0(**AD0**)Section 26.11.5
14hWMASK1This register configures the word selection dit mask for data pin 1(**AD1**)Section 26.11.6
20hINPTRNXTThis register configures DMA input buffer next pointerSection 26.11.7
24hINPTRThis register configures the DMA input buffer current pointerSection 26.11.8
28hOUTPTRNXTThis register configures DMA output buffer next pointerSection 26.11.9
2ChOUTPTRThis register configures DMA output buffer current pointerSection 26.11.10
34hSTMPCTLThis register controls the samplestamp generator.Section 26.11.11
38hSTMPXCNTCAPT0This register gives the captured **XOSC** counter value, capture channel 0Section 26.11.12
3ChSTMPXPERThe register gives the XOSC period valueSection 26.11.13
40hSTMPWCNTCAPT0This register gives the captured **WCLK** counter value, capture channel 0Section 26.11.14
44hSTMPWPERThis register configures **WCLK** counter period valueSection 26.11.15
48hSTMPINTRIGThis register configures **WCLK** counter trigger value for input pinsSection 26.11.16
4ChSTMPOUTTRIGThis register configures **WCLK** counter trigger value for output pinsSection 26.11.17
50hSTMPWSETThis register confiures **WCLK** counter set operationSection 26.11.18
54hSTMPWADDThis register configures WCLK counter add operationSection 26.11.19
58hSTMPXPERMINThis register configures **XOSC** minimum period valueSection 26.11.20
5ChSTMPWCNTThis register gives the current value of **WLCK** counterSection 26.11.21
60hSTMPXCNTThis register gives the current value **XOSC** counterSection 26.11.22
70hIRQMASKInterrupt Mask RegisterSection 26.11.23
74hIRQFLAGSThis registers gives the raw interrupt statusSection 26.11.24
78hIRQSETInterrupt Set Register. This register can be used by software for diagnostics and safety checking purposes.Section 26.11.25
7ChIRQCLRInterrupt clear register. This register allows software to clear interrupts.Section 26.11.26
80hMCLKDIVThis field configures **MCLK** division ratioSection 26.11.27
84hBCLKDIVThis field configures **BCLK** division ratioSection 26.11.28
88hWCLKDIVThis field configures **WCLK** division ratioSection 26.11.29
8ChCLKCTLThis register controls internal audio clockSection 26.11.30
90hDTBDigital test bus controlSection 26.11.31

Complex bit access types are encoded to fit into small table cells. Table 26-2 shows the codes that are used for access types in this section.

Table 26-2 I2S Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

26.11.1 WCLKSRC Register (Offset = 0h) [Reset = 00000000h]

WCLKSRC is shown in Table 26-3.

Return to the Summary Table.

This register configures the WCLK Source

Table 26-3 WCLKSRC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2WCLKINVR/W0hThis field Inverts WCLK source (pad or internal).
  • 0h = Source is not intverted
  • 1h = Source is inverted
1-0WBCLKSRCR/W0hThis field selects WCLK/BCLK source for I2S.
  • 0h = None ('0')
  • 1h = External WCLK generator, from pad
  • 2h = Internal WCLK generator, from module PRCM
  • 3h = Not supported. Will give same WCLK as 'NONE' ('00')

26.11.2 DMACFG Register (Offset = 4h) [Reset = 00000000h]

DMACFG is shown in Table 26-4.

Return to the Summary Table.

This register configures DMA buffer size

Table 26-4 DMACFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ENDFRMIDXR/W0hThis field defines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes I2S.
Note that before doing so, all other configuration must have been done, and INPTRNXT/OUTPTRNXT must have been loaded.

26.11.3 DIRCFG Register (Offset = 8h) [Reset = 00000000h]

DIRCFG is shown in Table 26-5.

Return to the Summary Table.

This register configures the direction of data pins(AD0/AD1)

Table 26-5 DIRCFG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-4AD1R/W0hThe field configures the AD1 data pin direction
  • 0h = Not in use (disabled)
  • 1h = Input
  • 2h = Output
  • 3h = Reserved
3-2RESERVEDR0hReserved
1-0AD0R/W0hThe field configures the AD0 data pin direction
  • 0h = Not in use (disabled)
  • 1h = Input
  • 2h = Output
  • 3h = Reserved

26.11.4 FMTCFG Register (Offset = Ch) [Reset = 00000000h]

FMTCFG is shown in Table 26-6.

Return to the Summary Table.

This register configures the serial interface format

Table 26-6 FMTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8DATADLYR/W1hThis field configures the number of BCLK periods between a WCLK edge and MSB of the first word in a phase
Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.
  • 0h = Zero BCLK periods - LJF and DSP formats
  • 1h = One BCLK periods - I2S and DSP formats
  • 2h = Two(Min) BCLK periods - RJF format
  • FFh = Max(255) BCLK periods - RJF format
7MEMLEN32R/W0hThis register configures the size of each word stored to or loaded from memory
  • 0h = 16-bit (one 16 bit access per sample)
  • 1h = 32-bit(one 32-bit access per sample)
6SMPLEDGER/W1hThis field configures the sample edge/ transfer edge of data (and WCLK) on BCLK
  • 0h = Data is sampled on the negative edge and clocked out on the positive edge.
  • 1h = Data is sampled on the positive edge and clocked out on the negative edge.
5DUALPHASER/W1hThis field selects between dual-phase or single-phase format
  • 0h = Single-phase: DSP format
  • 1h = Dual-phase: I2S, LJF and RJF formats
4-0WORDLENR/W10hNumber of bits per word (8-24):
In single-phase format, this is the exact number of bits per word.
In dual-phase format, this is the maximum number of bits per word.
Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEMLEN32. Bit widths that differ from this alignment will either be truncated or zero padded.

26.11.5 WMASK0 Register (Offset = 10h) [Reset = 00000000h]

WMASK0 is shown in Table 26-7.

Return to the Summary Table.

This register configures the word selection dit mask for data pin 0(AD0)

Table 26-7 WMASK0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0MASKR/W3hBit-mask indicating valid channels in a frame on AD0.
In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins.

26.11.6 WMASK1 Register (Offset = 14h) [Reset = 00000000h]

WMASK1 is shown in Table 26-8.

Return to the Summary Table.

This register configures the word selection dit mask for data pin 1(AD1)

Table 26-8 WMASK1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0MASKR/W3hBit-mask indicating valid channels in a frame on AD1.
In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins.

26.11.7 INPTRNXT Register (Offset = 20h) [Reset = 00000000h]

INPTRNXT is shown in Table 26-9.

Return to the Summary Table.

This register configures DMA input buffer next pointer

Table 26-9 INPTRNXT Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR/W0hPointer to the first byte in the next DMA input buffer.
The read value equals the last written value until the currently used DMA input buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.DMAIN.
At startup, the value must be written once before and once after configuring the DMA buffer size in DMACFG.
The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTRERR will be raised and all input pins will be disabled.

26.11.8 INPTR Register (Offset = 24h) [Reset = 00000000h]

INPTR is shown in Table 26-10.

Return to the Summary Table.

This register configures the DMA input buffer current pointer

Table 26-10 INPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR0hValue of the DMA input buffer pointer currently used by the DMA controller. Incremented by 1 (byte) or 2 (word) for each AHB access.

26.11.9 OUTPTRNXT Register (Offset = 28h) [Reset = 00000000h]

OUTPTRNXT is shown in Table 26-11.

Return to the Summary Table.

This register configures DMA output buffer next pointer

Table 26-11 OUTPTRNXT Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR/W0hPointer to the first byte in the next DMA output buffer.
The read value equals the last written value until the currently used DMA output buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.DMAOUT.
At startup, the value must be written once before and once after configuring the DMA buffer size in DMACFG. At this time, the first two samples will be fetched from memory.
The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTRERR will be raised and all output pins will be disabled.

26.11.10 OUTPTR Register (Offset = 2Ch) [Reset = 00000000h]

OUTPTR is shown in Table 26-12.

Return to the Summary Table.

This register configures DMA output buffer current pointer

Table 26-12 OUTPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR0hValue of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 (byte) or 2 (word) for each AHB access.

26.11.11 STMPCTL Register (Offset = 34h) [Reset = 00000000h]

STMPCTL is shown in Table 26-13.

Return to the Summary Table.

This register controls the samplestamp generator.

Table 26-13 STMPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2OUTRDYR0hThis field is low until the output pins are ready to be started by the samplestamp generator. When started (that is STMPOUTTRIG equals the WCLK counter) the bit goes back low.
1INRDYR0hThis field is low until the input pins are ready to be started by the samplestamp generator. When started (that is STMPINTRIG equals the WCLK counter) the bit goes back low.
0STMPENR/W0hThis field configures the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.
When cleared, all samplestamp generator counters and capture values are cleared.
  • 0h = Disable the samplestamp generator
  • 1h = Enable the samplestamp generator

26.11.12 STMPXCNTCAPT0 Register (Offset = 38h) [Reset = 00000000h]

STMPXCNTCAPT0 is shown in Table 26-14.

Return to the Summary Table.

This register gives the captured XOSC counter value, capture channel 0

Table 26-14 STMPXCNTCAPT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CAPTVALUER0hThe value of the samplestamp XOSC counter (STMPXCNT.CURRVALUE) last time an event was pulsed. This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK.
The value is cleared when STMPCTL.STMPEN = 0.
Note: Due to buffering and synchronization, WCLK is delayed by a small number of BCLK periods and clk periods.
Note: When calculating the fractional part of the sample stamp, STMPXPER may be less than this bit field.

26.11.13 STMPXPER Register (Offset = 3Ch) [Reset = 00000000h]

STMPXPER is shown in Table 26-15.

Return to the Summary Table.

The register gives the XOSC period value

Table 26-15 STMPXPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER0hThe number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge, had it not been reset to 0).
The value is cleared when STMPCTL.STMPEN = 0.

26.11.14 STMPWCNTCAPT0 Register (Offset = 40h) [Reset = 00000000h]

STMPWCNTCAPT0 is shown in Table 26-16.

Return to the Summary Table.

This register gives the captured WCLK counter value, capture channel 0

Table 26-16 STMPWCNTCAPT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CAPT_VALUER0hThe value of the samplestamp WCLK counter (STMPWCNT.CURRVALUE) last time an event was pulsed. This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled (not taking modification through STMPWADD/STMPWSET into account).
The value is cleared when STMPCTL.STMPEN = 0.

26.11.15 STMPWPER Register (Offset = 44h) [Reset = 00000000h]

STMPWPER is shown in Table 26-17.

Return to the Summary Table.

This register configures WCLK counter period value

Table 26-17 STMPWPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/W0hThis field defines when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer. This is thus a modulo value for the WCLK counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).

26.11.16 STMPINTRIG Register (Offset = 48h) [Reset = 00000000h]

STMPINTRIG is shown in Table 26-18.

Return to the Summary Table.

This register configures WCLK counter trigger value for input pins

Table 26-18 STMPINTRIG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0INSTARTWCNTR/W0hThis field configures the compare value used to start the incoming audio streams.
This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first DMA input buffer).
The value of this register takes effect when the following conditions are met:
- One or more pins are configured as inputs in DIRCFG.
- DMACFG has been configured for the correct buffer size, and at least 32 BCLK cycle ticks have happened.
Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE.

26.11.17 STMPOUTTRIG Register (Offset = 4Ch) [Reset = 00000000h]

STMPOUTTRIG is shown in Table 26-19.

Return to the Summary Table.

This register configures WCLK counter trigger value for output pins

Table 26-19 STMPOUTTRIG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0OUTSTARTWCNTR/W0hThis field cofnigures the compare value used to start the outgoing audio streams.
This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first DMA output buffer).
The value of this register takes effect when the following conditions are met:
- One or more pins are configured as outputs in DIRCFG.
- DMACFG has been configured for the correct buffer size, and 32 BCLK cycle ticks have happened.
- 2 samples have been preloaded from memory (examine the OUTPTR register if necessary).
Note: The memory read access is only performed when required, that is channels 0/1 must be selected in WMASK0/WMASK1.
Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE.

26.11.18 STMPWSET Register (Offset = 50h) [Reset = 00000000h]

STMPWSET is shown in Table 26-20.

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This register confiures WCLK counter set operation

Table 26-20 STMPWSET Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUEW0hSets the running WCLK counter equal to the written value.

26.11.19 STMPWADD Register (Offset = 54h) [Reset = 00000000h]

STMPWADD is shown in Table 26-21.

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This register configures WCLK counter add operation

Table 26-21 STMPWADD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUEINCW0hAdds the written value to the running WCLK counter. If a positive edge of WCLK occurs at the same time as the operation, this will be taken into account.
To add a negative value, write "STMPWPER.VALUE - value".

26.11.20 STMPXPERMIN Register (Offset = 58h) [Reset = 00000000h]

STMPXPERMIN is shown in Table 26-22.

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This register configures XOSC minimum period value
Minimum Value of STMPXPER

Table 26-22 STMPXPERMIN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/WFFFFhEach time STMPXPER is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register.
When written, the register is reset to 0xFFFF (65535), regardless of the value written.
The minimum value can be used to detect extra WCLK pulses (this registers value will be significantly smaller than STMPXPER.VALUE).

26.11.21 STMPWCNT Register (Offset = 5Ch) [Reset = 00000000h]

STMPWCNT is shown in Table 26-23.

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This register gives the current value of WLCK counter

Table 26-23 STMPWCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CURRVALUER0hCurrent value of the WCLK counter

26.11.22 STMPXCNT Register (Offset = 60h) [Reset = 00000000h]

STMPXCNT is shown in Table 26-24.

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This register gives the current value XOSC counter

Table 26-24 STMPXCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CURRVALUER0hCurrent value of the XOSC counter, latched when reading STMPWCNT.

26.11.23 IRQMASK Register (Offset = 70h) [Reset = 00000000h]

IRQMASK is shown in Table 26-25.

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Interrupt Mask Register
Selects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event.

Table 26-25 IRQMASK Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCAPTR/W0hIRQFLAGS.XCNTCAPT interrupt mask
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask
5DMAINR/W0hIRQFLAGS.DMAIN interrupt mask
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask
4DMAOUTR/W0hIRQFLAGS.DMAOUT interrupt mask
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask
3WCLKTIMEOUTR/W0hIRQFLAGS.WCLKTIMEOUT interrupt mask
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask
2BUSERRR/W0hIRQFLAGS.BUSERR interrupt mask
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask
1WCLKERRR/W0hIRQFLAGS.WCLKERR interrupt mask
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask
0PTRERRR/W0hIRQFLAGS.PTRERR interrupt mask.
  • 0h = Disable the interrupt mask
  • 1h = Enable the interrupt mask

26.11.24 IRQFLAGS Register (Offset = 74h) [Reset = 00000000h]

IRQFLAGS is shown in Table 26-26.

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This registers gives the raw interrupt status

Table 26-26 IRQFLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCAPTR0hThis interrupt is set when xcnt counter is captured either by events or software.
Needs to be cleared by software.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5DMAINR0hThis interrupt is set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register for details.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4DMAOUTR0hThis interrupt is set when condition for this bit field event occurs (auto cleared when output pointer is updated - OUTPTRNXT), see description of OUTPTRNXT register for details
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3WCLKTIMEOUTR0hSet when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled.
The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLKTIMEOUT).
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2BUSERRR0hThis interrupt set when a DMA operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow).
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.BUSERR).
Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1WCLKERRR0hThis interrupt is set when:
- An unexpected WCLK edge occurs during the data delay period of a phase. Note unexpected WCLK edges during the word and idle periods of the phase are not detected.
- In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles apart.
- In single-phase mode, when a WCLK pulse occurs before the last channel.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLKERR).
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0PTRERRR0hThis interrupt set when INPTRNXT or OUTPTRNXT has not been loaded with the next block address in time.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.PTRERR).
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

26.11.25 IRQSET Register (Offset = 78h) [Reset = 00000000h]

IRQSET is shown in Table 26-27.

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Interrupt Set Register. This register can be used by software for diagnostics and safety checking purposes.

Table 26-27 IRQSET Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCAPTW0hThis field sets the interrupt IRQFLAGS.XCNTCAPT (unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
5DMAINW0hThis field sets the interrupt IRQFLAGS.DMAIN (unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
4DMAOUTW0hThis field sets the interrupt IRQFLAGS.DMAOUT (unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
3WCLKTIMEOUTW0hThis field sets the interrupt IRQFLAGS.WCLKTIMEOUT(unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
2BUSERRW0h1: Sets the interrupt of IRQFLAGS.BUSERR(unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
1WCLKERRW0hThis field sets the interrupt IRQFLAGS.WCLKERR(unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
0PTRERRW0hThis field sets the interrupt IRQFLAGS.PTRERR(unless a auto clear criteria was given at the same time, in which the set will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt

26.11.26 IRQCLR Register (Offset = 7Ch) [Reset = 00000000h]

IRQCLR is shown in Table 26-28.

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Interrupt clear register. This register allows software to clear interrupts.

Table 26-28 IRQCLR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCAPTW0hThs field clears the interrupt IRQFLAGS.XCNTCAPT (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
5DMAINW0hThis field clears the interrupt of IRQFLAGS.DMAIN (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
4DMAOUTW0hThis field clears the interrupt IRQFLAGS.DMAOUT (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
3WCLKTIMEOUTW0h1: Clears the interrupt of IRQFLAGS.WCLKTIMEOUT (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
2BUSERRW0hThis field clears the interrupt IRQFLAGS.BUSERR (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
1WCLKERRW0hThis field clears the interrupt IRQFLAGS.WCLKERR (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
0PTRERRW0hThis field clears the interrupt IRQFLAGS.PTRERR (unless a set criteria was given at the same time in which the clear will be ignored)
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt

26.11.27 MCLKDIV Register (Offset = 80h) [Reset = 00000000h]

MCLKDIV is shown in Table 26-29.

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This field configures MCLK division ratio

Table 26-29 MCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0MDIVR/W0h An unsigned factor of the division ratio used to generate MCLK [2-1024]:
MCLK = MCUCLK/MDIV[Hz] MCUCLK is upto 96MHz.
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase.

26.11.28 BCLKDIV Register (Offset = 84h) [Reset = 00000000h]

BCLKDIV is shown in Table 26-30.

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This field configures BCLK division ratio

Table 26-30 BCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0BDIVR/W0h An unsigned factor of the division ratio used to generate BCLK [2-1024]:
BCLK = MCUCLK/BDIV[Hz] MCUCLK can be upto 96MHz.
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If BDIV is odd and FMTCFG.SMPLEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase.
If BDIV is odd and FMTCFG.SMPLEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase.

26.11.29 WCLKDIV Register (Offset = 88h) [Reset = 00000000h]

WCLKDIV is shown in Table 26-31.

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This field configures WCLK division ratio

Table 26-31 WCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
15-0WDIVR/W0h If CLKCTL.WCLKPHASE = 0, Single phase. WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods.
WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] MCUCLK upto 96MHz.
If WCLKPHASE = 1, Dual phase. Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods.
**WCLK **= **MCUCLK **/ BDIV*(2*WDIV[9:0]) [Hz]
If WCLKPHASE = 2, User defined. WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods.
WCLK = **MCUCLK **/ (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]

26.11.30 CLKCTL Register (Offset = 8Ch) [Reset = 00000000h]

CLKCTL is shown in Table 26-32.

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This register controls internal audio clock

Table 26-32 CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3MENR/W0hThis field configures the MCLK generation
  • 0h = Disable the generation
  • 1h = Enable the generation
2-1WCLKPHASER/W0hThe field configures how the WCLK division ratio is calculated and used to generate different duty cycles (See WCLKDIV.WDIV)
0WBENR/W0hThis field configures WCLK/BCLK generation
  • 0h = Disables the generation
  • 1h = Enable the generation

26.11.31 DTB Register (Offset = 90h) [Reset = 00000000h]

DTB is shown in Table 26-33.

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Digital test bus control

Table 26-33 DTB Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SELR/W0hThe field controls the select of DTB
  • 0h = None is selected
  • 1h = Samplestamp WCNT(16 bits)
  • 2h = Samplestamp XCNT(16 bits)
  • 3h = {12{1'b0},aif_words_sampled, aif_word_loaded, aif_output_en, aif_input_en}