SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755P10 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

7.3.1 FLASH Registers

Table 7-44 lists the memory-mapped registers for the FLASH registers. All register offset addresses not listed in Table 7-44 should be considered as reserved locations and the register contents should not be modified.

Table 7-44 FLASH Registers
OffsetAcronymRegister NameSection
28hIMASKInterrupt Mask RegisterSection 7.3.1.1
30hRISRaw Interrupt Status RegisterSection 7.3.1.2
38hMISMasked Interrupt Status RegisterSection 7.3.1.3
40hISETInterrupt Set RegisterSection 7.3.1.4
48hICLRInterrupt Clear RegisterSection 7.3.1.5
FChDESCHardware Version Description RegisterSection 7.3.1.6
100hCMDEXECCommand Execute RegisterSection 7.3.1.7
104hCMDTYPECommand Type RegisterSection 7.3.1.8
108hCMDCTLCommand Control RegisterSection 7.3.1.9
120hCMDADDRCommand Address RegisterSection 7.3.1.10
124hCMDBYTENCommand Program Byte Enable RegisterSection 7.3.1.11
130hCMDDATA0Command Data Register 0Section 7.3.1.12
134hCMDDATA1Command Data Register 1Section 7.3.1.13
138hCMDDATA2Command Data Register 2Section 7.3.1.14
13ChCMDDATA3Command Data Register Bits 127:96Section 7.3.1.15
1D0hCMDWEPROTACommand Write Erase Protect A RegisterSection 7.3.1.16
1D4hCMDWEPROTBCommand Write Erase Protect B RegisterSection 7.3.1.17
210hCMDWEPROTNMCommand Write Erase Protect Non-Main RegisterSection 7.3.1.18
214hCMDWEPROTTRCommand Write Erase Protect Trim RegisterSection 7.3.1.19
218hCMDWEPROTENCommand Write Erase Protect Engr RegisterSection 7.3.1.20
3B0hCFGCMDCommand Configuration RegisterSection 7.3.1.21
3B4hCFGPCNTPulse Counter Configuration RegisterSection 7.3.1.22
3D0hSTATCMDCommand Status RegisterSection 7.3.1.23
3D4hSTATADDRAddress Status RegisterSection 7.3.1.24
3D8hSTATPCNTPulse Count Status RegisterSection 7.3.1.25
3DChSTATMODEMode Status RegisterSection 7.3.1.26
3F0hGBLINFO0Global Information Register 0Section 7.3.1.27
3F4hGBLINFO1Global Information Register 1Section 7.3.1.28
3F8hGBLINFO2Global Information Register 2Section 7.3.1.29
400hBANK0INFO0Bank Information Register 0 for Bank 0Section 7.3.1.30
404hBANK0INFO1Bank Information Register 1 for Bank 0Section 7.3.1.31
410hBANK1INFO0Bank Information Register 0 for Bank 1Section 7.3.1.32
414hBANK1INFO1Bank Information Register 1 for Bank 1Section 7.3.1.33

Complex bit access types are encoded to fit into small table cells. Table 7-45 shows the codes that are used for access types in this section.

Table 7-45 FLASH Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.3.1.1 IMASK Register (Offset = 28h) [Reset = 00000000h]

IMASK is shown in Table 7-46.

Return to the Summary Table.

Interrupt Mask Register:
The IMASK register holds the current interrupt mask settings. Masked interrupts
are read in the MIS register. PSD compliant register.

Table 7-46 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER/W0hInterrupt mask for DONE:
0: Interrupt is disabled in MIS register
1: Interrupt is enabled in MIS register
  • 0h = Interrupt is masked out
  • 1h = Interrupt will request an interrupt service routine and corresponding bit in IPSTANDARD.MIS will be set

7.3.1.2 RIS Register (Offset = 30h) [Reset = 00000000h]

RIS is shown in Table 7-47.

Return to the Summary Table.

Raw Interrupt Status Register:
The RIS register reflects all pending interrupts, regardless of masking.
The RIS register allows the user to implement a poll scheme. A flag set in this
register can be cleared by writing a 1 to the ICLR register bit even if the
corresponding IMASK bit is not enabled. A flag can be set by software by writing
a 1 to the ISET register. Reading the IIDX register will also clear the
corresponding bit in RIS. PSD compliant register.

Table 7-47 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hFlash wrapper operation completed.
This interrupt bit is set by firmware or the corresponding bit in the ISET register.
It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

7.3.1.3 MIS Register (Offset = 38h) [Reset = 00000000h]

MIS is shown in Table 7-48.

Return to the Summary Table.

Masked Interrupt Status Register:
The MIS register is a bit-wise AND of the contents of the IMASK and RIS
registers. This is kept mainly for ARM compatibility, and has limited use since
the highest priority interrupt index is returned through the IIDX register.
PSD
compliant register.

Table 7-48 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hFlash wrapper operation completed.
This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
  • 0h = Masked interrupt did not occur
  • 1h = Masked interrupt occurred

7.3.1.4 ISET Register (Offset = 40h) [Reset = 00000000h]

ISET is shown in Table 7-49.

Return to the Summary Table.

Interrupt Set Register:
The ISET register allows software to write a 1 to set corresponding interrupt.
Safety:
This meets a safety requirement to allow software diagnostics to trigger
interrupts.
PSD compliant register.

Table 7-49 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONEW0h0: No effect
1: Set the DONE interrupt in the RIS register
  • 0h = Writing a 0 has no effect
  • 1h = Set IPSTANDARD.RIS bit

7.3.1.5 ICLR Register (Offset = 48h) [Reset = 00000000h]

ICLR is shown in Table 7-50.

Return to the Summary Table.

Interrupt Clear Register.
The ICLR register allows allows software to write a 1 to clear corresponding
interrupt.
PSD compliant register.

Table 7-50 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONEW0h0: No effect
1: Clear the DONE interrupt in the RIS register
  • 0h = Writing a 0 has no effect
  • 1h = Clear IPSTANDARD.RIS bit

7.3.1.6 DESC Register (Offset = FCh) [Reset = 00000000h]

DESC is shown in Table 7-51.

Return to the Summary Table.

Hardware Version Description Register:
This register identifies the flash wrapper hardware version and feature set used.

Table 7-51 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDRB40hModule ID
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12FEATUREVERR4hFeature set
  • 0h = Minimum Value
  • Fh = Maximum Value
11-8INSTNUMR0hInstance number
  • 0h = Smallest value
  • Fh = Highest possible value
7-4MAJREVR1hMajor Revision
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor Revision
  • 0h = Smallest value
  • Fh = Highest possible value

7.3.1.7 CMDEXEC Register (Offset = 100h) [Reset = 00000000h]

CMDEXEC is shown in Table 7-52.

Return to the Summary Table.

Command Execute Register:
Initiates execution of the command specified in the CMDTYPE register.
This register is blocked for writes after being written to 1 and prior to
STATCMD.DONE being set by the flash wrapper hardware.
flash wrapper hardware clears this register after the processing of the command
has completed.

Table 7-52 CMDEXEC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W0hCommand Execute value
Initiates execution of the command specified in the CMDTYPE register.
  • 0h = Command will not execute or is not executing in flash wrapper
  • 1h = Command will execute or is executing in flash wrapper

7.3.1.8 CMDTYPE Register (Offset = 104h) [Reset = 00000000h]

CMDTYPE is shown in Table 7-53.

Return to the Summary Table.

Command Type Register
This register specifies the type of command to be executed by the flash wrapper
hardware.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Table 7-53 CMDTYPE Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-4SIZER/W0hCommand size
  • 0h = Operate on 1 flash word
  • 1h = Operate on 2 flash words
  • 2h = Operate on 4 flash words
  • 3h = Operate on 8 flash words
  • 4h = Operate on a flash sector
  • 5h = Operate on an entire flash bank
3RESERVEDR0hReserved
2-0COMMANDR/W0hCommand type
  • 0h = No Operation
  • 1h = Program
  • 2h = Erase
  • 4h = Mode Change - Perform a mode change only, no other operation.
  • 5h = Clear Status - Clear status bits in FW_SMSTAT only.
  • 6h = Blank Verify - Check whether a flash word is in the erased state.;This command may only be used with CMDTYPE.SIZE = ONEWORD

7.3.1.9 CMDCTL Register (Offset = 108h) [Reset = 00000000h]

CMDCTL is shown in Table 7-54.

Return to the Summary Table.

Command Control Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Table 7-54 CMDCTL Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved
21DATAVERENR/W0hEnable invalid data verify.
This checks for 0->1 transitions in the memory when
a program operation is initiated. If such a transition is found, the program will
fail with an error without executing the program.
  • 0h = Disable
  • 1h = Enable
20SSERASEDISR/W0hDisable Stair-Step Erase. If set, the default VHV trim voltage setting will be used
for all erase pulses.
By default, this bit is reset, meaning that the VHV voltage will be stepped during
successive erase pulses. The step count, step voltage, begin and end voltages
are all hard-wired.
  • 0h = Enable
  • 1h = Disable
19-17RESERVEDR0hReserved
16ADDRXLATEOVRR/W0hOverride hardware address translation of address in CMDADDR from a
system address to a bank address and bank ID. Use data written to
CMDADDR directly as the bank address. Use the value written to
CMDCTL.BANKSEL directly as the bank ID. Use the value written to
CMDCTL.REGIONSEL directly as the region ID.
  • 0h = Do not override
  • 1h = Override
15-14RESERVEDR0hReserved
13RESERVEDR0hReserved
12-9REGIONSELR/W0hBank Region
A specific region ID can be written to this field to indicate to which region an
operation is to be applied if CMDCTL.ADDRXLATEOVR is set.
  • 1h = Main Region
  • 2h = Non-Main Region
  • 4h = Trim Region
  • 8h = Engr Region
8-6RESERVEDR0hReserved
5-4BANKSELR/W0hBank Select
A specific Bank ID can be written to this field to indicate to which bank an
operation is to be applied if CMDCTL.ADDRXLATEOVR is set.
  • 1h = Bank 0
  • 2h = Bank 1
  • 4h = Bank 2
  • 8h = Bank 3
  • 10h = Bank 4
3-0MODESELR/W0hMode
This field is only used for the Mode Change command type. Otherwise, bank
and pump modes are set automaticlly through the NW hardware.
  • 0h = Read Mode
  • 2h = Read Margin 0 Mode
  • 4h = Read Margin 1 Mode
  • 6h = Read Margin 0B Mode
  • 7h = Read Margin 1B Mode
  • 9h = Program Verify Mode
  • Ah = Program Single Word
  • Bh = Erase Verify Mode
  • Ch = Erase Sector
  • Eh = Program Multiple Word
  • Fh = Erase Bank

7.3.1.10 CMDADDR Register (Offset = 120h) [Reset = 00000000h]

CMDADDR is shown in Table 7-55.

Return to the Summary Table.

Command Address Register:
This register forms the target address of a command. The use cases are as
follows:
1) For single-word program, this address indicates the flash bank word to be
programmed.
2) For multi-word program, this address indicates the first flash bank address
for the program. The address will be incremented for further words.
3) For sector erase, this address indicates the sector to be erased.
4) For bank erase, the address indicates the bank to be erased.
Note the address written to this register will be submitted for translation to the
flash wrapper address translation interface, and the translated address
will be used to access the bank. However, if the
CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will
be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Table 7-55 CMDADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hAddress value
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.11 CMDBYTEN Register (Offset = 124h) [Reset = 00000000h]

CMDBYTEN is shown in Table 7-56.

Return to the Summary Table.

Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to
be programmed, a 1 must be written to the corresponding bit in this register.
Normally, all bits are written to 1, allowing program of full flash words.
However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit
or 64-bit portions of a flash word.
During verify, data bytes read from the flash will not be checked if the
corresponding CMDBYTEN bit is 0.
ECC data bytes are protected by the 1-2 MSB bits in this register, depending on
the presence of ECC and the flash word data width.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is written to all 0 after the completion of all flash wrapper commands.

Table 7-56 CMDBYTEN Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-16RESERVEDR0hReserved
15-0VALR/W0hCommand Byte Enable value.
A 1-bit per flash word byte value is placed in this register.
  • 0h = Minimum value of VAL
  • 0003FFFFh = Maximum value of VAL

7.3.1.12 CMDDATA0 Register (Offset = 130h) [Reset = 00000000h]

CMDDATA0 is shown in Table 7-57.

Return to the Summary Table.

Command Data Register 0
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-57 CMDDATA0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.13 CMDDATA1 Register (Offset = 134h) [Reset = 00000000h]

CMDDATA1 is shown in Table 7-58.

Return to the Summary Table.

Command Data Register 1
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to CMDSTAT.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-58 CMDDATA1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.14 CMDDATA2 Register (Offset = 138h) [Reset = 00000000h]

CMDDATA2 is shown in Table 7-59.

Return to the Summary Table.

Command Data Register 2
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-59 CMDDATA2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.15 CMDDATA3 Register (Offset = 13Ch) [Reset = 00000000h]

CMDDATA3 is shown in Table 7-60.

Return to the Summary Table.

Command Data Register 3
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-60 CMDDATA3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.16 CMDWEPROTA Register (Offset = 1D0h) [Reset = 00000000h]

CMDWEPROTA is shown in Table 7-61.

Return to the Summary Table.

Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from
program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32
sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-61 CMDWEPROTA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the flash memory will be protected from program
and erase.
bit [1]: When 1, sector 1 of the flash memory will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the flash memory will be protected from program
and erase.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.17 CMDWEPROTB Register (Offset = 1D4h) [Reset = 00000000h]

CMDWEPROTB is shown in Table 7-62.

Return to the Summary Table.

Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and
erase. Each bit corresponds to a group of 8 sectors.
There are multiple cases for how these protect bits are applied:
1. Single-bank system, CMDWEPROTA register present:
The first 32 sectors are protected via the CMDWEPROTA register. Thus, the
protection given by the bits in CMDWEPROTB begin with sector 32.
2. Single-bank system, CMDWEPROTA register not present:
The protection given by the bits in CMDWEPROTB begin with sector 0.
3. Multi-bank system, CMDWEPROTA register present - Bank 0:
The first 32 sectors of bank 0 are protected via the CMDWEPROTA register.
Thus, only bits 4 and above of CMDWEPROTB would be applicable to bank 0.
The protection of bit 4 and above would begin at sector 32. Bits 3:0
of WEPROTB are ignored for bank 0.
4. Multi-bank system, CMDWEPROTA register present, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has
no effect, so the bits in CMDWEPROTB will protect these banks starting
from sector 0.
5. Multi-bank system, CMDWEPROTA register not present:
The bits in CMDWEPROTB will protect any of the banks starting from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-62 CMDWEPROTB Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors
in the flash will be protected from program and erase. A maximum of 256
sectors can be protected with this register.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.18 CMDWEPROTNM Register (Offset = 210h) [Reset = 00000000h]

CMDWEPROTNM is shown in Table 7-63.

Return to the Summary Table.

Command WriteErase Protect Non-Main
Register
This register allows non-main region region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-63 CMDWEPROTNM Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0VALR/W3hEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the non-main region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the non-main region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the non-main will be protected from program
and erase.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.19 CMDWEPROTTR Register (Offset = 214h) [Reset = 00000000h]

CMDWEPROTTR is shown in Table 7-64.

Return to the Summary Table.

Command WriteErase Protect Trim
Register
This register allows trim region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-64 CMDWEPROTTR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1hEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the engr region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the engr region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the engr region will be protected from program
and erase.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.20 CMDWEPROTEN Register (Offset = 218h) [Reset = 00000000h]

CMDWEPROTEN is shown in Table 7-65.

Return to the Summary Table.

Command WriteErase Protect Engr
Register
This register allows engr region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-65 CMDWEPROTEN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1hEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the engr region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the engr region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the engr region will be protected from program
and erase.
  • 0h = Minimum value of VAL
  • FFFFFFFFh = Maximum value of VAL

7.3.1.21 CFGCMD Register (Offset = 3B0h) [Reset = 00000000h]

CFGCMD is shown in Table 7-66.

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Command Configuration Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Table 7-66 CFGCMD Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-4RESERVEDR0hReserved
3-0WAITSTATER/W2hWait State setting for verify reads
  • 0h = Minimum value
  • Fh = Maximum value

7.3.1.22 CFGPCNT Register (Offset = 3B4h) [Reset = 00000000h]

CFGPCNT is shown in Table 7-67.

Return to the Summary Table.

Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for
program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Table 7-67 CFGPCNT Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-17RESERVEDR0hReserved
16RESERVEDR0hReserved
15-12RESERVEDR0hReserved
11-4MAXPCNTVALR/W0hOverride maximum pulse counter with this value.
If MAXPCNTOVR = 0, then this field is ignored.
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used
to override the max pulse count for both program and erase. Full max value
will be {4'h0, MAXPCNTVAL} .
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used
to override the max pulse count for program only. Full max value will be
{4'h0, MAXPCNTVAL}.
  • 0h = Minimum value
  • FFh = Maximum value
3-1RESERVEDR0hReserved
0MAXPCNTOVRR/W0hOverride hard-wired maximum pulse count. If MAXERSPCNTOVR
is not set, then setting this value alone will override the max pulse count for
both program and erase. If MAXERSPCNTOVR is set, then this bit will only
control the max pulse count setting for program.
By default, this bit is 0, and a hard-wired max pulse count is used.
  • 0h = Use hard-wired (default) value for maximum pulse count
  • 1h = Use value from MAXPCNTVAL field as maximum puse count

7.3.1.23 STATCMD Register (Offset = 3D0h) [Reset = 00000000h]

STATCMD is shown in Table 7-68.

Return to the Summary Table.

Command Status Register
This register contains status regarding completion and errors of command
execution.

Table 7-68 STATCMD Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12FAILMISCR0hCommand failed due to error other than write/erase protect violation or verify
error. This is an extra bit in case a new failure mechanism is added which
requires a status bit.
  • 0h = No Fail
  • 1h = Fail
11-9RESERVEDR0hReserved
8FAILINVDATAR0hProgram command failed because an attempt was made to program a stored
0 value to a 1.
  • 0h = No Fail
  • 1h = Fail
7FAILMODER0hCommand failed because a bank has been set to a mode other than READ.
Program and Erase commands cannot be initiated unless all banks are in READ
mode.
  • 0h = No Fail
  • 1h = Fail
6FAILILLADDRR0hCommand failed due to the use of an illegal address
  • 0h = No Fail
  • 1h = Fail
5FAILVERIFYR0hCommand failed due to verify error
  • 0h = No Fail
  • 1h = Fail
4FAILWEPROTR0hCommand failed due to Write/Erase Protect Sector Violation
  • 0h = No Fail
  • 1h = Fail
3RESERVEDR0hReserved
2CMDINPROGRESSR0hCommand In Progress
  • 0h = Complete
  • 1h = In Progress
1CMDPASSR0hCommand Pass - valid when CMD_DONE field is 1
  • 0h = Fail
  • 1h = Pass
0CMDDONER0hCommand Done
  • 0h = Not Done
  • 1h = Done

7.3.1.24 STATADDR Register (Offset = 3D4h) [Reset = 00000000h]

STATADDR is shown in Table 7-69.

Return to the Summary Table.

Current Address Counter Value
Read only register giving read access to the state machine current address.
A bank id, region id and address are stored in this register and are incremented as
necessary during execution of a command.

Table 7-69 STATADDR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-21BANKIDR1hCurrent Bank ID
A bank indicator is stored in this register which represents the current bank on
which the state machine is operating. There is 1 bit per bank.
  • 1h = Bank 0
  • 2h = Bank 1
  • 4h = Bank 2
  • 8h = Bank 3
  • 10h = Bank 4
20-16REGIONIDR1hCurrent Region ID
A region indicator is stored in this register which represents the current flash
region on which the state machine is operating.
  • 1h = Main Region
  • 2h = Non-Main Region
  • 4h = Trim Region
  • 8h = Engr Region
15-0BANKADDRR0hCurrent Bank Address
A bank offset address is stored in this register.
  • 0h = Minimum value
  • FFFFh = Maximum value

7.3.1.25 STATPCNT Register (Offset = 3D8h) [Reset = 00000000h]

STATPCNT is shown in Table 7-70.

Return to the Summary Table.

Current Pulse Count Register:
Read only register giving read access to the state machine current pulse count
value for program/erase operations.

Table 7-70 STATPCNT Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0PULSECNTR0hCurrent Pulse Counter Value
  • 0h = Minimum value
  • FFFh = Maximum value

7.3.1.26 STATMODE Register (Offset = 3DCh) [Reset = 00000000h]

STATMODE is shown in Table 7-71.

Return to the Summary Table.

Mode Status Register
Indicates one or more banks which not in READ mode, and it indicates the mode
which the bank(s) are in.

Table 7-71 STATMODE Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17BANK1TRDYR0hBank 1T Ready.
Bank(s) are ready for 1T access. This is accomplished when the bank and pump
have been trimmed.
  • 0h = Not ready
  • 1h = Ready
16BANK2TRDYR0hBank 2T Ready.
Bank(s) are ready for 2T access. This is accomplished when the pump has
fully driven power rails to the bank(s).
  • 0h = Not ready
  • 1h = Ready
15-12RESERVEDR0hReserved
11-8BANKMODER0hIndicates mode of bank(s) that are not in READ mode
  • 0h = Read Mode
  • 2h = Read Margin 0 Mode
  • 4h = Read Margin 1 Mode
  • 6h = Read Margin 0B Mode
  • 7h = Read Margin 1B Mode
  • 9h = Program Verify Mode
  • Ah = Program Single Word
  • Bh = Erase Verify Mode
  • Ch = Erase Sector
  • Eh = Program Multiple Word
  • Fh = Erase Bank
7-5RESERVEDR0hReserved
4-2RESERVEDR0hReserved
1-0BANKNOTINRDR0hBank not in read mode.
Indicates which banks are not in READ mode. There is 1 bit per bank.
  • 1h = Bank 0
  • 2h = Bank 1
  • 4h = Bank 2
  • 8h = Bank 3
  • 10h = Bank 4

7.3.1.27 GBLINFO0 Register (Offset = 3F0h) [Reset = 00000000h]

GBLINFO0 is shown in Table 7-72.

Return to the Summary Table.

Global Info 0 Register
Read only register detailing information about sector size and number of banks
present.

Table 7-72 GBLINFO0 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16NUMBANKSR2hNumber of banks instantiated
Minimum: 1
Maximum: 5
  • 1h = Minimum value
  • 5h = Maximum value
15-0SECTORSIZER800hSector size in bytes
  • 400h = Sector size is ONEKB
  • 800h = Sector size is TWOKB

7.3.1.28 GBLINFO1 Register (Offset = 3F4h) [Reset = 00000000h]

GBLINFO1 is shown in Table 7-73.

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Global Info 1 Register
Read only register detailing information about data, ecc and redundant data
widths in bits.

Table 7-73 GBLINFO1 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16REDWIDTHR4hRedundant data width in bits
  • 0h = Redundant data width is 0. Redundancy/Repair not present.
  • 2h = Redundant data width is 2 bits
  • 4h = Redundant data width is 4 bits
15-13RESERVEDR0hReserved
12-8ECCWIDTHR0hECC data width in bits
  • 0h = ECC data width is 0. ECC not used.
  • 8h = ECC data width is 8 bits
  • 10h = ECC data width is 16 bits
7-0DATAWIDTHR80hData width in bits
  • 40h = Data width is 64 bits
  • 80h = Data width is 128 bits

7.3.1.29 GBLINFO2 Register (Offset = 3F8h) [Reset = 00000000h]

GBLINFO2 is shown in Table 7-74.

Return to the Summary Table.

Global Info 2 Register
Read only register detailing information about the number of data registers
present.

Table 7-74 GBLINFO2 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0DATAREGISTERSR1hNumber of data registers present.
  • 1h = Minimum value of DATAREGISTERS
  • 8h = Maximum value of DATAREGISTERS

7.3.1.30 BANK0INFO0 Register (Offset = 400h) [Reset = 00000000h]

BANK0INFO0 is shown in Table 7-75.

Return to the Summary Table.

Bank Info 0 Register for bank 0.
Read only register detailing information about Main region size in the bank.

Table 7-75 BANK0INFO0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER100hMain region size in sectors
Minimum: 0x8 (8)
Maximum: 0x200 (512)
  • 8h = Minimum value of MAINSIZE
  • 200h = Maximum value of MAINSIZE

7.3.1.31 BANK0INFO1 Register (Offset = 404h) [Reset = 00000000h]

BANK0INFO1 is shown in Table 7-76.

Return to the Summary Table.

Bank Info1 Register for bank 0.
Read only register detailing information about Non-Main, Trim, and Engr
region sizes in the bank.

Table 7-76 BANK0INFO1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER1hEngr region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
  • 0h = Minimum value of ENGRSIZE
  • 20h = Maximum value of ENGRSIZE
15-8TRIMSIZER1hTrim region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
  • 0h = Minimum value of TRIMSIZE
  • 20h = Maximum value of TRIMSIZE
7-0NONMAINSIZER2hNon-main region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
  • 0h = Minimum value of NONMAINSIZE
  • 20h = Maximum value of NONMAINSIZE

7.3.1.32 BANK1INFO0 Register (Offset = 410h) [Reset = 00000000h]

BANK1INFO0 is shown in Table 7-77.

Return to the Summary Table.

Bank Info 0 Register for bank 1.
Read only register detailing information about Main region size in the bank.

Table 7-77 BANK1INFO0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER100hMain region size in sectors
Minimum: 0x8 (8)
Maximum: 0x200 (512)
  • 8h = Minimum value of MAINSIZE
  • 200h = Maximum value of MAINSIZE

7.3.1.33 BANK1INFO1 Register (Offset = 414h) [Reset = 00000000h]

BANK1INFO1 is shown in Table 7-78.

Return to the Summary Table.

Bank Info1 Register for bank 1.
Read only register detailing information about Non-Main, Trim, and Engr
region sizes in the bank.

Table 7-78 BANK1INFO1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER1hEngr region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
  • 0h = Minimum value of ENGRSIZE
  • 20h = Maximum value of ENGRSIZE
15-8TRIMSIZER1hTrim region size in sectors
  • 0h = Minimum value of TRIMSIZE
  • 20h = Maximum value of TRIMSIZE
7-0NONMAINSIZER2hNon-main region size in sectors
  • 0h = Minimum value of NONMAINSIZE
  • 20h = Maximum value of NONMAINSIZE