SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

21.5 ADC Registers

Table 21-8 lists the memory-mapped registers for the ADC registers. All register offset addresses not listed in Table 21-8 should be considered as reserved locations and the register contents should not be modified.

Table 21-8 ADC Registers
OffsetAcronymRegister NameSection
28hIMASK0Interrupt maskSection 21.5.1
30hRIS0Raw interrupt statusSection 21.5.2
38hMIS0Masked interrupt statusSection 21.5.3
40hISET0Interrupt setSection 21.5.4
48hICLR0Interrupt clearSection 21.5.5
58hIMASK1Interrupt maskSection 21.5.6
60hRIS1Raw interrupt statusSection 21.5.7
68hMIS1Masked interrupt statusSection 21.5.8
70hISET1Interrupt setSection 21.5.9
78hICLR1Interrupt clearSection 21.5.10
88hIMASK2Interrupt maskSection 21.5.11
90hRIS2Raw interrupt statusSection 21.5.12
98hMIS2Masked interrupt statusSection 21.5.13
A0hISET2Interrupt setSection 21.5.14
A8hICLR2Interrupt clearSection 21.5.15
100hCTL0Control Register 0Section 21.5.16
104hCTL1Control Register 1Section 21.5.17
108hCTL2Control Register 2Section 21.5.18
10ChCTL3Control Register 3Section 21.5.19
114hSCOMP0Sample Time Compare 0 RegisterSection 21.5.20
118hSCOMP1Sample Time Compare 1 RegisterSection 21.5.21
11ChREFCFGReference Buffer Configuration RegisterSection 21.5.22
148hWCLOWWindow Comparator Low Threshold RegisterSection 21.5.23
150hWCHIGHWindow Comparator High Threshold RegisterSection 21.5.24
160hFIFODATAFIFO Data RegisterSection 21.5.25
170hASCRESASC Result RegisterSection 21.5.26
180hMEMCTL0Conversion Memory Control Register 0Section 21.5.27
184hMEMCTL1Conversion Memory Control Register 1Section 21.5.28
188hMEMCTL2Conversion Memory Control Register 2Section 21.5.29
18ChMEMCTL3Conversion Memory Control Register 3Section 21.5.30
280hMEMRES0Memory Result Register 0Section 21.5.31
284hMEMRES1Memory Result Register 1Section 21.5.32
288hMEMRES2Memory Result Register 2Section 21.5.33
28ChMEMRES3Memory Result Register 3Section 21.5.34
340hSTAStatus RegisterSection 21.5.35
E00hTEST0Internal. Only to be used through TI provided API.Section 21.5.36
E08hTEST2Internal. Only to be used through TI provided API.Section 21.5.37
E0ChTEST3Internal. Only to be used through TI provided API.Section 21.5.38
E10hTEST4Internal. Only to be used through TI provided API.Section 21.5.39
E14hTEST5Internal. Only to be used through TI provided API.Section 21.5.40
E18hTEST6Internal. Only to be used through TI provided API.Section 21.5.41
E20hDEBUG1Internal. Only to be used through TI provided API.Section 21.5.42
E24hDEBUG2Internal. Only to be used through TI provided API.Section 21.5.43
E28hDEBUG3Internal. Only to be used through TI provided API.Section 21.5.44
E2ChDEBUG4Internal. Only to be used through TI provided API.Section 21.5.45

Complex bit access types are encoded to fit into small table cells. Table 21-9 shows the codes that are used for access types in this section.

Table 21-9 ADC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

21.5.1 IMASK0 Register (Offset = 28h) [Reset = 00000000h]

IMASK0 is shown in Table 21-10.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.

Table 21-10 IMASK0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hMEMRES3 conversion result interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
10MEMRESIFG2R/W0hMEMRES2 conversion result interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
9MEMRESIFG1R/W0hMEMRES1 conversion result interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
8MEMRESIFG0R/W0hMEMRES0 conversion result interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
7ASCDONER/W0hMask for ASC done raw interrupt flag.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
6UVIFGR/W0hConversion underflow interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
5DMADONER/W0hDMA done interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
4INIFGR/W0hIn-range comparator interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
3LOWIFGR/W0hLow threshold compare interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
2HIGHIFGR/W0hHigh threshold compare interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
1TOVIFGR/W0hSequence conversion time overflow interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
0OVIFGR/W0hConversion overflow interrupt mask.
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask

21.5.2 RIS0 Register (Offset = 30h) [Reset = 00000000h]

RIS0 is shown in Table 21-11.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.

Table 21-11 RIS0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2R0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1R0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7ASCDONER0hRaw interrupt flag for ASC done.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
6UVIFGR0hRaw interrupt flag for MEMRESx underflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
4INIFGR0hRaw interrupt status for In-range comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGR0hRaw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGR0hRaw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1TOVIFGR0hRaw interrupt flag for sequence conversion trigger overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
0OVIFGR0hRaw interrupt flag for MEMRESx overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.

21.5.3 MIS0 Register (Offset = 38h) [Reset = 00000000h]

MIS0 is shown in Table 21-12.

Return to the Summary Table.

Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 21-12 MIS0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R0hMasked interrupt status for MEMRES3.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2R0hMasked interrupt status for MEMRES2.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1R0hMasked interrupt status for MEMRES1.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0R0hMasked interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7ASCDONER0hMasked interrupt status for ASC done.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
6UVIFGR0hMasked interrupt flag for MEMRESx underflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
5DMADONER0hMasked interrupt flag for DMADONE.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
4INIFGR0hMask INIFG in MIS0 register.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGR0hMasked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGR0hMasked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1TOVIFGR0hMasked interrupt flag for sequence conversion timeout overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
0OVIFGR0hMasked interrupt flag for MEMRESx overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.

21.5.4 ISET0 Register (Offset = 40h) [Reset = 00000000h]

ISET0 is shown in Table 21-13.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 21-13 ISET0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3W0hSet interrupt status for MEMRES3.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2W0hSet interrupt status for MEMRES2.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1W0hSet interrupt status for MEMRES1.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0W0hSet Interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7ASCDONEW0hSet interrupt for ASC done.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
6UVIFGW0hSet interrupt for MEMRESx underflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
5DMADONEW0hSet interrupt for DMADONE.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
4INIFGW0hSet INIFG interrupt register.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGW0hSet interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGW0hSet Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1TOVIFGW0hSet interrupt for sequence conversion timeout overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
0OVIFGW0hSet Interrupt for MEMRESx overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.

21.5.5 ICLR0 Register (Offset = 48h) [Reset = 00000000h]

ICLR0 is shown in Table 21-14.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 21-14 ICLR0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3W0hClear interrupt status for MEMRES3.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2W0hClear interrupt status for MEMRES2.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1W0hClear interrupt status for MEMRES1.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0W0hClear interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7ASCDONEW0hClear ASC done flag in RIS.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
6UVIFGW0hClear interrupt flag for MEMRESx underflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
5DMADONEW0hClear interrupt flag for DMADONE.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
4INIFGW0hClear INIFG in MIS0 register.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGW0hClear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGW0hClear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1TOVIFGW0hClear interrupt flag for sequence conversion timeout overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
0OVIFGW0hClear interrupt flag for MEMRESx overflow.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.

21.5.6 IMASK1 Register (Offset = 58h) [Reset = 00000000h]

IMASK1 is shown in Table 21-15.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.

Table 21-15 IMASK1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R/W0hMEMRES0 conversion result interrupt mask.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR/W0hIn-range comparator interrupt mask.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGR/W0hLow threshold compare interrupt mask.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGR/W0hHigh threshold compare interrupt mask.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1-0RESERVEDR0hReserved

21.5.7 RIS1 Register (Offset = 60h) [Reset = 00000000h]

RIS1 is shown in Table 21-16.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.

Table 21-16 RIS1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR1 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR0hRaw interrupt status for In-range comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGR0hRaw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGR0hRaw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1-0RESERVEDR0hReserved

21.5.8 MIS1 Register (Offset = 68h) [Reset = 00000000h]

MIS1 is shown in Table 21-17.

Return to the Summary Table.

Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 21-17 MIS1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R0hMasked interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR0hMask INIFG in MIS1 register.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGR0hMasked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGR0hMasked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1-0RESERVEDR0hReserved

21.5.9 ISET1 Register (Offset = 70h) [Reset = 00000000h]

ISET1 is shown in Table 21-18.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 21-18 ISET1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0W0hSet Interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGW0hSet INIFG interrupt register.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGW0hSet interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGW0hSet Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1-0RESERVEDR0hReserved

21.5.10 ICLR1 Register (Offset = 78h) [Reset = 00000000h]

ICLR1 is shown in Table 21-19.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 21-19 ICLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0W0hClear interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGW0hClear INIFG in MIS1 register.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
3LOWIFGW0hClear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
2HIGHIFGW0hClear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
  • 0h = Interrupt is not pending.
  • 1h = Interrupt is pending.
1-0RESERVEDR0hReserved

21.5.11 IMASK2 Register (Offset = 88h) [Reset = 00000000h]

IMASK2 is shown in Table 21-20.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.

Table 21-20 IMASK2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hMEMRES3 conversion result interrupt mask.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2R/W0hMEMRES2 conversion result interrupt mask.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1R/W0hMEMRES1 conversion result interrupt mask.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0R/W0hMEMRES0 conversion result interrupt mask.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

21.5.12 RIS2 Register (Offset = 90h) [Reset = 00000000h]

RIS2 is shown in Table 21-21.

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Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.

Table 21-21 RIS2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2R0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1R0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

21.5.13 MIS2 Register (Offset = 98h) [Reset = 00000000h]

MIS2 is shown in Table 21-22.

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Extension of Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 21-22 MIS2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R0hMasked interrupt status for MEMRES3.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2R0hMasked interrupt status for MEMRES2.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1R0hMasked interrupt status for MEMRES1.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0R0hMasked interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

21.5.14 ISET2 Register (Offset = A0h) [Reset = 00000000h]

ISET2 is shown in Table 21-23.

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Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 21-23 ISET2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3W0hSet interrupt status for MEMRES3.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2W0hSet interrupt status for MEMRES2.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1W0hSet interrupt status for MEMRES1.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0W0hSet Interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

21.5.15 ICLR2 Register (Offset = A8h) [Reset = 00000000h]

ICLR2 is shown in Table 21-24.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 21-24 ICLR2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3W0hClear interrupt status for MEMRES3.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
10MEMRESIFG2W0hClear interrupt status for MEMRES2.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
9MEMRESIFG1W0hClear interrupt status for MEMRES1.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
8MEMRESIFG0W0hClear interrupt status for MEMRES0.
  • 0h = No new data ready.
  • 1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

21.5.16 CTL0 Register (Offset = 100h) [Reset = 00000000h]

CTL0 is shown in Table 21-25.

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Control Register 0

Table 21-25 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0hReserved
26-24SCLKDIVR/W0hSample clock divider
  • 0h = Do not divide clock source
  • 1h = Divide clock source by 2
  • 2h = Divide clock source by 4
  • 3h = Divide clock source by 8
  • 4h = Divide clock source by 16
  • 5h = Divide clock source by 24
  • 6h = Divide clock source by 32
  • 7h = Divide clock source by 48
23-17RESERVEDR0hReserved
16PWRDNR/W0hPower down policy
  • 0h = ADC is powered down on completion of a conversion if there is no pending trigger
  • 1h = ADC remains powered on as long as it is enabled through software.
15-1RESERVEDR0hReserved
0ENCR/W0hEnable conversion
  • 0h = Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
  • 1h = Conversion enabled. ADC sequencer waits for the programmed trigger (software or hardware).

21.5.17 CTL1 Register (Offset = 104h) [Reset = 00000000h]

CTL1 is shown in Table 21-26.

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Control Register 1

Table 21-26 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20SAMPMODER/W0hSample mode. This bit selects the source of the sampling signal.
MANUAL option is not applicable when TRIGSRC is selected as hardware event trigger.
  • 0h = Sample timer high phase is used as sample signal
  • 1h = Software trigger is used as sample signal
19-18RESERVEDR0hReserved
17-16CONSEQR/W0hConversion sequence mode
  • 0h = ADC channel in MEMCTLx pointed by STARTADD will be converted once
  • 1h = ADC channel sequence pointed by STARTADD and ENDADD will be converted once
  • 2h = ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly
  • 3h = ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
15-9RESERVEDR0hReserved
8SCR/W0hStart of conversion
  • 0h = When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start.;When SAMPMODE is set to AUTO, writing 0 has no effect.
  • 1h = When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set. ;When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
7-1RESERVEDR0hReserved
0TRIGSRCR/W0hSample trigger source
  • 0h = Software trigger
  • 1h = Hardware event trigger

21.5.18 CTL2 Register (Offset = 108h) [Reset = 00000000h]

CTL2 is shown in Table 21-27.

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Control Register 2

Table 21-27 CTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24ENDADDR/W0hSequence end address. These bits select which MEMCTLx is the last one for the sequence mode.
The value of ENDADD is 0x00 to 0x03 corresponding to MEMRES0 to MEMRES3.
  • 0h = MEMCTL0 is selected as end address of sequence.
  • 1h = MEMCTL1 is selected as end address of sequence.
  • 2h = MEMCTL2 is selected as end address of sequence.
  • 3h = MEMCTL3 is selected as end address of sequence.
23-21RESERVEDR0hReserved
20-16STARTADDR/W0hSequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode.
The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
  • 0h = MEMCTL0 is selected as start address of a sequence or for a single conversion.
  • 1h = MEMCTL1 is selected as start address of a sequence or for a single conversion.
  • 2h = MEMCTL2 is selected as start address of a sequence or for a single conversion.
  • 3h = MEMCTL3 is selected as start address of a sequence or for a single conversion.
15-11RESERVEDR0hReserved
10FIFOENR/W0hEnable FIFO based operation
  • 0h = Disable
  • 1h = Enable
9RESERVEDR0hReserved
8DMAENR/W0hEnable DMA trigger for data transfer.
Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
  • 0h = DMA trigger not enabled
  • 1h = DMA trigger enabled
7-3RESERVEDR0hReserved
2-1RESR/W0hResolution. These bits define the resolutoin of ADC conversion result.
Note : A value of 3 defaults to 12-bits resolution.
  • 0h = 12-bits resolution
  • 1h = 10-bits resolution
  • 2h = 8-bits resolution
0DFR/W0hData read-back format. Data is always stored in binary unsigned format.
  • 0h = Digital result reads as Binary Unsigned.
  • 1h = Digital result reads Signed Binary. (2s complement), left aligned.

21.5.19 CTL3 Register (Offset = 10Ch) [Reset = 00000000h]

CTL3 is shown in Table 21-28.

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Control Register 3. This register is used to configure ADC for ad-hoc single conversion.

Table 21-28 CTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-12ASCVRSELR/W0hSelects voltage reference for ASC operation. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
  • 0h = VDDS reference
  • 1h = External reference from AREF+/AREF- pins
  • 2h = Internal reference
11-9RESERVEDR0hReserved
8ASCSTIMER/W0hASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
  • 0h = Select SCOMP0
  • 1h = Select SCOMP1
7-5RESERVEDR0hReserved
4-0ASCCHSELR/W0hASC channel select
  • 0h = Selects channel 0
  • 1h = Selects channel 1
  • 2h = Selects channel 2
  • 3h = Selects channel 3
  • 4h = Selects channel 4
  • 5h = Selects channel 5
  • 6h = Selects channel 6
  • 7h = Selects channel 7
  • 8h = Selects channel 8
  • 9h = Selects channel 9
  • Ah = Selects channel 10
  • Bh = Selects channel 11
  • Ch = Selects channel 12
  • Dh = Selects channel 13
  • Eh = Selects channel 14
  • Fh = Selects channel 15

21.5.20 SCOMP0 Register (Offset = 114h) [Reset = 00000000h]

SCOMP0 is shown in Table 21-29.

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Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.

Table 21-29 SCOMP0 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

21.5.21 SCOMP1 Register (Offset = 118h) [Reset = 00000000h]

SCOMP1 is shown in Table 21-30.

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Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.

Table 21-30 SCOMP1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

21.5.22 REFCFG Register (Offset = 11Ch) [Reset = 00000000h]

REFCFG is shown in Table 21-31.

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Reference buffer configuration register

Table 21-31 REFCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-3IBPROGR/W0hConfigures reference buffer bias current output value
  • 0h = 1uA
  • 1h = 0.5uA
  • 2h = 2uA
  • 3h = 0.67uA
2SPARER/W0hSpare bit
1REFVSELR/W0hConfigures reference buffer output voltage
  • 0h = REFBUF generates 2.5V output
  • 1h = REFBUF generates 1.4V output
0REFENR/W0hReference buffer enable
  • 0h = Disable
  • 1h = Enable

21.5.23 WCLOW Register (Offset = 148h) [Reset = 00000000h]

WCLOW is shown in Table 21-32.

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Window Comparator Low Threshold Register.
The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCLOW.

Table 21-32 WCLOW Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The value based on the resolution has to be right aligned with the MSB on the left.
For 10-bits and 8-bits resolution, unused bits have to be 0s.
If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

21.5.24 WCHIGH Register (Offset = 150h) [Reset = 00000000h]

WCHIGH is shown in Table 21-33.

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Window Comparator High Threshold Register.
The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCHIGH.

Table 21-33 WCHIGH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The threshold value has to be right aligned, with the MSB on the left.
For 10-bits and 8-bits resolution, unused bit have to be 0s.
If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

21.5.25 FIFODATA Register (Offset = 160h) [Reset = 00000000h]

FIFODATA is shown in Table 21-34.

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FIFO data register. This is a virtual register used to read from FIFO.

Table 21-34 FIFODATA Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hRead from this data field returns the ADC sample from FIFO.

21.5.26 ASCRES Register (Offset = 170h) [Reset = 00000000h]

ASCRES is shown in Table 21-35.

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ASC result register

Table 21-35 ASCRES Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hResult of ADC ad-hoc single conversion.
If DF = 0, unsigned binary:
The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

21.5.27 MEMCTL0 Register (Offset = 180h) [Reset = 00000000h]

MEMCTL0 is shown in Table 21-36.

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Conversion Memory Control Register 0.
CTL0.ENC must be set to 0 to write to this register.

Table 21-36 MEMCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
  • 0h = Disable
  • 1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
  • 0h = Next conversion is automatic
  • 1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
  • 0h = Select SCOMP0
  • 1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
  • 0h = VDDS reference
  • 1h = External reference from AREF+/AREF- pins
  • 2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
  • 0h = Selects channel 0
  • 1h = Selects channel 1
  • 2h = Selects channel 2
  • 3h = Selects channel 3
  • 4h = Selects channel 4
  • 5h = Selects channel 5
  • 6h = Selects channel 6
  • 7h = Selects channel 7
  • 8h = Selects channel 8
  • 9h = Selects channel 9
  • Ah = Selects channel 10
  • Bh = Selects channel 11
  • Ch = Selects channel 12
  • Dh = Selects channel 13
  • Eh = Selects channel 14
  • Fh = Selects channel 15

21.5.28 MEMCTL1 Register (Offset = 184h) [Reset = 00000000h]

MEMCTL1 is shown in Table 21-37.

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Conversion Memory Control Register 1.
CTL0.ENC must be set to 0 to write to this register.

Table 21-37 MEMCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
  • 0h = Disable
  • 1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
  • 0h = Next conversion is automatic
  • 1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
  • 0h = Select SCOMP0
  • 1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
  • 0h = VDDS reference
  • 1h = External reference from AREF+/AREF- pins
  • 2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
  • 0h = Selects channel 0
  • 1h = Selects channel 1
  • 2h = Selects channel 2
  • 3h = Selects channel 3
  • 4h = Selects channel 4
  • 5h = Selects channel 5
  • 6h = Selects channel 6
  • 7h = Selects channel 7
  • 8h = Selects channel 8
  • 9h = Selects channel 9
  • Ah = Selects channel 10
  • Bh = Selects channel 11
  • Ch = Selects channel 12
  • Dh = Selects channel 13
  • Eh = Selects channel 14
  • Fh = Selects channel 15

21.5.29 MEMCTL2 Register (Offset = 188h) [Reset = 00000000h]

MEMCTL2 is shown in Table 21-38.

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Conversion Memory Control Register 2.
CTL0.ENC must be set to 0 to write to this register.

Table 21-38 MEMCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
  • 0h = Disable
  • 1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
  • 0h = Next conversion is automatic
  • 1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
  • 0h = Select SCOMP0
  • 1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
  • 0h = VDDS reference
  • 1h = External reference from AREF+/AREF- pins
  • 2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
  • 0h = Selects channel 0
  • 1h = Selects channel 1
  • 2h = Selects channel 2
  • 3h = Selects channel 3
  • 4h = Selects channel 4
  • 5h = Selects channel 5
  • 6h = Selects channel 6
  • 7h = Selects channel 7
  • 8h = Selects channel 8
  • 9h = Selects channel 9
  • Ah = Selects channel 10
  • Bh = Selects channel 11
  • Ch = Selects channel 12
  • Dh = Selects channel 13
  • Eh = Selects channel 14
  • Fh = Selects channel 15

21.5.30 MEMCTL3 Register (Offset = 18Ch) [Reset = 00000000h]

MEMCTL3 is shown in Table 21-39.

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Conversion Memory Control Register 3.
CTL0.ENC must be set to 0 to write to this register.

Table 21-39 MEMCTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
  • 0h = Disable
  • 1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
  • 0h = Next conversion is automatic
  • 1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
  • 0h = Select SCOMP0
  • 1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
  • 0h = VDDS reference
  • 1h = External reference from AREF+/AREF- pins
  • 2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
  • 0h = Selects channel 0
  • 1h = Selects channel 1
  • 2h = Selects channel 2
  • 3h = Selects channel 3
  • 4h = Selects channel 4
  • 5h = Selects channel 5
  • 6h = Selects channel 6
  • 7h = Selects channel 7
  • 8h = Selects channel 8
  • 9h = Selects channel 9
  • Ah = Selects channel 10
  • Bh = Selects channel 11
  • Ch = Selects channel 12
  • Dh = Selects channel 13
  • Eh = Selects channel 14
  • Fh = Selects channel 15

21.5.31 MEMRES0 Register (Offset = 280h) [Reset = 00000000h]

MEMRES0 is shown in Table 21-40.

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Memory Result Register 0

Table 21-40 MEMRES0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

21.5.32 MEMRES1 Register (Offset = 284h) [Reset = 00000000h]

MEMRES1 is shown in Table 21-41.

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Memory Result Register 1

Table 21-41 MEMRES1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

21.5.33 MEMRES2 Register (Offset = 288h) [Reset = 00000000h]

MEMRES2 is shown in Table 21-42.

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Memory Result Register 2

Table 21-42 MEMRES2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

21.5.34 MEMRES3 Register (Offset = 28Ch) [Reset = 00000000h]

MEMRES3 is shown in Table 21-43.

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Memory Result Register 3

Table 21-43 MEMRES3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

21.5.35 STA Register (Offset = 340h) [Reset = 00000000h]

STA is shown in Table 21-44.

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Status Register

Table 21-44 STA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2ASCACTR0hASC active
  • 0h = Idle or done
  • 1h = ASC active
1RESERVEDR0hReserved
0BUSYR0hBusy. This bit indicates that an active ADC sample or conversion operation is in progress.
  • 0h = No ADC sampling or conversion in progress.
  • 1h = ADC sampling or conversion is in progress.

21.5.36 TEST0 Register (Offset = E00h) [Reset = 00000000h]

TEST0 is shown in Table 21-45.

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Internal. Only to be used through TI provided API.

Table 21-45 TEST0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ATEST0_ENR/W0hInternal. Only to be used through TI provided API.
29ATEST1_ENR/W0hInternal. Only to be used through TI provided API.
28-13RESERVEDR0hReserved
12-8ATEST1_MUXSELR/W0hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4-0ATEST0_MUXSELR/W0hInternal. Only to be used through TI provided API.

21.5.37 TEST2 Register (Offset = E08h) [Reset = 00000000h]

TEST2 is shown in Table 21-46.

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Internal. Only to be used through TI provided API.

Table 21-46 TEST2 Register Field Descriptions
BitFieldTypeResetDescription
31CDAC_OVST_ENR/W0hInternal. Only to be used through TI provided API.
30-25RESERVEDR0hReserved
24LATCH_TRIM_ENR/W0hInternal. Only to be used through TI provided API.
23-21RESERVEDR0hReserved
20COMP_GAIN_TRIMR/W0hInternal. Only to be used through TI provided API.
19-9RESERVEDR0hReserved
8MUX_TEST_SELR/W0hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

21.5.38 TEST3 Register (Offset = E0Ch) [Reset = 00000000h]

TEST3 is shown in Table 21-47.

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Internal. Only to be used through TI provided API.

Table 21-47 TEST3 Register Field Descriptions
BitFieldTypeResetDescription
31-0CAL_ACUMLR/W0hInternal. Only to be used through TI provided API.

21.5.39 TEST4 Register (Offset = E10h) [Reset = 00000000h]

TEST4 is shown in Table 21-48.

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Internal. Only to be used through TI provided API.

Table 21-48 TEST4 Register Field Descriptions
BitFieldTypeResetDescription
31HW_STEP_SEL_DISR/W0hInternal. Only to be used through TI provided API.
30-25RESERVEDR0hReserved
24CAL_MODE_ENR/W0hInternal. Only to be used through TI provided API.
23-22RESERVEDR0hReserved
21-16CAL_STEP_SELR/W0hInternal. Only to be used through TI provided API.
15-0RESERVEDR0hReserved

21.5.40 TEST5 Register (Offset = E14h) [Reset = 00000000h]

TEST5 is shown in Table 21-49.

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Internal. Only to be used through TI provided API.

Table 21-49 TEST5 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0CAL_CAP_CTLR/W0hInternal. Only to be used through TI provided API.

21.5.41 TEST6 Register (Offset = E18h) [Reset = 00000000h]

TEST6 is shown in Table 21-50.

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Internal. Only to be used through TI provided API.

Table 21-50 TEST6 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0ATESTSELR/W0hInternal. Only to be used through TI provided API.

21.5.42 DEBUG1 Register (Offset = E20h) [Reset = 00000000h]

DEBUG1 is shown in Table 21-51.

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Internal. Only to be used through TI provided API.

Table 21-51 DEBUG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0CTRLR/W00801000hInternal. Only to be used through TI provided API.

21.5.43 DEBUG2 Register (Offset = E24h) [Reset = 00000000h]

DEBUG2 is shown in Table 21-52.

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Internal. Only to be used through TI provided API.

Table 21-52 DEBUG2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-28VTOI_CTRLR/W0hInternal. Only to be used through TI provided API.
27-25RESERVEDR0hReserved
24VTOI_TESTMODE_ENR/W0hInternal. Only to be used through TI provided API.
23-0RESERVEDR0hReserved

21.5.44 DEBUG3 Register (Offset = E28h) [Reset = 00000000h]

DEBUG3 is shown in Table 21-53.

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Internal. Only to be used through TI provided API.

Table 21-53 DEBUG3 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5DEC1_DISR/W0hInternal. Only to be used through TI provided API.
4DEC0_DISR/W0hInternal. Only to be used through TI provided API.
3-1RESERVEDR0hReserved
0BOOST_ENZR/W0hInternal. Only to be used through TI provided API.

21.5.45 DEBUG4 Register (Offset = E2Ch) [Reset = 00000000h]

DEBUG4 is shown in Table 21-54.

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Internal. Only to be used through TI provided API.

Table 21-54 DEBUG4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0ADC_CTRL0R/W0hInternal. Only to be used through TI provided API.