SWCU195A December   2024  â€“ May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

4.6 EVTSVT Registers

Table 4-10 lists the memory-mapped registers for the EVTSVT registers. All register offset addresses not listed in Table 4-10 should be considered as reserved locations and the register contents should not be modified.

Table 4-10 EVTSVT Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.Section 4.6.1
4hDESCEXExtended Description Register. This register provides configuration details of the IP to software drivers and end users.Section 4.6.2
64hDTBDigital test bus control register. This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.Section 4.6.3
400hNMICPU NMI Interrupt RegisterSection 4.6.4
404hCPUIRQ0SELOutput Selection for CPU Interrupt CPUIRQ0Section 4.6.5
408hCPUIRQ1SELOutput Selection for CPU Interrupt CPUIRQ1Section 4.6.6
40ChCPUIRQ2SELOutput Selection for CPU Interrupt CPUIRQ2Section 4.6.7
410hCPUIRQ3SELOutput Selection for CPU Interrupt CPUIRQ3Section 4.6.8
414hCPUIRQ4SELOutput Selection for CPU Interrupt CPUIRQ4Section 4.6.9
418hCPUIRQ5SELOutput Selection for CPU Interrupt CPUIRQ5Section 4.6.10
41ChCPUIRQ6SELOutput Selection for CPU Interrupt CPUIRQ6Section 4.6.11
420hCPUIRQ7SELOutput Selection for CPU Interrupt CPUIRQ7Section 4.6.12
424hCPUIRQ8SELOutput Selection for CPU Interrupt CPUIRQ8Section 4.6.13
428hCPUIRQ9SELOutput Selection for CPU Interrupt CPUIRQ9Section 4.6.14
42ChCPUIRQ10SELOutput Selection for CPU Interrupt CPUIRQ10Section 4.6.15
430hCPUIRQ11SELOutput Selection for CPU Interrupt CPUIRQ11Section 4.6.16
434hCPUIRQ12SELOutput Selection for CPU Interrupt CPUIRQ12Section 4.6.17
438hCPUIRQ13SELOutput Selection for CPU Interrupt CPUIRQ13Section 4.6.18
43ChCPUIRQ14SELOutput Selection for CPU Interrupt CPUIRQ14Section 4.6.19
440hCPUIRQ15SELOutput Selection for CPU Interrupt CPUIRQ15Section 4.6.20
444hCPUIRQ16SELOutput Selection for CPU Interrupt CPUIRQ16Section 4.6.21
448hCPUIRQ17SELOutput Selection for CPU Interrupt CPUIRQ17Section 4.6.22
44ChCPUIRQ18SELOutput Selection for CPU Interrupt CPUIRQ18Section 4.6.23
450hCPUIRQ19SELOutput Selection for CPU Interrupt CPUIRQ19Section 4.6.24
454hCPUIRQ20SELOutput Selection for CPU Interrupt CPUIRQ20Section 4.6.25
458hCPUIRQ21SELOutput Selection for CPU Interrupt CPUIRQ21Section 4.6.26
45ChCPUIRQ22SELOutput Selection for CPU Interrupt CPUIRQ22Section 4.6.27
460hCPUIRQ23SELOutput Selection for CPU Interrupt CPUIRQ23Section 4.6.28
464hCPUIRQ24SELOutput Selection for CPU Interrupt CPUIRQ24Section 4.6.29
468hCPUIRQ25SELOutput Selection for CPU Interrupt CPUIRQ25Section 4.6.30
46ChCPUIRQ26SELOutput Selection for CPU Interrupt CPUIRQ26Section 4.6.31
470hCPUIRQ27SELOutput Selection for CPU Interrupt CPUIRQ27Section 4.6.32
474hCPUIRQ28SELOutput Selection for CPU Interrupt CPUIRQ28Section 4.6.33
478hCPUIRQ29SELOutput Selection for CPU Interrupt CPUIRQ29Section 4.6.34
47ChCPUIRQ30SELOutput Selection for CPU Interrupt CPUIRQ30Section 4.6.35
480hCPUIRQ31SELOutput Selection for CPU Interrupt CPUIRQ31Section 4.6.36
484hCPUIRQ32SELOutput Selection for CPU Interrupt CPUIRQ32Section 4.6.37
488hSYSTIMC0SELOutput Selection for SYSTIMC0Section 4.6.38
48ChSYSTIMC1SELOutput Selection for SYSTIMC1Section 4.6.39
490hSYSTIMC2SELOutput Selection for SYSTIMC2Section 4.6.40
494hSYSTIMC3SELOutput Selection for SYSTIMC3Section 4.6.41
498hSYSTIMC4SELOutput Selection for SYSTIMC4Section 4.6.42
49ChSYSTIMC5SELOutput Selection for SYSTIMC5Section 4.6.43
4A0hADCTRGSELOutput Selection for ADCTRGSection 4.6.44
4A4hLGPTSYNCSELOutput Selection for LGPTSYNCSection 4.6.45
4A8hLGPT0IN0SELOutput Selection for LGPT0IN0Section 4.6.46
4AChLGPT0IN1SELOutput Selection for LGPT0IN1Section 4.6.47
4B0hLGPT0IN2SELOutput Selection for LGPT0IN2Section 4.6.48
4B4hLGPT0TENSELOutput Selection for LGPT0TENSection 4.6.49
4B8hLGPT1IN0SELOutput Selection for LGPT1IN0Section 4.6.50
4BChLGPT1IN1SELOutput Selection for LGPT1IN1Section 4.6.51
4C0hLGPT1IN2SELOutput Selection for LGPT1IN2Section 4.6.52
4C4hLGPT1TENSELOutput Selection for LGPT1TENSection 4.6.53
4C8hLGPT2IN0SELOutput Selection for LGPT2IN0Section 4.6.54
4CChLGPT2IN1SELOutput Selection for LGPT2IN1Section 4.6.55
4D0hLGPT2IN2SELOutput Selection for LGPT2IN2Section 4.6.56
4D4hLGPT2TENSELOutput Selection for LGPT2TENSection 4.6.57
4D8hLGPT3IN0SELOutput Selection for LGPT3IN0Section 4.6.58
4DChLGPT3IN1SELOutput Selection for LGPT3IN1Section 4.6.59
4E0hLGPT3IN2SELOutput Selection for LGPT3IN2Section 4.6.60
4E4hLGPT3TENSELOutput Selection for LGPT3TENSection 4.6.61
4E8hLRFDIN0SELOutput Selection for LRFDIN0Section 4.6.62
4EChLRFDIN1SELOutput Selection for LRFDIN1Section 4.6.63
4F0hLRFDIN2SELOutput Selection for LRFDIN2Section 4.6.64
4F4hI2SSTMPSELOutput Selection for I2SSTMPSection 4.6.65
C00hDMACH0SELOutput Selection for DMA CH0Section 4.6.66
C04hDMACH1SELOutput Selection for DMA CH1Section 4.6.67
C08hDMACH2SELOutput Selection for DMA CH2Section 4.6.68
C0ChDMACH3SELOutput Selection for DMA CH3Section 4.6.69
C10hDMACH4SELOutput Selection for DMA CH4Section 4.6.70
C14hDMACH5SELOutput Selection for DMA CH5Section 4.6.71
C18hDMACH6SELOutput Selection for DMA CH6Section 4.6.72
C1ChDMACH7SELOutput Selection for DMA CH7Section 4.6.73
C20hDMACH10SELOutput Selection for DMA CH10Section 4.6.74
C24hDMACH11SELOutput Selection for DMA CH11Section 4.6.75
C28hDMACH8SELOutput Selection for DMA CH8Section 4.6.76
C2ChDMACH9SELOutput Selection for DMA CH9Section 4.6.77

Complex bit access types are encoded to fit into small table cells. Table 4-11 shows the codes that are used for access types in this section.

Table 4-11 EVTSVT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

4.6.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 4-12.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 4-12 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR3045hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

4.6.2 DESCEX Register (Offset = 4h) [Reset = 00000000h]

DESCEX is shown in Table 4-13.

Return to the Summary Table.

Extended Description Register. This register provides configuration details of the IP to software drivers and end users.

Table 4-13 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-22IDMAREhNumber of DMA input channels
21-17NDMAR10hNumber of DMA output channels
16PDR0hPower Domain.
0 : SVT
1 : ULL
15-8NSUBR3DhNumber of Subscribers
7-0NPUBR39hNumber of Publishers

4.6.3 DTB Register (Offset = 64h) [Reset = 00000000h]

DTB is shown in Table 4-14.

Return to the Summary Table.

Digital test bus control register. This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.

Table 4-14 DTB Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
1-0SELR/W0hDigital test bus selection mux control.
Non-zero select values output a 16 bit selected group of signals per value.

4.6.4 NMI Register (Offset = 400h) [Reset = 00000000h]

NMI is shown in Table 4-15.

Return to the Summary Table.

CPU NMI Interrupt Register

Table 4-15 NMI Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16SRAM_EVT_SETW0hWriting a value of 1'b1 sets the corresponding NMI status flag
15-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
0SRAM_EVT_STAR/W0hRead value indicates the current state of NMI flops.
Writing a value of 1'b1 clears the NMI status when set.

4.6.5 CPUIRQ0SEL Register (Offset = 404h) [Reset = 00000000h]

CPUIRQ0SEL is shown in Table 4-16.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ0

Table 4-16 CPUIRQ0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.6 CPUIRQ1SEL Register (Offset = 408h) [Reset = 00000000h]

CPUIRQ1SEL is shown in Table 4-17.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ1

Table 4-17 CPUIRQ1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.7 CPUIRQ2SEL Register (Offset = 40Ch) [Reset = 00000000h]

CPUIRQ2SEL is shown in Table 4-18.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ2

Table 4-18 CPUIRQ2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.8 CPUIRQ3SEL Register (Offset = 410h) [Reset = 00000000h]

CPUIRQ3SEL is shown in Table 4-19.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ3

Table 4-19 CPUIRQ3SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.9 CPUIRQ4SEL Register (Offset = 414h) [Reset = 00000000h]

CPUIRQ4SEL is shown in Table 4-20.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ4

Table 4-20 CPUIRQ4SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.10 CPUIRQ5SEL Register (Offset = 418h) [Reset = 00000000h]

CPUIRQ5SEL is shown in Table 4-21.

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Output Selection for CPU Interrupt CPUIRQ5

Table 4-21 CPUIRQ5SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR11hRead only selection value
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS

4.6.11 CPUIRQ6SEL Register (Offset = 41Ch) [Reset = 00000000h]

CPUIRQ6SEL is shown in Table 4-22.

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Output Selection for CPU Interrupt CPUIRQ6

Table 4-22 CPUIRQ6SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR14hRead only selection value
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0

4.6.12 CPUIRQ7SEL Register (Offset = 420h) [Reset = 00000000h]

CPUIRQ7SEL is shown in Table 4-23.

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Output Selection for CPU Interrupt CPUIRQ7

Table 4-23 CPUIRQ7SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR15hRead only selection value
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1

4.6.13 CPUIRQ8SEL Register (Offset = 424h) [Reset = 00000000h]

CPUIRQ8SEL is shown in Table 4-24.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ8

Table 4-24 CPUIRQ8SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR1ChRead only selection value
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE

4.6.14 CPUIRQ9SEL Register (Offset = 428h) [Reset = 00000000h]

CPUIRQ9SEL is shown in Table 4-25.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ9

Table 4-25 CPUIRQ9SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR1EhRead only selection value
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS

4.6.15 CPUIRQ10SEL Register (Offset = 42Ch) [Reset = 00000000h]

CPUIRQ10SEL is shown in Table 4-26.

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Output Selection for CPU Interrupt CPUIRQ10

Table 4-26 CPUIRQ10SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR17hRead only selection value
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS

4.6.16 CPUIRQ11SEL Register (Offset = 430h) [Reset = 00000000h]

CPUIRQ11SEL is shown in Table 4-27.

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Output Selection for CPU Interrupt CPUIRQ11

Table 4-27 CPUIRQ11SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR1FhRead only selection value
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS

4.6.17 CPUIRQ12SEL Register (Offset = 434h) [Reset = 00000000h]

CPUIRQ12SEL is shown in Table 4-28.

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Output Selection for CPU Interrupt CPUIRQ12

Table 4-28 CPUIRQ12SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR20hRead only selection value
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS

4.6.18 CPUIRQ13SEL Register (Offset = 438h) [Reset = 00000000h]

CPUIRQ13SEL is shown in Table 4-29.

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Output Selection for CPU Interrupt CPUIRQ13

Table 4-29 CPUIRQ13SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR1AhRead only selection value
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS

4.6.19 CPUIRQ14SEL Register (Offset = 43Ch) [Reset = 00000000h]

CPUIRQ14SEL is shown in Table 4-30.

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Output Selection for CPU Interrupt CPUIRQ14

Table 4-30 CPUIRQ14SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR1BhRead only selection value
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS

4.6.20 CPUIRQ15SEL Register (Offset = 440h) [Reset = 00000000h]

CPUIRQ15SEL is shown in Table 4-31.

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Output Selection for CPU Interrupt CPUIRQ15

Table 4-31 CPUIRQ15SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR18hRead only selection value
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0

4.6.21 CPUIRQ16SEL Register (Offset = 444h) [Reset = 00000000h]

CPUIRQ16SEL is shown in Table 4-32.

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Output Selection for CPU Interrupt CPUIRQ16

Table 4-32 CPUIRQ16SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.22 CPUIRQ17SEL Register (Offset = 448h) [Reset = 00000000h]

CPUIRQ17SEL is shown in Table 4-33.

Return to the Summary Table.

Output Selection for CPU Interrupt CPUIRQ17

Table 4-33 CPUIRQ17SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.23 CPUIRQ18SEL Register (Offset = 44Ch) [Reset = 00000000h]

CPUIRQ18SEL is shown in Table 4-34.

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Output Selection for CPU Interrupt CPUIRQ18

Table 4-34 CPUIRQ18SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR39hRead only selection value
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS

4.6.24 CPUIRQ19SEL Register (Offset = 450h) [Reset = 00000000h]

CPUIRQ19SEL is shown in Table 4-35.

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Output Selection for CPU Interrupt CPUIRQ19

Table 4-35 CPUIRQ19SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR3FhRead only selection value
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS

4.6.25 CPUIRQ20SEL Register (Offset = 454h) [Reset = 00000000h]

CPUIRQ20SEL is shown in Table 4-36.

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Output Selection for CPU Interrupt CPUIRQ20

Table 4-36 CPUIRQ20SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR42hRead only selection value
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK

4.6.26 CPUIRQ21SEL Register (Offset = 458h) [Reset = 00000000h]

CPUIRQ21SEL is shown in Table 4-37.

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Output Selection for CPU Interrupt CPUIRQ21

Table 4-37 CPUIRQ21SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR43hRead only selection value
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0

4.6.27 CPUIRQ22SEL Register (Offset = 45Ch) [Reset = 00000000h]

CPUIRQ22SEL is shown in Table 4-38.

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Output Selection for CPU Interrupt CPUIRQ22

Table 4-38 CPUIRQ22SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR35hRead only selection value
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS

4.6.28 CPUIRQ23SEL Register (Offset = 460h) [Reset = 00000000h]

CPUIRQ23SEL is shown in Table 4-39.

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Output Selection for CPU Interrupt CPUIRQ23

Table 4-39 CPUIRQ23SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR45hRead only selection value
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS

4.6.29 CPUIRQ24SEL Register (Offset = 464h) [Reset = 00000000h]

CPUIRQ24SEL is shown in Table 4-40.

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Output Selection for CPU Interrupt CPUIRQ24

Table 4-40 CPUIRQ24SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR46hRead only selection value
  • 46h = APU IRQ

4.6.30 CPUIRQ25SEL Register (Offset = 468h) [Reset = 00000000h]

CPUIRQ25SEL is shown in Table 4-41.

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Output Selection for CPU Interrupt CPUIRQ25

Table 4-41 CPUIRQ25SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR47hRead only selection value
  • 47h = HSM Secure IRQ

4.6.31 CPUIRQ26SEL Register (Offset = 46Ch) [Reset = 00000000h]

CPUIRQ26SEL is shown in Table 4-42.

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Output Selection for CPU Interrupt CPUIRQ26

Table 4-42 CPUIRQ26SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR48hRead only selection value
  • 48h = HSM Non-secure IRQ

4.6.32 CPUIRQ27SEL Register (Offset = 470h) [Reset = 00000000h]

CPUIRQ27SEL is shown in Table 4-43.

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Output Selection for CPU Interrupt CPUIRQ27

Table 4-43 CPUIRQ27SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR49hRead only selection value
  • 49h = HSM OTP IRQ

4.6.33 CPUIRQ28SEL Register (Offset = 474h) [Reset = 00000000h]

CPUIRQ28SEL is shown in Table 4-44.

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Output Selection for CPU Interrupt CPUIRQ28

Table 4-44 CPUIRQ28SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR2hRead only selection value
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT

4.6.34 CPUIRQ29SEL Register (Offset = 478h) [Reset = 00000000h]

CPUIRQ29SEL is shown in Table 4-45.

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Output Selection for CPU Interrupt CPUIRQ29

Table 4-45 CPUIRQ29SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR3hRead only selection value
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS

4.6.35 CPUIRQ30SEL Register (Offset = 47Ch) [Reset = 00000000h]

CPUIRQ30SEL is shown in Table 4-46.

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Output Selection for CPU Interrupt CPUIRQ30

Table 4-46 CPUIRQ30SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR4hRead only selection value
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting

4.6.36 CPUIRQ31SEL Register (Offset = 480h) [Reset = 00000000h]

CPUIRQ31SEL is shown in Table 4-47.

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Output Selection for CPU Interrupt CPUIRQ31

Table 4-47 CPUIRQ31SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR6hRead only selection value
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG

4.6.37 CPUIRQ32SEL Register (Offset = 484h) [Reset = 00000000h]

CPUIRQ32SEL is shown in Table 4-48.

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Output Selection for CPU Interrupt CPUIRQ32

Table 4-48 CPUIRQ32SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR7hRead only selection value
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG

4.6.38 SYSTIMC0SEL Register (Offset = 488h) [Reset = 00000000h]

SYSTIMC0SEL is shown in Table 4-49.

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Output Selection for SYSTIMC0

Table 4-49 SYSTIMC0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR4hRead only selection value
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting

4.6.39 SYSTIMC1SEL Register (Offset = 48Ch) [Reset = 00000000h]

SYSTIMC1SEL is shown in Table 4-50.

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Output Selection for SYSTIMC1

Table 4-50 SYSTIMC1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.40 SYSTIMC2SEL Register (Offset = 490h) [Reset = 00000000h]

SYSTIMC2SEL is shown in Table 4-51.

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Output Selection for SYSTIMC2

Table 4-51 SYSTIMC2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR32hRead only selection value
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0

4.6.41 SYSTIMC3SEL Register (Offset = 494h) [Reset = 00000000h]

SYSTIMC3SEL is shown in Table 4-52.

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Output Selection for SYSTIMC3

Table 4-52 SYSTIMC3SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR33hRead only selection value
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1

4.6.42 SYSTIMC4SEL Register (Offset = 498h) [Reset = 00000000h]

SYSTIMC4SEL is shown in Table 4-53.

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Output Selection for SYSTIMC4

Table 4-53 SYSTIMC4SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR34hRead only selection value
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2

4.6.43 SYSTIMC5SEL Register (Offset = 49Ch) [Reset = 00000000h]

SYSTIMC5SEL is shown in Table 4-54.

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Output Selection for SYSTIMC5

Table 4-54 SYSTIMC5SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.44 ADCTRGSEL Register (Offset = 4A0h) [Reset = 00000000h]

ADCTRGSEL is shown in Table 4-55.

Return to the Summary Table.

Output Selection for ADCTRG

Table 4-55 ADCTRGSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.45 LGPTSYNCSEL Register (Offset = 4A4h) [Reset = 00000000h]

LGPTSYNCSEL is shown in Table 4-56.

Return to the Summary Table.

Output Selection for LGPTSYNC

Table 4-56 LGPTSYNCSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.46 LGPT0IN0SEL Register (Offset = 4A8h) [Reset = 00000000h]

LGPT0IN0SEL is shown in Table 4-57.

Return to the Summary Table.

Output Selection for LGPT0IN0

Table 4-57 LGPT0IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.47 LGPT0IN1SEL Register (Offset = 4ACh) [Reset = 00000000h]

LGPT0IN1SEL is shown in Table 4-58.

Return to the Summary Table.

Output Selection for LGPT0IN1

Table 4-58 LGPT0IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.48 LGPT0IN2SEL Register (Offset = 4B0h) [Reset = 00000000h]

LGPT0IN2SEL is shown in Table 4-59.

Return to the Summary Table.

Output Selection for LGPT0IN2

Table 4-59 LGPT0IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.49 LGPT0TENSEL Register (Offset = 4B4h) [Reset = 00000000h]

LGPT0TENSEL is shown in Table 4-60.

Return to the Summary Table.

Output Selection for LGPT0TEN

Table 4-60 LGPT0TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.50 LGPT1IN0SEL Register (Offset = 4B8h) [Reset = 00000000h]

LGPT1IN0SEL is shown in Table 4-61.

Return to the Summary Table.

Output Selection for LGPT1IN0

Table 4-61 LGPT1IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.51 LGPT1IN1SEL Register (Offset = 4BCh) [Reset = 00000000h]

LGPT1IN1SEL is shown in Table 4-62.

Return to the Summary Table.

Output Selection for LGPT1IN1

Table 4-62 LGPT1IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.52 LGPT1IN2SEL Register (Offset = 4C0h) [Reset = 00000000h]

LGPT1IN2SEL is shown in Table 4-63.

Return to the Summary Table.

Output Selection for LGPT1IN2

Table 4-63 LGPT1IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.53 LGPT1TENSEL Register (Offset = 4C4h) [Reset = 00000000h]

LGPT1TENSEL is shown in Table 4-64.

Return to the Summary Table.

Output Selection for LGPT1TEN

Table 4-64 LGPT1TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.54 LGPT2IN0SEL Register (Offset = 4C8h) [Reset = 00000000h]

LGPT2IN0SEL is shown in Table 4-65.

Return to the Summary Table.

Output Selection for LGPT2IN0

Table 4-65 LGPT2IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.55 LGPT2IN1SEL Register (Offset = 4CCh) [Reset = 00000000h]

LGPT2IN1SEL is shown in Table 4-66.

Return to the Summary Table.

Output Selection for LGPT2IN1

Table 4-66 LGPT2IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.56 LGPT2IN2SEL Register (Offset = 4D0h) [Reset = 00000000h]

LGPT2IN2SEL is shown in Table 4-67.

Return to the Summary Table.

Output Selection for LGPT2IN2

Table 4-67 LGPT2IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.57 LGPT2TENSEL Register (Offset = 4D4h) [Reset = 00000000h]

LGPT2TENSEL is shown in Table 4-68.

Return to the Summary Table.

Output Selection for LGPT2TEN

Table 4-68 LGPT2TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.58 LGPT3IN0SEL Register (Offset = 4D8h) [Reset = 00000000h]

LGPT3IN0SEL is shown in Table 4-69.

Return to the Summary Table.

Output Selection for LGPT3IN0

Table 4-69 LGPT3IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.59 LGPT3IN1SEL Register (Offset = 4DCh) [Reset = 00000000h]

LGPT3IN1SEL is shown in Table 4-70.

Return to the Summary Table.

Output Selection for LGPT3IN1

Table 4-70 LGPT3IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.60 LGPT3IN2SEL Register (Offset = 4E0h) [Reset = 00000000h]

LGPT3IN2SEL is shown in Table 4-71.

Return to the Summary Table.

Output Selection for LGPT3IN2

Table 4-71 LGPT3IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.61 LGPT3TENSEL Register (Offset = 4E4h) [Reset = 00000000h]

LGPT3TENSEL is shown in Table 4-72.

Return to the Summary Table.

Output Selection for LGPT3TEN

Table 4-72 LGPT3TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.62 LRFDIN0SEL Register (Offset = 4E8h) [Reset = 00000000h]

LRFDIN0SEL is shown in Table 4-73.

Return to the Summary Table.

Output Selection for LRFDIN0

Table 4-73 LRFDIN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR25hRead only selection value
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2

4.6.63 LRFDIN1SEL Register (Offset = 4ECh) [Reset = 00000000h]

LRFDIN1SEL is shown in Table 4-74.

Return to the Summary Table.

Output Selection for LRFDIN1

Table 4-74 LRFDIN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR26hRead only selection value
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3

4.6.64 LRFDIN2SEL Register (Offset = 4F0h) [Reset = 00000000h]

LRFDIN2SEL is shown in Table 4-75.

Return to the Summary Table.

Output Selection for LRFDIN2

Table 4-75 LRFDIN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR27hRead only selection value
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4

4.6.65 I2SSTMPSEL Register (Offset = 4F4h) [Reset = 00000000h]

I2SSTMPSEL is shown in Table 4-76.

Return to the Summary Table.

Output Selection for I2SSTMP

Table 4-76 I2SSTMPSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.66 DMACH0SEL Register (Offset = C00h) [Reset = 00000000h]

DMACH0SEL is shown in Table 4-77.

Return to the Summary Table.

Output Selection for DMA CH0

Table 4-77 DMACH0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Selects spi0txtrg as channel source
  • Dh = Selects uart1rxtrg as channel source

4.6.67 DMACH1SEL Register (Offset = C04h) [Reset = 00000000h]

DMACH1SEL is shown in Table 4-78.

Return to the Summary Table.

Output Selection for DMA CH1

Table 4-78 DMACH1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 1h = Selects spi0rxtrg as channel source
  • Ch = Selects uart1txtrg as channel source

4.6.68 DMACH2SEL Register (Offset = C08h) [Reset = 00000000h]

DMACH2SEL is shown in Table 4-79.

Return to the Summary Table.

Output Selection for DMA CH2

Table 4-79 DMACH2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 2h = Selects lrfdtrg as channel source
  • 6h = Selects uart0txtrg as channel source

4.6.69 DMACH3SEL Register (Offset = C0Ch) [Reset = 00000000h]

DMACH3SEL is shown in Table 4-80.

Return to the Summary Table.

Output Selection for DMA CH3

Table 4-80 DMACH3SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 5h = Selects adc0trg as channel source
  • 7h = Selects uart0rxtrg as channel source

4.6.70 DMACH4SEL Register (Offset = C10h) [Reset = 00000000h]

DMACH4SEL is shown in Table 4-81.

Return to the Summary Table.

Output Selection for DMA CH4

Table 4-81 DMACH4SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 2h = Selects lrfdtrg as channel source
  • 3h = Selects laestrga as channel source

4.6.71 DMACH5SEL Register (Offset = C14h) [Reset = 00000000h]

DMACH5SEL is shown in Table 4-82.

Return to the Summary Table.

Output Selection for DMA CH5

Table 4-82 DMACH5SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 4h = Selects laestrgb as channel source
  • 5h = Selects adc0trg as channel source

4.6.72 DMACH6SEL Register (Offset = C18h) [Reset = 00000000h]

DMACH6SEL is shown in Table 4-83.

Return to the Summary Table.

Output Selection for DMA CH6

Table 4-83 DMACH6SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 8h = Selects cantrga as channel source
  • Ah = Selects spi1txtrg as channel source

4.6.73 DMACH7SEL Register (Offset = C1Ch) [Reset = 00000000h]

DMACH7SEL is shown in Table 4-84.

Return to the Summary Table.

Output Selection for DMA CH7

Table 4-84 DMACH7SEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
3-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 9h = Selects cantrgb as channel source
  • Bh = Selects spi1rxtrg as channel source

4.6.74 DMACH10SEL Register (Offset = C20h) [Reset = 00000000h]

DMACH10SEL is shown in Table 4-85.

Return to the Summary Table.

Output Selection for DMA CH10

Table 4-85 DMACH10SEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16EDGDETDISR/W0hEdge detect disable.
0: Enabled.
1: Disabled
15-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.75 DMACH11SEL Register (Offset = C24h) [Reset = 00000000h]

DMACH11SEL is shown in Table 4-86.

Return to the Summary Table.

Output Selection for DMA CH11

Table 4-86 DMACH11SEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16EDGDETDISR/W0hEdge detect disable.
0: Enabled.
1: Disabled
15-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.76 DMACH8SEL Register (Offset = C28h) [Reset = 00000000h]

DMACH8SEL is shown in Table 4-87.

Return to the Summary Table.

Output Selection for DMA CH8

Table 4-87 DMACH8SEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16EDGDETDISR/W0hEdge detect disable.
0: Enabled.
1: Disabled
15-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event

4.6.77 DMACH9SEL Register (Offset = C2Ch) [Reset = 00000000h]

DMACH9SEL is shown in Table 4-88.

Return to the Summary Table.

Output Selection for DMA CH9

Table 4-88 DMACH9SEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16EDGDETDISR/W0hEdge detect disable.
0: Enabled.
1: Disabled
15-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
6-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
  • 0h = Always inactive
  • 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
  • 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
  • 4h = AON_RTC event, controlled by the RTC:IMASK setting
  • 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
  • 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
  • 7h = IOC synchronous combined event, controlled by IOC:EVTCFG
  • 10h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
  • 11h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
  • 12h = GPIO generic published event 0, controlled by GPIO:EVTCFG
  • 13h = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
  • 14h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
  • 15h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
  • 16h = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
  • 17h = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
  • 18h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
  • 19h = ADC general published event, interrupt flags can be found here ADC:MIS1
  • 1Ah = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
  • 1Bh = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
  • 1Ch = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
  • 1Dh = DMA bus error, corresponds to DMA:ERROR.STATUS
  • 1Eh = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
  • 1Fh = UART0 combined interrupt, interrupt flags are found here UART0:MIS
  • 20h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
  • 21h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
  • 22h = SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
  • 23h = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
  • 24h = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
  • 25h = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
  • 26h = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
  • 27h = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
  • 28h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
  • 29h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
  • 2Ah = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
  • 2Bh = LGPT0 DMA request event, controlled by LGPT0:DMA setting
  • 2Ch = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
  • 2Dh = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
  • 2Eh = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
  • 2Fh = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
  • 30h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
  • 31h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
  • 32h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
  • 33h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
  • 34h = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
  • 35h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
  • 36h = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
  • 37h = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
  • 38h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
  • 39h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
  • 3Ah = LGPT2 DMA request event, controlled by LGPT2:DMA setting
  • 3Bh = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
  • 3Ch = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
  • 3Dh = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
  • 3Eh = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
  • 3Fh = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
  • 40h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
  • 41h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
  • 42h = I2S interrupt event, controlled by I2S:IRQMASK
  • 43h = MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
  • 44h = MCAN general event, interrupt flags can be found here MCAN:MIS1
  • 45h = SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
  • 46h = APU IRQ
  • 4Bh = GPIO generic published event 1, controlled by GPIO:EVTCFG
  • 4Ch = SYSTIM Channel 5 event