SWCU195 User guide

SWCU195A December 2024 – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

1
Read This First
1. About This Manual
2. Devices
3. Register, Field, and Bit Calls
4. Related Documentation
5. Trademarks
1 Architectural Overview
1. 1.1 Target Applications
2. 1.2 Introduction
3. 1.3 Arm Cortex M33
4. 1.4 On-Chip Memory
5. 1.5 Power Supply System
6. 1.6 Radio
7. 1.7 Hardware Security Module
8. 1.8 AES 128-Bit Cryptographic Accelerator
9. 1.9 System Timer (SYSTIM)
10. 1.10 General Purpose Timers (LGPT)
11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
12. 1.12 Direct Memory Access
13. 1.13 System Control and Clock
14. 1.14 Communication Peripherals
15. 1.15 Programmable I/Os
16. 1.16 Algorithm Processing Unit (APU)
17. 1.17 Serial Wire Debug (SWD)
2 Arm® Cortex®-M33 Processor
1. 2.1 Arm® Cortex®-M33 Processor Introduction
2. 2.2 M33 Instantiation Parameters
3. 2.3 Arm® Cortex®-M33 System Peripheral Details
4. 2.4 CPU Sub-System Peripheral Details
5. 2.5 Programming Model
6. 2.6 TrustZone-M
7. 2.7 Arm® Cortex®-M33 Registers
3 Memory Map
1. 3.1 Memory Map
4 Interrupts and Events
1. 4.1 Exception Model
2. 4.2 Fault Handling
3. 4.3 Security State Switches
4. 4.4 Event Fabric
5. 4.5 Digital Test Bus (DTB)
6. 4.6 EVTSVT Registers
7. 4.7 EVTULL Registers
5 Debug Subsystem
1. 5.1 Introduction
2. 5.2 Block Diagram
3. 5.3 Overview
  1. 5.3.1 Physical Interface
  2. 5.3.2 Debug Access Ports
4. 5.4 Debug Features
5. 5.5 Behavior in Low Power Modes
6. 5.6 Restricting Debug Access
7. 5.7 Mailbox (DSSM)
8. 5.8 Mailbox Events
  1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
9. 5.9 Software Considerations
10. 5.10 DBGSS Registers
6 Power, Reset, and Clocking
1. 6.1 Introduction
2. 6.2 System CPU Modes
3. 6.3 Supply System
  1. 6.3.1 Internal DC/DC Converter and Global LDO
4. 6.4 Power States
5. 6.5 Digital Power Partitioning
6. 6.6 Clocks
7. 6.7 Resets
8. 6.8 AON (REG3V3) Register Bank
7 Internal Memory
1. 7.1 SRAM
2. 7.2 VIMS
3. 7.3 FLASH
  1. 7.3.1 FLASH Registers
8 Hardware Security Module (HSM)
1. 8.1 Introduction
2. 8.2 Overview
3. 8.3 One-Time-Programmable (OTP) Controller
  1. 8.3.1 High-Level Sequence to Handle OTP Requests
4. 8.4 Mailbox and Register Access Firewall
5. 8.5 DMA Firewall
6. 8.6 Coprocessor
7. 8.7 HSM FW
8. 8.8 HSM Registers
9. 8.9 HSMCRYPTO Registers
9 Device Boot and Bootloader
1. 9.1 Device Boot and Programming
2. 9.2 Flash Programming
3. 9.3 Device Management Command Interface
  1. 9.3.1 SACI Communication Protocol
  2. 9.3.2 SACI Commands
4. 9.4 Bootloader Support
  1. 9.4.1 Bootloader v.s Secure Boot
5. 9.5 ROM Serial Bootloader
10Device Configuration
1. 10.1 Guidelines for Securely Configuring Your Device
2. 10.2 Factory Configuration (FCFG)
3. 10.3 Customer Configuration (CCFG)
4. 10.4 Security Configuration (SCFG)
11Secure Boot
1. 11.1 Secure Boot
2. 11.2 Execution Flow
3. 11.3 ROM API
  1. 11.3.1 HAPI (Hardware API)
  2. 11.3.2 Registers
4. 11.4 Configuration
5. 11.5 Generic Image Format
6. 11.6 Application Update
  1. 11.6.1 Image Format
7. 11.7 Secondary Secure Bootloader Update
  1. 11.7.1 Image Format
  2. 11.7.2 Update Pattern
8. 11.8 Key Update
  1. 11.8.1 Image Format
9. 11.9 Antirollback
10. 11.10 Version Log (VLOG)
  1. 11.10.1 Record structure
11. 11.11 Fallback
12. 11.12 ROM Panic
12General Purpose Timers (LGPT)
1. 12.1 Overview
2. 12.2 Block Diagram
3. 12.3 Functional Description
4. 12.4 Timer Modes
5. 12.5 LGPT0 Registers
6. 12.6 LGPT1 Registers
7. 12.7 LGPT2 Registers
8. 12.8 LGPT3 Registers
13Algorithm Processing Unit (APU)
1. 13.1 Introduction
2. 13.2 APU Related Collateral
3. 13.3 Functional Description
4. 13.4 APU Operation
5. 13.5 Interrupts and Events
6. 13.6 Data Representation
7. 13.7 Data Memory
8. 13.8 Software
9. 13.9 APU Registers
14Voltage Glitch Monitor (VGM)
1. 14.1 Overview
2. 14.2 Features and Operation
15System Timer (SYSTIM)
1. 15.1 Overview
2. 15.2 Block Diagram
3. 15.3 Functional Description
  1. 15.3.1 Common Channel Features
  2. 15.3.2 Interrupts and Events
4. 15.4 SYSTIM Registers
16Real Time Clock (RTC)
1. 16.1 Introduction
2. 16.2 Block Diagram
3. 16.3 Interrupts and Events
4. 16.4 CAPTURE and COMPARE Configurations
  1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
  2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
5. 16.5 RTC Registers
17Low Power Comparator (SYS0)
1. 17.1 Introduction
2. 17.2 Block Diagram
3. 17.3 Functional Description
4. 17.4 SYS0 Registers
18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
1. 18.1 Introduction
2. 18.2 Functional Description
  1. 18.2.1 BATMON
  2. 18.2.2 DCDC
3. 18.3 PMUD Registers
19Micro Direct Memory Access (µDMA)
1. 19.1 Introduction
2. 19.2 Block Diagram
3. 19.3 Functional Description
4. 19.4 DMA Registers
20Advanced Encryption Standard (AES)
1. 20.1 Introduction
  1. 20.1.1 AES Performance
2. 20.2 Functional Description
3. 20.3 Encryption and Decryption Configuration
4. 20.4 AES Registers
5. 20.5 CRYPTO Registers
21Analog to Digital Converter (ADC)
1. 21.1 Overview
2. 21.2 Block Diagram
3. 21.3 Functional Description
4. 21.4 Advanced Features
5. 21.5 ADC Registers
22I/O Controller (IOC)
1. 22.1 Introduction
2. 22.2 Block Diagram
3. 22.3 I/O Mapping and Configuration
4. 22.4 Edge Detection
5. 22.5 GPIO
6. 22.6 I/O Pins
7. 22.7 Unused Pins
8. 22.8 Debug Configuration
9. 22.9 IOC Registers
10. 22.10 GPIO Registers
23Universal Asynchronous Receiver/Transmitter (UART-LIN)
1. 23.1 Introduction
2. 23.2 Block Diagram
3. 23.3 UART Functional Description
4. 23.4 UART-LIN Specification
5. 23.5 Interface to µDMA
6. 23.6 Initialization and Configuration
7. 23.7 UART Registers
24Serial Peripheral Interface (SPI)
1. 24.1 Overview
  1. 24.1.1 Features
  2. 24.1.2 Block Diagram
2. 24.2 Signal Description
3. 24.3 Functional Description
4. 24.4 µDMA Operation
5. 24.5 Initialization and Configuration
6. 24.6 SPI Registers
25Inter-Integrated Circuit (I2C)
1. 25.1 Introduction
2. 25.2 Block Diagram
3. 25.3 Functional Description
4. 25.4 Initialization and Configuration
5. 25.5 I2C Registers
26Inter-IC Sound (I2S)
1. 26.1 Introduction
2. 26.2 Block Diagram
3. 26.3 Clock Architecture
4. 26.4 Signal Descriptions
5. 26.5 Functional Description
6. 26.6 Memory Interface
7. 26.7 Samplestamp Generator
8. 26.8 Error Detection
9. 26.9 Usage
  1. 26.9.1 Start-Up Sequence
  2. 26.9.2 Shutdown Sequence
10. 26.10 I2S Configuration Guideline
11. 26.11 I2S Registers
27CAN-FD
1. 27.1 Introduction
2. 27.2 Functions
3. 27.3 MCAN Subsystem
4. 27.4 MCAN Functional Description
5. 27.5 CC27xx MCAN Wrapper
6. 27.6 MCAN Clock Enable
7. 27.7 Additional Notes
8. 27.8 CANFD Registers
28Radio
1. 28.1 Introduction
2. 28.2 Block Diagram
3. 28.3 Overview
4. 28.4 Radio Usage Model
  1. 28.4.1 CRC and Whitening
5. 28.5 LRFDDBELL Registers
6. 28.6 LRFDMDM32 Registers
7. 28.7 LRFDPBE Registers
8. 28.8 LRFDPBE32 Registers
9. 28.9 LRFDRFE Registers
10. 28.10 LRFDRFE32 Registers
11. 28.11 LRFDRXF Registers
12. 28.12 LRFDS2R Registers
13. 28.13 LRFDTRC Registers
14. 28.14 LRFDTXF Registers
29Revision History

27.8 CANFD Registers

Table 27-12 lists the memory-mapped registers for the CANFD registers. All register offset addresses not listed in Table 27-12 should be considered as reserved locations and the register contents should not be modified.

Table 27-12 CANFD Registers

Offset	Acronym	Register Name	Section
0h	MCAN_CREL	MCAN Core Release Register	Section 27.8.1
4h	MCAN_ENDN	MCAN Endian Register	Section 27.8.2
Ch	MCAN_DBTP	MCAN Data Bit Timing and Prescaler Register	Section 27.8.3
10h	MCAN_TEST	MCAN Test Register	Section 27.8.4
14h	MCAN_RWD	MCAN RAM Watchdog	Section 27.8.5
18h	MCAN_CCCR	MCAN CC Control Register	Section 27.8.6
1Ch	MCAN_NBTP	MCAN Nominal Bit Timing and Prescaler Register	Section 27.8.7
20h	MCAN_TSCC	MCAN Timestamp Counter Configuration	Section 27.8.8
24h	MCAN_TSCV	MCAN Timestamp Counter Value	Section 27.8.9
28h	MCAN_TOCC	MCAN Timeout Counter Configuration	Section 27.8.10
2Ch	MCAN_TOCV	MCAN Timeout Counter Value	Section 27.8.11
40h	MCAN_ECR	MCAN Error Counter Register	Section 27.8.12
44h	MCAN_PSR	MCAN Protocol Status Register	Section 27.8.13
48h	MCAN_TDCR	MCAN Transmitter Delay Compensation Register	Section 27.8.14
50h	MCAN_IR	MCAN Interrupt Register	Section 27.8.15
54h	MCAN_IE	MCAN Interrupt Enable	Section 27.8.16
58h	MCAN_ILS	MCAN Interrupt Line Select	Section 27.8.17
5Ch	MCAN_ILE	MCAN Interrupt Line Enable	Section 27.8.18
80h	MCAN_GFC	MCAN Global Filter Configuration	Section 27.8.19
84h	MCAN_SIDFC	MCAN Standard ID Filter Configuration	Section 27.8.20
88h	MCAN_XIDFC	MCAN Extended ID Filter Configuration	Section 27.8.21
90h	MCAN_XIDAM	MCAN Extended ID and Mask	Section 27.8.22
94h	MCAN_HPMS	MCAN High Priority Message Status	Section 27.8.23
98h	MCAN_NDAT1	MCAN New Data 1	Section 27.8.24
9Ch	MCAN_NDAT2	MCAN New Data 2	Section 27.8.25
A0h	MCAN_RXF0C	MCAN Rx FIFO 0 Configuration	Section 27.8.26
A4h	MCAN_RXF0S	MCAN Rx FIFO 0 Status	Section 27.8.27
A8h	MCAN_RXF0A	MCAN Rx FIFO 0 Acknowledge	Section 27.8.28
ACh	MCAN_RXBC	MCAN Rx Buffer Configuration	Section 27.8.29
B0h	MCAN_RXF1C	MCAN Rx FIFO 1 Configuration	Section 27.8.30
B4h	MCAN_RXF1S	MCAN Rx FIFO 1 Status	Section 27.8.31
B8h	MCAN_RXF1A	MCAN Rx FIFO 1 Acknowledge	Section 27.8.32
BCh	MCAN_RXESC	MCAN Rx Buffer / FIFO Element Size Configuration	Section 27.8.33
C0h	MCAN_TXBC	MCAN Tx Buffer Configuration	Section 27.8.34
C4h	MCAN_TXFQS	MCAN Tx FIFO / Queue Status	Section 27.8.35
C8h	MCAN_TXESC	MCAN Tx Buffer Element Size Configuration	Section 27.8.36
CCh	MCAN_TXBRP	MCAN Tx Buffer Request Pending	Section 27.8.37
D0h	MCAN_TXBAR	MCAN Tx Buffer Add Request	Section 27.8.38
D4h	MCAN_TXBCR	MCAN Tx Buffer Cancellation Request	Section 27.8.39
D8h	MCAN_TXBTO	MCAN Tx Buffer Transmission Occurred	Section 27.8.40
DCh	MCAN_TXBCF	MCAN Tx Buffer Cancellation Finished	Section 27.8.41
E0h	MCAN_TXBTIE	MCAN Tx Buffer Transmission Interrupt Enable	Section 27.8.42
E4h	MCAN_TXBCIE	MCAN Tx Buffer Cancellation Finished Interrupt Enable	Section 27.8.43
F0h	MCAN_TXEFC	MCAN Tx Event FIFO Configuration	Section 27.8.44
F4h	MCAN_TXEFS	MCAN Tx Event FIFO Status	Section 27.8.45
F8h	MCAN_TXEFA	MCAN Tx Event FIFO Acknowledge	Section 27.8.46
200h	MCANSS_PID	MCAN Subsystem Revision Register	Section 27.8.47
204h	MCANSS_CTRL	MCAN Subsystem Control Register	Section 27.8.48
208h	MCANSS_STAT	MCAN Subsystem Status Register	Section 27.8.49
20Ch	MCANSS_ICS	MCAN Subsystem Interrupt Clear Shadow Register	Section 27.8.50
210h	MCANSS_IRS	MCAN Subsystem Interrupt Raw Satus Register	Section 27.8.51
214h	MCANSS_IECS	MCAN Subsystem Interrupt Enable Clear Shadow Register	Section 27.8.52
218h	MCANSS_IE	MCAN Subsystem Interrupt Enable Register	Section 27.8.53
21Ch	MCANSS_IES	MCAN Subsystem Masked Interrupt Status	Section 27.8.54
220h	MCANSS_EOI	MCAN Subsystem End of Interrupt	Section 27.8.55
224h	MCANSS_EXT_TS_PRESCALER	MCAN Subsystem External Timestamp Prescaler 0	Section 27.8.56
228h	MCANSS_EXT_TS_UNSERVICED_INTR_CNTR	MCAN Subsystem External Timestamp Unserviced Interrupts Counter	Section 27.8.57
400h	MCANERR_REV	MCAN Error Aggregator Revision Register	Section 27.8.58
408h	MCANERR_VECTOR	MCAN ECC Vector Register	Section 27.8.59
40Ch	MCANERR_STAT	MCAN Error Misc Status	Section 27.8.60
410h	MCANERR_WRAP_REV	MCAN ECC Wrapper Revision Register	Section 27.8.61
414h	MCANERR_CTRL	MCAN ECC Control	Section 27.8.62
418h	MCANERR_ERR_CTRL1	MCAN ECC Error Control 1 Register	Section 27.8.63
41Ch	MCANERR_ERR_CTRL2	MCAN ECC Error Control 2 Register	Section 27.8.64
420h	MCANERR_ERR_STAT1	MCAN ECC Error Status 1 Register	Section 27.8.65
424h	MCANERR_ERR_STAT2	MCAN ECC Error Status 2 Register	Section 27.8.66
428h	MCANERR_ERR_STAT3	MCAN ECC Error Status 3 Register	Section 27.8.67
43Ch	MCANERR_SEC_EOI	MCAN Single Error Corrected End of Interrupt Register	Section 27.8.68
440h	MCANERR_SEC_STATUS	MCAN Single Error Corrected Interrupt Status Register	Section 27.8.69
480h	MCANERR_SEC_ENABLE_SET	MCAN Single Error Corrected Interrupt Enable Set Register	Section 27.8.70
4C0h	MCANERR_SEC_ENABLE_CLR	MCAN Single Error Corrected Interrupt Enable Clear Register	Section 27.8.71
53Ch	MCANERR_DED_EOI	MCAN Double Error Detected End of Interrupt Register	Section 27.8.72
540h	MCANERR_DED_STATUS	MCAN Double Error Detected Interrupt Status Register	Section 27.8.73
580h	MCANERR_DED_ENABLE_SET	MCAN Double Error Detected Interrupt Enable Set Register	Section 27.8.74
5C0h	MCANERR_DED_ENABLE_CLR	MCAN Double Error Detected Interrupt Enable Clear Register	Section 27.8.75
600h	MCANERR_AGGR_ENABLE_SET	MCAN Error Aggregator Enable Set Register	Section 27.8.76
604h	MCANERR_AGGR_ENABLE_CLR	MCAN Error Aggregator Enable Clear Register	Section 27.8.77
608h	MCANERR_AGGR_STATUS_SET	MCAN Error Aggregator Status Set Register	Section 27.8.78
60Ch	MCANERR_AGGR_STATUS_CLR	MCAN Error Aggregator Status Clear Register	Section 27.8.79
800h	DESC	Description	Section 27.8.80
844h	IMASK0	Interrupt mask	Section 27.8.81
848h	RIS0	Raw interrupt status	Section 27.8.82
84Ch	MIS0	Masked interrupt status	Section 27.8.83
850h	ISET0	Interrupt set	Section 27.8.84
854h	ICLR0	Interrupt clear	Section 27.8.85
864h	DTB	Digital Test Bus	Section 27.8.86
868h	IMASK1	Interrupt mask	Section 27.8.87
86Ch	RIS1	Raw interrupt status	Section 27.8.88
870h	MIS1	Masked interrupt status	Section 27.8.89
874h	ISET1	Interrupt set	Section 27.8.90
878h	ICLR1	Interrupt clear	Section 27.8.91
904h	MCANSS_CLKDIV	Clock divider	Section 27.8.92
908h	MCANSS_CLKCTL	MCAN-SS clock stop control register	Section 27.8.93
90Ch	MCANSS_CLKSTS	MCANSS clock stop status register	Section 27.8.94
924h	MCANSS_DMA0_CTL	MCANSS Fixed DMA0 Control Register	Section 27.8.95
92Ch	MCANSS_DMA1_CTL	MCANSS Fixed DMA1 Control Register	Section 27.8.96
938h	RXDMA_TTO_FE0_BA	Rx buffer [x] base address - most significant word	Section 27.8.97
948h	RXDMA_TTO_FE1_BA	Rx buffer [x+1] base address - most significant word	Section 27.8.98
950h	RXDMA_TTO_NDAT1	Rx Buffer two-to-one DMA mode, hardware NDAT1 value register.	Section 27.8.99

Complex bit access types are encoded to fit into small table cells. Table 27-13 shows the codes that are used for access types in this section.

Table 27-13 CANFD Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
WD	W D	Write Decrement. Decrements the specified bit field by the amount written.
WI	W I	Write Increment. Increments the specified bit field by the amount written.
WQ	W Q	Write Qualified. A condition must be met for this operation to occur.
Reset or Default Value
-n		Value after reset or the default value

27.8.1 MCAN_CREL Register (Offset = 0h) [Reset = 00000000h]

MCAN_CREL is shown in Table 27-14.

Return to the Summary Table.

MCAN Core Release Register

Table 27-14 MCAN_CREL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	REL	R	3h	Core Release. One digit, BCD-coded.
27-24	STEP	R	2h	Step of Core Release. One digit, BCD-coded.
23-20	SUBSTEP	R	3h	Sub-Step of Core Release. One digit, BCD-coded.
19-16	YEAR	R	8h	Time Stamp Year. One digit, BCD-coded.
15-8	MON	R	6h	Time Stamp Month. Two digits, BCD-coded.
7-0	DAY	R	8h	Time Stamp Day. Two digits, BCD-coded.

27.8.2 MCAN_ENDN Register (Offset = 4h) [Reset = 00000000h]

MCAN_ENDN is shown in Table 27-15.

Return to the Summary Table.

MCAN Endian Register

Table 27-15 MCAN_ENDN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ETV	R	87654321h	Endianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU.

27.8.3 MCAN_DBTP Register (Offset = Ch) [Reset = 00000000h]

MCAN_DBTP is shown in Table 27-16.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 m_can_cclk periods. tq = (DBRP + 1) mtq.;DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2.;Therefore the length of the bit time is (programmed values) (DTSEG1 + DTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq.;The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Table 27-16 MCAN_DBTP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23	TDC	R/WQ	0h	Transmitter Delay Compensation; 0 Transmitter Delay Compensation disabled; 1 Transmitter Delay Compensation enabled
22-21	RESERVED	R	0h	Reserved
20-16	DBRP	R/WQ	0h	Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-13	RESERVED	R	0h	Reserved
12-8	DTSEG1	R/WQ	Ah	Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7-4	DTSEG2	R/WQ	3h	Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-0	DSJW	R/WQ	3h	Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.4 MCAN_TEST Register (Offset = 10h) [Reset = 00000000h]

MCAN_TEST is shown in Table 27-17.

Return to the Summary Table.

Write access to the Test Register has to be enabled by setting bit CCCR.TEST to '1'. All Test Register functions are set to their reset values when bit CCCR.TEST is reset.;Loop Back Mode and software control of the internal CAN TX pin are hardware test modes. Programming of;TX ? "00" may disturb the message transfer on the CAN bus.

Table 27-17 MCAN_TEST Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RX	R	0h	Receive Pin. Monitors the actual value of the CAN receive pin.; 0 The CAN bus is dominant (CAN RX pin = '0'); 1 The CAN bus is recessive (CAN RX pin = '1')
6-5	TX	R/WQ	0h	Control of Transmit Pin; 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time; 01 Sample Point can be monitored at CAN TX pin; 10 Dominant ('0') level at CAN TX pin; 11 Recessive ('1') at CAN TX pin; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4	LBCK	R/WQ	0h	Loop Back Mode; 0 Reset value, Loop Back Mode is disabled; 1 Loop Back Mode is enabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-0	RESERVED	R	0h	Reserved

27.8.5 MCAN_RWD Register (Offset = 14h) [Reset = 00000000h]

MCAN_RWD is shown in Table 27-18.

Return to the Summary Table.

MCAN RAM Watchdog

Table 27-18 MCAN_RWD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	WDV	R	0h	Watchdog Value. Acutal Message RAM Watchdog Counter Value.; ;The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.
7-0	WDC	R/WQ	0h	Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.6 MCAN_CCCR Register (Offset = 18h) [Reset = 00000000h]

MCAN_CCCR is shown in Table 27-19.

Return to the Summary Table.

MCAN CC Control Register

Table 27-19 MCAN_CCCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	NISO	R/WQ	0h	Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.; 0 CAN FD frame format according to ISO 11898-1:2015; 1 CAN FD frame format according to Bosch CAN FD Specification V1.0
14	TXP	R/WQ	0h	Transmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame.; 0 Transmit pause disabled; 1 Transmit pause enabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
13	EFBI	R/WQ	0h	Edge Filtering during Bus Integration; 0 Edge filtering disabled; 1 Two consecutive dominant tq required to detect an edge for hard synchronization; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
12	PXHD	R/WQ	0h	Protocol Exception Handling Disable; 0 Protocol exception handling enabled; 1 Protocol exception handling disabled;Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
11-10	RESERVED	R	0h	Reserved
9	BRSE	R/WQ	0h	Bit Rate Switch Enable; 0 Bit rate switching for transmissions disabled; 1 Bit rate switching for transmissions enabled;Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
8	FDOE	R/WQ	0h	Flexible Datarate Operation Enable; 0 FD operation disabled; 1 FD operation enabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7	TEST	R/WQ	0h	Test Mode Enable; 0 Normal operation, register TEST holds reset values; 1 Test Mode, write access to register TEST enabled; ;Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
6	DAR	R/WQ	0h	Disable Automatic Retransmission; 0 Automatic retransmission of messages not transmitted successfully enabled; 1 Automatic retransmission disabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
5	MON	R/WQ	0h	Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.; 0 Bus Monitoring Mode is disabled; 1 Bus Monitoring Mode is enabled; ;Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4	CSR	R/W	0h	Clock Stop Request; 0 No clock stop is requested; 1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.
3	CSA	R	0h	Clock Stop Acknowledge; 0 No clock stop acknowledged; 1 MCAN may be set in power down by stopping the Host and CAN clocks
2	ASM	R/WQ	0h	Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.; 0 Normal CAN operation; 1 Restricted Operation Mode active; ;Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1	CCE	R/WQ	0h	Configuration Change Enable; 0 The CPU has no write access to the protected configuration registers; 1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1'); ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0	INIT	R/W	1h	Initialization; 0 Normal Operation; 1 Initialization is started;Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

27.8.7 MCAN_NBTP Register (Offset = 1Ch) [Reset = 00000000h]

MCAN_NBTP is shown in Table 27-20.

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This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 m_can_cclk periods. tq = (NBRP + 1) mtq.;NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2.;Therefore the length of the bit time is (programmed values) (NTSEG1 + NTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq.;The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.;Note: With a CAN clock of 8 MHz, the reset value of 0x06000A03 configures the MCAN for a bit rate of 500 kBit/s.

Table 27-20 MCAN_NBTP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	NSJW	R/WQ	3h	Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
24-16	NBRP	R/WQ	0h	Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-8	NTSEG1	R/WQ	Ah	Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7	RESERVED	R	0h	Reserved
6-0	NTSEG2	R/WQ	3h	Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.8 MCAN_TSCC Register (Offset = 20h) [Reset = 00000000h]

MCAN_TSCC is shown in Table 27-21.

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MCAN Timestamp Counter Configuration

Table 27-21 MCAN_TSCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	TCP	R/WQ	0h	Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.; ;Note: With CAN FD an external counter is required for timestamp generation (TSS = "10").; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2	RESERVED	R	0h	Reserved
1-0	TSS	R/WQ	0h	Timestamp Select; 00 Timestamp counter value always 0x0000; 01 Timestamp counter value incremented according to TCP; 10 External timestamp counter value used; 11 Same as "00"; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.9 MCAN_TSCV Register (Offset = 24h) [Reset = 00000000h]

MCAN_TSCV is shown in Table 27-22.

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MCAN Timestamp Counter Value

Table 27-22 MCAN_TSCV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	TSC	R/W	0h	Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact.; ;Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not;caused by write access to MCAN_TSCV.

27.8.10 MCAN_TOCC Register (Offset = 28h) [Reset = 00000000h]

MCAN_TOCC is shown in Table 27-23.

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MCAN Timeout Counter Configuration

Table 27-23 MCAN_TOCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TOP	R/WQ	FFFFh	Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-3	RESERVED	R	0h	Reserved
2-1	TOS	R/WQ	0h	Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored.; 00 Continuous operation; 01 Timeout controlled by Tx Event FIFO; 10 Timeout controlled by Rx FIFO 0; 11 Timeout controlled by Rx FIFO 1; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0	ETOC	R/WQ	0h	Enable Timeout Counter; 0 Timeout Counter disabled; 1 Timeout Counter enabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.11 MCAN_TOCV Register (Offset = 2Ch) [Reset = 00000000h]

MCAN_TOCV is shown in Table 27-24.

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MCAN Timeout Counter Value

Table 27-24 MCAN_TOCV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	TOC	R/W	FFFFh	Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

27.8.12 MCAN_ECR Register (Offset = 40h) [Reset = 00000000h]

MCAN_ECR is shown in Table 27-25.

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MCAN Error Counter Register

Table 27-25 MCAN_ECR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-16	CEL	R	0h	CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.; ;Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
15	RP	R	0h	Receive Error Passive; 0 The Receive Error Counter is below the error passive level of 128; 1 The Receive Error Counter has reached the error passive level of 128
14-8	REC	R	0h	Receive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127.; ;Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
7-0	TEC	R	0h	Transmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255.; ;Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

27.8.13 MCAN_PSR Register (Offset = 44h) [Reset = 00000000h]

MCAN_PSR is shown in Table 27-26.

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MCAN Protocol Status Register

Table 27-26 MCAN_PSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	TDCV	R	0h	Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
15	RESERVED	R	0h	Reserved
14	PXE	R	0h	Protocol Exception Event; 0 No protocol exception event occurred since last read access; 1 Protocol exception event occurred
13	RFDF	R	0h	Received a CAN FD Message. This bit is set independent of acceptance filtering.; 0 Since this bit was reset by the CPU, no CAN FD message has been received; 1 Message in CAN FD format with FDF flag set has been received
12	RBRS	R	0h	BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.; 0 Last received CAN FD message did not have its BRS flag set; 1 Last received CAN FD message had its BRS flag set
11	RESI	R	0h	ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.; 0 Last received CAN FD message did not have its ESI flag set; 1 Last received CAN FD message had its ESI flag set
10-8	DLEC	R	7h	Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
7	BO	R	0h	Bus_Off Status; 0 The M_CAN is not Bus_Off; 1 The M_CAN is in Bus_Off state
6	EW	R	0h	Warning Status; 0 Both error counters are below the Error_Warning limit of 96; 1 At least one of error counter has reached the Error_Warning limit of 96
5	EP	R	0h	Error Passive; 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected; 1 The M_CAN is in the Error_Passive state
4-3	ACT	R	0h	Node Activity. Monitors the module's CAN communication state.; 00 Synchronizing - node is synchronizing on CAN communication; 01 Idle - node is neither receiver nor transmitter; 10 Receiver - node is operating as receiver; 11 Transmitter - node is operating as transmitter; ;Note: ACT is set to "00" by a Protocol Exception Event.
2-0	LEC	R	7h	Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.; 0 No Error: No error occurred since LEC has been reset by successful reception or transmission.; 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.; 2 Form Error: A fixed format part of a received frame has the wrong format.; 3 AckError: The message transmitted by the MCAN was not acknowledged by another node.; 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.; 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).; 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.; 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register.; ;Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.

27.8.14 MCAN_TDCR Register (Offset = 48h) [Reset = 00000000h]

MCAN_TDCR is shown in Table 27-27.

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MCAN Transmitter Delay Compensation Register

Table 27-27 MCAN_TDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R	0h	Reserved
14-8	TDCO	R/WQ	0h	Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7	RESERVED	R	0h	Reserved
6-0	TDCF	R/WQ	0h	Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.15 MCAN_IR Register (Offset = 50h) [Reset = 00000000h]

MCAN_IR is shown in Table 27-28.

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The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. Aflag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. Ahard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled.

Table 27-28 MCAN_IR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ARA	R/W	0h	Access to Reserved Address; 0 No access to reserved address occurred; 1 Access to reserved address occurred
28	PED	R/W	0h	Protocol Error in Data Phase (Data Bit Time is used); 0 No protocol error in data phase; 1 Protocol error in data phase detected (PSR.DLEC ? 0,7)
27	PEA	R/W	0h	Protocol Error in Arbitration Phase (Nominal Bit Time is used); 0 No protocol error in arbitration phase; 1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7)
26	WDI	R/W	0h	Watchdog Interrupt; 0 No Message RAM Watchdog event occurred; 1 Message RAM Watchdog event due to missing READY
25	BO	R/W	0h	Bus_Off Status; 0 Bus_Off status unchanged; 1 Bus_Off status changed
24	EW	R/W	0h	Warning Status; 0 Error_Warning status unchanged; 1 Error_Warning status changed
23	EP	R/W	0h	Error Passive; 0 Error_Passive status unchanged; 1 Error_Passive status changed
22	ELO	R/W	0h	Error Logging Overflow; 0 CAN Error Logging Counter did not overflow; 1 Overflow of CAN Error Logging Counter occurred
21	BEU	R/W	0h	Bit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.; 0 No bit error detected when reading from Message RAM; 1 Bit error detected, uncorrected (e.g. parity logic)
20	RESERVED	R	0h	Reserved
19	DRX	R/W	0h	Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer.; 0 No Rx Buffer updated; 1 At least one received message stored into an Rx Buffer
18	TOO	R/W	0h	Timeout Occurred; 0 No timeout; 1 Timeout reached
17	MRAF	R/W	0h	Message RAM Access Failure. The flag is set, when the Rx Handler:; - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.; - was not able to write a message to the Message RAM. In this case message storage is aborted.; ;In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.; ;The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.; 0 No Message RAM access failure occurred; 1 Message RAM access failure occurred
16	TSW	R/W	0h	Timestamp Wraparound; 0 No timestamp counter wrap-around; 1 Timestamp counter wrapped around
15	TEFL	R/W	0h	Tx Event FIFO Element Lost; 0 No Tx Event FIFO element lost; 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
14	TEFF	R/W	0h	Tx Event FIFO Full; 0 Tx Event FIFO not full; 1 Tx Event FIFO full
13	TEFW	R/W	0h	Tx Event FIFO Watermark Reached; 0 Tx Event FIFO fill level below watermark; 1 Tx Event FIFO fill level reached watermark
12	TEFN	R/W	0h	Tx Event FIFO New Entry; 0 Tx Event FIFO unchanged; 1 Tx Handler wrote Tx Event FIFO element
11	TFE	R/W	0h	Tx FIFO Empty; 0 Tx FIFO non-empty; 1 Tx FIFO empty
10	TCF	R/W	0h	Transmission Cancellation Finished; 0 No transmission cancellation finished; 1 Transmission cancellation finished
9	TC	R/W	0h	Transmission Completed; 0 No transmission completed; 1 Transmission completed
8	HPM	R/W	0h	High Priority Message; 0 No high priority message received; 1 High priority message received
7	RF1L	R/W	0h	Rx FIFO 1 Message Lost; 0 No Rx FIFO 1 message lost; 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
6	RF1F	R/W	0h	Rx FIFO 1 Full; 0 Rx FIFO 1 not full; 1 Rx FIFO 1 full
5	RF1W	R/W	0h	Rx FIFO 1 Watermark Reached; 0 Rx FIFO 1 fill level below watermark; 1 Rx FIFO 1 fill level reached watermark
4	RF1N	R/W	0h	Rx FIFO 1 New Message; 0 No new message written to Rx FIFO 1; 1 New message written to Rx FIFO 1
3	RF0L	R/W	0h	Rx FIFO 0 Message Lost; 0 No Rx FIFO 0 message lost; 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
2	RF0F	R/W	0h	Rx FIFO 0 Full; 0 Rx FIFO 0 not full; 1 Rx FIFO 0 full
1	RF0W	R/W	0h	Rx FIFO 0 Watermark Reached; 0 Rx FIFO 0 fill level below watermark; 1 Rx FIFO 0 fill level reached watermark
0	RF0N	R/W	0h	Rx FIFO 0 New Message; 0 No new message written to Rx FIFO 0; 1 New message written to Rx FIFO 0

27.8.16 MCAN_IE Register (Offset = 54h) [Reset = 00000000h]

MCAN_IE is shown in Table 27-29.

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MCAN Interrupt Enable

Table 27-29 MCAN_IE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ARAE	R/W	0h	Access to Reserved Address Enable
28	PEDE	R/W	0h	Protocol Error in Data Phase Enable
27	PEAE	R/W	0h	Protocol Error in Arbitration Phase Enable
26	WDIE	R/W	0h	Watchdog Interrupt Enable
25	BOE	R/W	0h	Bus_Off Status Enable
24	EWE	R/W	0h	Warning Status Enable
23	EPE	R/W	0h	Error Passive Enable
22	ELOE	R/W	0h	Error Logging Overflow Enable
21	BEUE	R/W	0h	Bit Error Uncorrected Enable
20	RESERVED	R	0h	Reserved
19	DRXE	R/W	0h	Message Stored to Dedicated Rx Buffer Enable
18	TOOE	R/W	0h	Timeout Occurred Enable
17	MRAFE	R/W	0h	Message RAM Access Failure Enable
16	TSWE	R/W	0h	Timestamp Wraparound Enable
15	TEFLE	R/W	0h	Tx Event FIFO Element Lost Enable
14	TEFFE	R/W	0h	Tx Event FIFO Full Enable
13	TEFWE	R/W	0h	Tx Event FIFO Watermark Reached Enable
12	TEFNE	R/W	0h	Tx Event FIFO New Entry Enable
11	TFEE	R/W	0h	Tx FIFO Empty Enable
10	TCFE	R/W	0h	Transmission Cancellation Finished Enable
9	TCE	R/W	0h	Transmission Completed Enable
8	HPME	R/W	0h	High Priority Message Enable
7	RF1LE	R/W	0h	Rx FIFO 1 Message Lost Enable
6	RF1FE	R/W	0h	Rx FIFO 1 Full Enable
5	RF1WE	R/W	0h	Rx FIFO 1 Watermark Reached Enable
4	RF1NE	R/W	0h	Rx FIFO 1 New Message Enable
3	RF0LE	R/W	0h	Rx FIFO 0 Message Lost Enable
2	RF0FE	R/W	0h	Rx FIFO 0 Full Enable
1	RF0WE	R/W	0h	Rx FIFO 0 Watermark Reached Enable
0	RF0NE	R/W	0h	Rx FIFO 0 New Message Enable

27.8.17 MCAN_ILS Register (Offset = 58h) [Reset = 00000000h]

MCAN_ILS is shown in Table 27-30.

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The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.

Table 27-30 MCAN_ILS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ARAL	R/W	0h	Access to Reserved Address Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
28	PEDL	R/W	0h	Protocol Error in Data Phase Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
27	PEAL	R/W	0h	Protocol Error in Arbitration Phase Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
26	WDIL	R/W	0h	Watchdog Interrupt Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
25	BOL	R/W	0h	Bus_Off Status Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
24	EWL	R/W	0h	Warning Status Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
23	EPL	R/W	0h	Error Passive Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
22	ELOL	R/W	0h	Error Logging Overflow Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
21	BEUL	R/W	0h	Bit Error Uncorrected Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
20	RESERVED	R	0h	Reserved
19	DRXL	R/W	0h	Message Stored to Dedicated Rx Buffer Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
18	TOOL	R/W	0h	Timeout Occurred Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
17	MRAFL	R/W	0h	Message RAM Access Failure Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
16	TSWL	R/W	0h	Timestamp Wraparound Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
15	TEFLL	R/W	0h	Tx Event FIFO Element Lost Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
14	TEFFL	R/W	0h	Tx Event FIFO Full Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
13	TEFWL	R/W	0h	Tx Event FIFO Watermark Reached Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
12	TEFNL	R/W	0h	Tx Event FIFO New Entry Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
11	TFEL	R/W	0h	Tx FIFO Empty Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
10	TCFL	R/W	0h	Transmission Cancellation Finished Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
9	TCL	R/W	0h	Transmission Completed Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
8	HPML	R/W	0h	High Priority Message Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
7	RF1LL	R/W	0h	Rx FIFO 1 Message Lost Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
6	RF1FL	R/W	0h	Rx FIFO 1 Full Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
5	RF1WL	R/W	0h	Rx FIFO 1 Watermark Reached Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
4	RF1NL	R/W	0h	Rx FIFO 1 New Message Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
3	RF0LL	R/W	0h	Rx FIFO 0 Message Lost Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
2	RF0FL	R/W	0h	Rx FIFO 0 Full Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
1	RF0WL	R/W	0h	Rx FIFO 0 Watermark Reached Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1
0	RF0NL	R/W	0h	Rx FIFO 0 New Message Line; 0 Interrupt source is assigned to Interrupt Line 0; 1 Interrupt source is assigned to Interrupt Line 1

27.8.18 MCAN_ILE Register (Offset = 5Ch) [Reset = 00000000h]

MCAN_ILE is shown in Table 27-31.

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MCAN Interrupt Line Enable

Table 27-31 MCAN_ILE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	EINT1	R/W	0h	Enable Interrupt Line 1; 0 Interrupt Line 1 is disabled; 1 Interrupt Line 1 is enabled
0	EINT0	R/W	0h	Enable Interrupt Line 0; 0 Interrupt Line 0 is disabled; 1 Interrupt Line 0 is enabled

27.8.19 MCAN_GFC Register (Offset = 80h) [Reset = 00000000h]

MCAN_GFC is shown in Table 27-32.

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MCAN Global Filter Configuration

Table 27-32 MCAN_GFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-4	ANFS	R/WQ	0h	Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.; 00 Accept in Rx FIFO 0; 01 Accept in Rx FIFO 1; 10 Reject; 11 Reject; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-2	ANFE	R/WQ	0h	Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.; 00 Accept in Rx FIFO 0; 01 Accept in Rx FIFO 1; 10 Reject; 11 Reject; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1	RRFS	R/WQ	0h	Reject Remote Frames Standard; 0 Filter remote frames with 11-bit standard IDs; 1 Reject all remote frames with 11-bit standard IDs; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0	RRFE	R/WQ	0h	Reject Remote Frames Extended; 0 Filter remote frames with 29-bit extended IDs; 1 Reject all remote frames with 29-bit extended IDs; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.20 MCAN_SIDFC Register (Offset = 84h) [Reset = 00000000h]

MCAN_SIDFC is shown in Table 27-33.

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MCAN Standard ID Filter Configuration

Table 27-33 MCAN_SIDFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-16	LSS	R/WQ	0h	List Size Standard; 0 No standard Message ID filter; 1-128 Number of standard Message ID filter elements; >128 Values greater than 128 are interpreted as 128
15-2	FLSSA	R/WQ	0h	Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address).
1-0	RESERVED	R	0h	Reserved

27.8.21 MCAN_XIDFC Register (Offset = 88h) [Reset = 00000000h]

MCAN_XIDFC is shown in Table 27-34.

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MCAN Extended ID Filter Configuration

Table 27-34 MCAN_XIDFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	LSE	R/WQ	0h	List Size Extended; 0 No extended Message ID filter; 1-64 Number of extended Message ID filter elements; >64 Values greater than 64 are interpreted as 64; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2	FLESA	R/WQ	0h	Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address).; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0	RESERVED	R	0h	Reserved

27.8.22 MCAN_XIDAM Register (Offset = 90h) [Reset = 00000000h]

MCAN_XIDAM is shown in Table 27-35.

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MCAN Extended ID and Mask

Table 27-35 MCAN_XIDAM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	0h	Reserved
28-0	EIDM	R/WQ	1FFFFFFFh	Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.23 MCAN_HPMS Register (Offset = 94h) [Reset = 00000000h]

MCAN_HPMS is shown in Table 27-36.

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This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Table 27-36 MCAN_HPMS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	FLST	R	0h	Filter List. Indicates the filter list of the matching filter element.; 0 Standard Filter List; 1 Extended Filter List
14-8	FIDX	R	0h	Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.
7-6	MSI	R	0h	Message Storage Indicator; 00 No FIFO selected; 01 FIFO message lost; 10 Message stored in FIFO 0; 11 Message stored in FIFO 1
5-0	BIDX	R	0h	Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'.

27.8.24 MCAN_NDAT1 Register (Offset = 98h) [Reset = 00000000h]

MCAN_NDAT1 is shown in Table 27-37.

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MCAN New Data 1

Table 27-37 MCAN_NDAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ND31	R/W	0h	New Data RX Buffer 31; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
30	ND30	R/W	0h	New Data RX Buffer 30; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
29	ND29	R/W	0h	New Data RX Buffer 29; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
28	ND28	R/W	0h	New Data RX Buffer 28; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
27	ND27	R/W	0h	New Data RX Buffer 27; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
26	ND26	R/W	0h	New Data RX Buffer 26; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
25	ND25	R/W	0h	New Data RX Buffer 25; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
24	ND24	R/W	0h	New Data RX Buffer 24; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
23	ND23	R/W	0h	New Data RX Buffer 23; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
22	ND22	R/W	0h	New Data RX Buffer 22; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
21	ND21	R/W	0h	New Data RX Buffer 21; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
20	ND20	R/W	0h	New Data RX Buffer 20; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
19	ND19	R/W	0h	New Data RX Buffer 19; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
18	ND18	R/W	0h	New Data RX Buffer 18; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
17	ND17	R/W	0h	New Data RX Buffer 17; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
16	ND16	R/W	0h	New Data RX Buffer 16; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
15	ND15	R/W	0h	New Data RX Buffer 15; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
14	ND14	R/W	0h	New Data RX Buffer 14; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
13	ND13	R/W	0h	New Data RX Buffer 13; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
12	ND12	R/W	0h	New Data RX Buffer 12; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
11	ND11	R/W	0h	New Data RX Buffer 11; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
10	ND10	R/W	0h	New Data RX Buffer 10; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
9	ND9	R/W	0h	New Data RX Buffer 9; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
8	ND8	R/W	0h	New Data RX Buffer 8; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
7	ND7	R/W	0h	New Data RX Buffer 7; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
6	ND6	R/W	0h	New Data RX Buffer 6; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
5	ND5	R/W	0h	New Data RX Buffer 5; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
4	ND4	R/W	0h	New Data RX Buffer 4; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
3	ND3	R/W	0h	New Data RX Buffer 3; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
2	ND2	R/W	0h	New Data RX Buffer 2; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
1	ND1	R/W	0h	New Data RX Buffer 1; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
0	ND0	R/W	0h	New Data RX Buffer 0; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message

27.8.25 MCAN_NDAT2 Register (Offset = 9Ch) [Reset = 00000000h]

MCAN_NDAT2 is shown in Table 27-38.

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MCAN New Data 2

Table 27-38 MCAN_NDAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ND63	R/W	0h	New Data RX Buffer 63; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
30	ND62	R/W	0h	New Data RX Buffer 62; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
29	ND61	R/W	0h	New Data RX Buffer 61; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
28	ND60	R/W	0h	New Data RX Buffer 60; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
27	ND59	R/W	0h	New Data RX Buffer 59; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
26	ND58	R/W	0h	New Data RX Buffer 58; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
25	ND57	R/W	0h	New Data RX Buffer 57; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
24	ND56	R/W	0h	New Data RX Buffer 56; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
23	ND55	R/W	0h	New Data RX Buffer 55; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
22	ND54	R/W	0h	New Data RX Buffer 54; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
21	ND53	R/W	0h	New Data RX Buffer 53; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
20	ND52	R/W	0h	New Data RX Buffer 52; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
19	ND51	R/W	0h	New Data RX Buffer 51; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
18	ND50	R/W	0h	New Data RX Buffer 50; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
17	ND49	R/W	0h	New Data RX Buffer 49; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
16	ND48	R/W	0h	New Data RX Buffer 48; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
15	ND47	R/W	0h	New Data RX Buffer 47; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
14	ND46	R/W	0h	New Data RX Buffer 46; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
13	ND45	R/W	0h	New Data RX Buffer 45; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
12	ND44	R/W	0h	New Data RX Buffer 44; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
11	ND43	R/W	0h	New Data RX Buffer 43; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
10	ND42	R/W	0h	New Data RX Buffer 42; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
9	ND41	R/W	0h	New Data RX Buffer 41; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
8	ND40	R/W	0h	New Data RX Buffer 40; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
7	ND39	R/W	0h	New Data RX Buffer 39; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
6	ND38	R/W	0h	New Data RX Buffer 38; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
5	ND37	R/W	0h	New Data RX Buffer 37; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
4	ND36	R/W	0h	New Data RX Buffer 36; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
3	ND35	R/W	0h	New Data RX Buffer 35; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
2	ND34	R/W	0h	New Data RX Buffer 34; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
1	ND33	R/W	0h	New Data RX Buffer 33; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message
0	ND32	R/W	0h	New Data RX Buffer 32; 0 Rx Buffer not updated; 1 Rx Buffer updated from new message

27.8.26 MCAN_RXF0C Register (Offset = A0h) [Reset = 00000000h]

MCAN_RXF0C is shown in Table 27-39.

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MCAN Rx FIFO 0 Configuration

Table 27-39 MCAN_RXF0C Register Field Descriptions

Bit	Field	Type	Reset	Description
31	F0OM	R/WQ	0h	FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode.; 0 FIFO 0 blocking mode; 1 FIFO 0 overwrite mode; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24	F0WM	R/WQ	0h	Rx FIFO 0 Watermark; 0 Watermark interrupt disabled; 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W); >64 Watermark interrupt disabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23	RESERVED	R	0h	Reserved
22-16	F0S	R/WQ	0h	Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1.; 0 No Rx FIFO 0; 1-64 Number of Rx FIFO 0 elements; >64 Values greater than 64 are interpreted as 64; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2	F0SA	R/WQ	0h	Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address).; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0	RESERVED	R	0h	Reserved

27.8.27 MCAN_RXF0S Register (Offset = A4h) [Reset = 00000000h]

MCAN_RXF0S is shown in Table 27-40.

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MCAN Rx FIFO 0 Status

Table 27-40 MCAN_RXF0S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	RF0L	R	0h	Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.; 0 No Rx FIFO 0 message lost; 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero; ;Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag.
24	F0F	R	0h	Rx FIFO 0 Full; 0 Rx FIFO 0 not full; 1 Rx FIFO 0 full
23-22	RESERVED	R	0h	Reserved
21-16	F0PI	R	0h	Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63.
15-14	RESERVED	R	0h	Reserved
13-8	F0GI	R	0h	Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63.
7	RESERVED	R	0h	Reserved
6-0	F0FL	R	0h	Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64.

27.8.28 MCAN_RXF0A Register (Offset = A8h) [Reset = 00000000h]

MCAN_RXF0A is shown in Table 27-41.

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MCAN Rx FIFO 0 Acknowledge

Table 27-41 MCAN_RXF0A Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	F0AI	R/W	0h	Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.

27.8.29 MCAN_RXBC Register (Offset = ACh) [Reset = 00000000h]

MCAN_RXBC is shown in Table 27-42.

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MCAN Rx Buffer Configuration

Table 27-42 MCAN_RXBC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-2	RBSA	R/WQ	0h	Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).; ;+I466
1-0	RESERVED	R	0h	Reserved

27.8.30 MCAN_RXF1C Register (Offset = B0h) [Reset = 00000000h]

MCAN_RXF1C is shown in Table 27-43.

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MCAN Rx FIFO 1 Configuration

Table 27-43 MCAN_RXF1C Register Field Descriptions

Bit	Field	Type	Reset	Description
31	F1OM	R/WQ	0h	FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode.; 0 FIFO 1 blocking mode; 1 FIFO 1 overwrite mode; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24	F1WM	R/WQ	0h	Rx FIFO 1 Watermark; 0 Watermark interrupt disabled; 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W); >64 Watermark interrupt disabled; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23	RESERVED	R	0h	Reserved
22-16	F1S	R/WQ	0h	Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1.; 0 No Rx FIFO 1; 1-64 Number of Rx FIFO 1 elements; >64 Values greater than 64 are interpreted as 64; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2	F1SA	R/WQ	0h	Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address).
1-0	RESERVED	R	0h	Reserved

27.8.31 MCAN_RXF1S Register (Offset = B4h) [Reset = 00000000h]

MCAN_RXF1S is shown in Table 27-44.

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MCAN Rx FIFO 1 Status

Table 27-44 MCAN_RXF1S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	DMS	R	0h	Debug Message Status; 00 Idle state, wait for reception of debug messages, DMA request is cleared; 01 Debug message A received; 10 Debug messages A, B received; 11 Debug messages A, B, C received, DMA request is set
29-26	RESERVED	R	0h	Reserved
25	RF1L	R	0h	Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.; 0 No Rx FIFO 1 message lost; 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero; ;Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag.
24	F1F	R	0h	Rx FIFO 1 Full; 0 Rx FIFO 1 not full; 1 Rx FIFO 1 full
23-22	RESERVED	R	0h	Reserved
21-16	F1PI	R	0h	Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63.
15-14	RESERVED	R	0h	Reserved
13-8	F1GI	R	0h	Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63.
7	RESERVED	R	0h	Reserved
6-0	F1FL	R	0h	Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64.

27.8.32 MCAN_RXF1A Register (Offset = B8h) [Reset = 00000000h]

MCAN_RXF1A is shown in Table 27-45.

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MCAN Rx FIFO 1 Acknowledge

Table 27-45 MCAN_RXF1A Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	F1AI	R/W	0h	Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.

27.8.33 MCAN_RXESC Register (Offset = BCh) [Reset = 00000000h]

MCAN_RXESC is shown in Table 27-46.

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Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.

Table 27-46 MCAN_RXESC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-8	RBDS	R/WQ	0h	Rx Buffer Data Field Size; 000 8 byte data field; 001 12 byte data field; 010 16 byte data field; 011 20 byte data field; 100 24 byte data field; 101 32 byte data field; 110 48 byte data field; 111 64 byte data field; ;Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7	RESERVED	R	0h	Reserved
6-4	F1DS	R/WQ	0h	Rx FIFO 1 Data Field Size; 000 8 byte data field; 001 12 byte data field; 010 16 byte data field; 011 20 byte data field; 100 24 byte data field; 101 32 byte data field; 110 48 byte data field; 111 64 byte data field; ;Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3	RESERVED	R	0h	Reserved
2-0	F0DS	R/WQ	0h	Rx FIFO 0 Data Field Size; 000 8 byte data field; 001 12 byte data field; 010 16 byte data field; 011 20 byte data field; 100 24 byte data field; 101 32 byte data field; 110 48 byte data field; 111 64 byte data field; ;Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.34 MCAN_TXBC Register (Offset = C0h) [Reset = 00000000h]

MCAN_TXBC is shown in Table 27-47.

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MCAN Tx Buffer Configuration

Table 27-47 MCAN_TXBC Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	TFQM	R/WQ	0h	Tx FIFO/Queue Mode; 0 Tx FIFO operation; 1 Tx Queue operation; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
29-24	TFQS	R/WQ	0h	Transmit FIFO/Queue Size; 0 No Tx FIFO/Queue; 1-32 Number of Tx Buffers used for Tx FIFO/Queue; >32 Values greater than 32 are interpreted as 32; ;Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23-22	RESERVED	R	0h	Reserved
21-16	NDTB	R/WQ	0h	Number of Dedicated Transmit Buffers; 0 No Dedicated Tx Buffers; 1-32 Number of Dedicated Tx Buffers; >32 Values greater than 32 are interpreted as 32; ;Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2	TBSA	R/WQ	0h	Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address).; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0	RESERVED	R	0h	Reserved

27.8.35 MCAN_TXFQS Register (Offset = C4h) [Reset = 00000000h]

MCAN_TXFQS is shown in Table 27-48.

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The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).

Table 27-48 MCAN_TXFQS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-22	RESERVED	R	0h	Reserved
21	TFQF	R	0h	Tx FIFO/Queue Full; 0 Tx FIFO/Queue not full; 1 Tx FIFO/Queue full
20-16	TFQP	R	0h	Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31.; ;Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
15-13	RESERVED	R	0h	Reserved
12-8	TFGI	R	0h	Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').; ;Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
7-6	RESERVED	R	0h	Reserved
5-0	TFFL	R	0h	Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

27.8.36 MCAN_TXESC Register (Offset = C8h) [Reset = 00000000h]

MCAN_TXESC is shown in Table 27-49.

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Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Table 27-49 MCAN_TXESC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	TBDS	R/WQ	0h	Tx Buffer Data Field Size; 000 8 byte data field; 001 12 byte data field; 010 16 byte data field; 011 20 byte data field; 100 24 byte data field; 101 32 byte data field; 110 48 byte data field; 111 64 byte data field; ;Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as "0xCC" (padding bytes).; ;Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

27.8.37 MCAN_TXBRP Register (Offset = CCh) [Reset = 00000000h]

MCAN_TXBRP is shown in Table 27-50.

Return to the Summary Table.

MCAN Tx Buffer Request Pending

Table 27-50 MCAN_TXBRP Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TRP31	R	0h	Transmission Request Pending 31. See description for bit 0.
30	TRP30	R	0h	Transmission Request Pending 30. See description for bit 0.
29	TRP29	R	0h	Transmission Request Pending 29. See description for bit 0.
28	TRP28	R	0h	Transmission Request Pending 28. See description for bit 0.
27	TRP27	R	0h	Transmission Request Pending 27. See description for bit 0.
26	TRP26	R	0h	Transmission Request Pending 26. See description for bit 0.
25	TRP25	R	0h	Transmission Request Pending 25. See description for bit 0.
24	TRP24	R	0h	Transmission Request Pending 24. See description for bit 0.
23	TRP23	R	0h	Transmission Request Pending 23. See description for bit 0.
22	TRP22	R	0h	Transmission Request Pending 22. See description for bit 0.
21	TRP21	R	0h	Transmission Request Pending 21. See description for bit 0.
20	TRP20	R	0h	Transmission Request Pending 20. See description for bit 0.
19	TRP19	R	0h	Transmission Request Pending 19. See description for bit 0.
18	TRP18	R	0h	Transmission Request Pending 18. See description for bit 0.
17	TRP17	R	0h	Transmission Request Pending 17. See description for bit 0.
16	TRP16	R	0h	Transmission Request Pending 16. See description for bit 0.
15	TRP15	R	0h	Transmission Request Pending 15. See description for bit 0.
14	TRP14	R	0h	Transmission Request Pending 14. See description for bit 0.
13	TRP13	R	0h	Transmission Request Pending 13. See description for bit 0.
12	TRP12	R	0h	Transmission Request Pending 12. See description for bit 0.
11	TRP11	R	0h	Transmission Request Pending 11. See description for bit 0.
10	TRP10	R	0h	Transmission Request Pending 10. See description for bit 0.
9	TRP9	R	0h	Transmission Request Pending 9. See description for bit 0.
8	TRP8	R	0h	Transmission Request Pending 8. See description for bit 0.
7	TRP7	R	0h	Transmission Request Pending 7. See description for bit 0.
6	TRP6	R	0h	Transmission Request Pending 6. See description for bit 0.
5	TRP5	R	0h	Transmission Request Pending 5. See description for bit 0.
4	TRP4	R	0h	Transmission Request Pending 4. See description for bit 0.
3	TRP3	R	0h	Transmission Request Pending 3. See description for bit 0.
2	TRP2	R	0h	Transmission Request Pending 2. See description for bit 0.
1	TRP1	R	0h	Transmission Request Pending 1. See description for bit 0.
0	TRP0	R	0h	Transmission Request Pending 0.; ;Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR.; ;TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).; ;A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.; ;After a cancellation has been requested, a finished cancellation is signalled via TXBCF;- after successful transmission together with the corresponding TXBTO bit;- when the transmission has not yet been started at the point of cancellation;- when the transmission has been aborted due to lost arbitration;- when an error occurred during frame transmission; ;In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions.; 0 No transmission request pending; 1 Transmission request pending; ;Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.

27.8.38 MCAN_TXBAR Register (Offset = D0h) [Reset = 00000000h]

MCAN_TXBAR is shown in Table 27-51.

Return to the Summary Table.

MCAN Tx Buffer Add Request

Table 27-51 MCAN_TXBAR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	AR31	R/WQ	0h	Add Request 31. See description for bit 0.
30	AR30	R/WQ	0h	Add Request 30. See description for bit 0.
29	AR29	R/WQ	0h	Add Request 29. See description for bit 0.
28	AR28	R/WQ	0h	Add Request 28. See description for bit 0.
27	AR27	R/WQ	0h	Add Request 27. See description for bit 0.
26	AR26	R/WQ	0h	Add Request 26. See description for bit 0.
25	AR25	R/WQ	0h	Add Request 25. See description for bit 0.
24	AR24	R/WQ	0h	Add Request 24. See description for bit 0.
23	AR23	R/WQ	0h	Add Request 23. See description for bit 0.
22	AR22	R/WQ	0h	Add Request 22. See description for bit 0.
21	AR21	R/WQ	0h	Add Request 21. See description for bit 0.
20	AR20	R/WQ	0h	Add Request 20. See description for bit 0.
19	AR19	R/WQ	0h	Add Request 19. See description for bit 0.
18	AR18	R/WQ	0h	Add Request 18. See description for bit 0.
17	AR17	R/WQ	0h	Add Request 17. See description for bit 0.
16	AR16	R/WQ	0h	Add Request 16. See description for bit 0.
15	AR15	R/WQ	0h	Add Request 15. See description for bit 0.
14	AR14	R/WQ	0h	Add Request 14. See description for bit 0.
13	AR13	R/WQ	0h	Add Request 13. See description for bit 0.
12	AR12	R/WQ	0h	Add Request 12. See description for bit 0.
11	AR11	R/WQ	0h	Add Request 11. See description for bit 0.
10	AR10	R/WQ	0h	Add Request 10. See description for bit 0.
9	AR9	R/WQ	0h	Add Request 9. See description for bit 0.
8	AR8	R/WQ	0h	Add Request 8. See description for bit 0.
7	AR7	R/WQ	0h	Add Request 7. See description for bit 0.
6	AR6	R/WQ	0h	Add Request 6. See description for bit 0.
5	AR5	R/WQ	0h	Add Request 5. See description for bit 0.
4	AR4	R/WQ	0h	Add Request 4. See description for bit 0.
3	AR3	R/WQ	0h	Add Request 3. See description for bit 0.
2	AR2	R/WQ	0h	Add Request 2. See description for bit 0.
1	AR1	R/WQ	0h	Add Request 1. See description for bit 0.
0	AR0	R/WQ	0h	Add Request 0.; ;Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.; 0 No transmission request added; 1 Transmission requested added; ;Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored.; ;Qualified Write is possible only with CCCR.CCE='0'

27.8.39 MCAN_TXBCR Register (Offset = D4h) [Reset = 00000000h]

MCAN_TXBCR is shown in Table 27-52.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Request

Table 27-52 MCAN_TXBCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CR31	R/WQ	0h	Cancellation Request 31. See description for bit 0.
30	CR30	R/WQ	0h	Cancellation Request 30. See description for bit 0.
29	CR29	R/WQ	0h	Cancellation Request 29. See description for bit 0.
28	CR28	R/WQ	0h	Cancellation Request 28. See description for bit 0.
27	CR27	R/WQ	0h	Cancellation Request 27. See description for bit 0.
26	CR26	R/WQ	0h	Cancellation Request 26. See description for bit 0.
25	CR25	R/WQ	0h	Cancellation Request 25. See description for bit 0.
24	CR24	R/WQ	0h	Cancellation Request 24. See description for bit 0.
23	CR23	R/WQ	0h	Cancellation Request 23. See description for bit 0.
22	CR22	R/WQ	0h	Cancellation Request 22. See description for bit 0.
21	CR21	R/WQ	0h	Cancellation Request 21. See description for bit 0.
20	CR20	R/WQ	0h	Cancellation Request 20. See description for bit 0.
19	CR19	R/WQ	0h	Cancellation Request 19. See description for bit 0.
18	CR18	R/WQ	0h	Cancellation Request 18. See description for bit 0.
17	CR17	R/WQ	0h	Cancellation Request 17. See description for bit 0.
16	CR16	R/WQ	0h	Cancellation Request 16. See description for bit 0.
15	CR15	R/WQ	0h	Cancellation Request 15. See description for bit 0.
14	CR14	R/WQ	0h	Cancellation Request 14. See description for bit 0.
13	CR13	R/WQ	0h	Cancellation Request 13. See description for bit 0.
12	CR12	R/WQ	0h	Cancellation Request 12. See description for bit 0.
11	CR11	R/WQ	0h	Cancellation Request 11. See description for bit 0.
10	CR10	R/WQ	0h	Cancellation Request 10. See description for bit 0.
9	CR9	R/WQ	0h	Cancellation Request 9. See description for bit 0.
8	CR8	R/WQ	0h	Cancellation Request 8. See description for bit 0.
7	CR7	R/WQ	0h	Cancellation Request 7. See description for bit 0.
6	CR6	R/WQ	0h	Cancellation Request 6. See description for bit 0.
5	CR5	R/WQ	0h	Cancellation Request 5. See description for bit 0.
4	CR4	R/WQ	0h	Cancellation Request 4. See description for bit 0.
3	CR3	R/WQ	0h	Cancellation Request 3. See description for bit 0.
2	CR2	R/WQ	0h	Cancellation Request 2. See description for bit 0.
1	CR1	R/WQ	0h	Cancellation Request 1. See description for bit 0.
0	CR0	R/WQ	0h	Cancellation Request 0.; ;Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.; 0 No cancellation pending; 1 Cancellation pending; ;Qualified Write is possible only with CCCR.CCE='0'

27.8.40 MCAN_TXBTO Register (Offset = D8h) [Reset = 00000000h]

MCAN_TXBTO is shown in Table 27-53.

Return to the Summary Table.

MCAN Tx Buffer Transmission Occurred

Table 27-53 MCAN_TXBTO Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TO31	R	0h	Transmission Occurred 31. See description for bit 0.
30	TO30	R	0h	Transmission Occurred 30. See description for bit 0.
29	TO29	R	0h	Transmission Occurred 29. See description for bit 0.
28	TO28	R	0h	Transmission Occurred 28. See description for bit 0.
27	TO27	R	0h	Transmission Occurred 27. See description for bit 0.
26	TO26	R	0h	Transmission Occurred 26. See description for bit 0.
25	TO25	R	0h	Transmission Occurred 25. See description for bit 0.
24	TO24	R	0h	Transmission Occurred 24. See description for bit 0.
23	TO23	R	0h	Transmission Occurred 23. See description for bit 0.
22	TO22	R	0h	Transmission Occurred 22. See description for bit 0.
21	TO21	R	0h	Transmission Occurred 21. See description for bit 0.
20	TO20	R	0h	Transmission Occurred 20. See description for bit 0.
19	TO19	R	0h	Transmission Occurred 19. See description for bit 0.
18	TO18	R	0h	Transmission Occurred 18. See description for bit 0.
17	TO17	R	0h	Transmission Occurred 17. See description for bit 0.
16	TO16	R	0h	Transmission Occurred 16. See description for bit 0.
15	TO15	R	0h	Transmission Occurred 15. See description for bit 0.
14	TO14	R	0h	Transmission Occurred 14. See description for bit 0.
13	TO13	R	0h	Transmission Occurred 13. See description for bit 0.
12	TO12	R	0h	Transmission Occurred 12. See description for bit 0.
11	TO11	R	0h	Transmission Occurred 11. See description for bit 0.
10	TO10	R	0h	Transmission Occurred 10. See description for bit 0.
9	TO9	R	0h	Transmission Occurred 9. See description for bit 0.
8	TO8	R	0h	Transmission Occurred 8. See description for bit 0.
7	TO7	R	0h	Transmission Occurred 7. See description for bit 0.
6	TO6	R	0h	Transmission Occurred 6. See description for bit 0.
5	TO5	R	0h	Transmission Occurred 5. See description for bit 0.
4	TO4	R	0h	Transmission Occurred 4. See description for bit 0.
3	TO3	R	0h	Transmission Occurred 3. See description for bit 0.
2	TO2	R	0h	Transmission Occurred 2. See description for bit 0.
1	TO1	R	0h	Transmission Occurred 1. See description for bit 0.
0	TO0	R	0h	Transmission Occurred 0.; ;Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.; 0 No transmission occurred; 1 Transmission occurred

27.8.41 MCAN_TXBCF Register (Offset = DCh) [Reset = 00000000h]

MCAN_TXBCF is shown in Table 27-54.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished

Table 27-54 MCAN_TXBCF Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CF31	R	0h	Cancellation Finished 31. See description for bit 0.
30	CF30	R	0h	Cancellation Finished 30. See description for bit 0.
29	CF29	R	0h	Cancellation Finished 29. See description for bit 0.
28	CF28	R	0h	Cancellation Finished 28. See description for bit 0.
27	CF27	R	0h	Cancellation Finished 27. See description for bit 0.
26	CF26	R	0h	Cancellation Finished 26. See description for bit 0.
25	CF25	R	0h	Cancellation Finished 25. See description for bit 0.
24	CF24	R	0h	Cancellation Finished 24. See description for bit 0.
23	CF23	R	0h	Cancellation Finished 23. See description for bit 0.
22	CF22	R	0h	Cancellation Finished 22. See description for bit 0.
21	CF21	R	0h	Cancellation Finished 21. See description for bit 0.
20	CF20	R	0h	Cancellation Finished 20. See description for bit 0.
19	CF19	R	0h	Cancellation Finished 19. See description for bit 0.
18	CF18	R	0h	Cancellation Finished 18. See description for bit 0.
17	CF17	R	0h	Cancellation Finished 17. See description for bit 0.
16	CF16	R	0h	Cancellation Finished 16. See description for bit 0.
15	CF15	R	0h	Cancellation Finished 15. See description for bit 0.
14	CF14	R	0h	Cancellation Finished 14. See description for bit 0.
13	CF13	R	0h	Cancellation Finished 13. See description for bit 0.
12	CF12	R	0h	Cancellation Finished 12. See description for bit 0.
11	CF11	R	0h	Cancellation Finished 11. See description for bit 0.
10	CF10	R	0h	Cancellation Finished 10. See description for bit 0.
9	CF9	R	0h	Cancellation Finished 9. See description for bit 0.
8	CF8	R	0h	Cancellation Finished 8. See description for bit 0.
7	CF7	R	0h	Cancellation Finished 7. See description for bit 0.
6	CF6	R	0h	Cancellation Finished 6. See description for bit 0.
5	CF5	R	0h	Cancellation Finished 5. See description for bit 0.
4	CF4	R	0h	Cancellation Finished 4. See description for bit 0.
3	CF3	R	0h	Cancellation Finished 3. See description for bit 0.
2	CF2	R	0h	Cancellation Finished 2. See description for bit 0.
1	CF1	R	0h	Cancellation Finished 1. See description for bit 0.
0	CF0	R	0h	Cancellation Finished 0.; ;Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.; 0 No transmit buffer cancellation; 1 Transmit buffer cancellation finished

27.8.42 MCAN_TXBTIE Register (Offset = E0h) [Reset = 00000000h]

MCAN_TXBTIE is shown in Table 27-55.

Return to the Summary Table.

MCAN Tx Buffer Transmission Interrupt Enable

Table 27-55 MCAN_TXBTIE Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TIE31	R/W	0h	Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
30	TIE30	R/W	0h	Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
29	TIE29	R/W	0h	Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
28	TIE28	R/W	0h	Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
27	TIE27	R/W	0h	Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
26	TIE26	R/W	0h	Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
25	TIE25	R/W	0h	Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
24	TIE24	R/W	0h	Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
23	TIE23	R/W	0h	Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
22	TIE22	R/W	0h	Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
21	TIE21	R/W	0h	Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
20	TIE20	R/W	0h	Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
19	TIE19	R/W	0h	Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
18	TIE18	R/W	0h	Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
17	TIE17	R/W	0h	Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
16	TIE16	R/W	0h	Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
15	TIE15	R/W	0h	Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
14	TIE14	R/W	0h	Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
13	TIE13	R/W	0h	Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
12	TIE12	R/W	0h	Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
11	TIE11	R/W	0h	Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
10	TIE10	R/W	0h	Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
9	TIE9	R/W	0h	Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
8	TIE8	R/W	0h	Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
7	TIE7	R/W	0h	Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
6	TIE6	R/W	0h	Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
5	TIE5	R/W	0h	Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
4	TIE4	R/W	0h	Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
3	TIE3	R/W	0h	Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
2	TIE2	R/W	0h	Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
1	TIE1	R/W	0h	Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable
0	TIE0	R/W	0h	Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit.; 0 Transmission interrupt disabled; 1 Transmission interrupt enable

27.8.43 MCAN_TXBCIE Register (Offset = E4h) [Reset = 00000000h]

MCAN_TXBCIE is shown in Table 27-56.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished Interrupt Enable

Table 27-56 MCAN_TXBCIE Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CFIE31	R/W	0h	Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
30	CFIE30	R/W	0h	Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
29	CFIE29	R/W	0h	Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
28	CFIE28	R/W	0h	Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
27	CFIE27	R/W	0h	Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
26	CFIE26	R/W	0h	Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
25	CFIE25	R/W	0h	Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
24	CFIE24	R/W	0h	Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
23	CFIE23	R/W	0h	Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
22	CFIE22	R/W	0h	Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
21	CFIE21	R/W	0h	Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
20	CFIE20	R/W	0h	Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
19	CFIE19	R/W	0h	Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
18	CFIE18	R/W	0h	Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
17	CFIE17	R/W	0h	Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
16	CFIE16	R/W	0h	Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
15	CFIE15	R/W	0h	Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
14	CFIE14	R/W	0h	Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
13	CFIE13	R/W	0h	Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
12	CFIE12	R/W	0h	Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
11	CFIE11	R/W	0h	Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
10	CFIE10	R/W	0h	Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
9	CFIE9	R/W	0h	Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
8	CFIE8	R/W	0h	Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
7	CFIE7	R/W	0h	Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
6	CFIE6	R/W	0h	Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
5	CFIE5	R/W	0h	Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
4	CFIE4	R/W	0h	Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
3	CFIE3	R/W	0h	Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
2	CFIE2	R/W	0h	Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
1	CFIE1	R/W	0h	Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled
0	CFIE0	R/W	0h	Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.; 0 Cancellation finished interrupt disabled; 1 Cancellation finished interrupt enabled

27.8.44 MCAN_TXEFC Register (Offset = F0h) [Reset = 00000000h]

MCAN_TXEFC is shown in Table 27-57.

Return to the Summary Table.

MCAN Tx Event FIFO Configuration

Table 27-57 MCAN_TXEFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29-24	EFWM	R/WQ	0h	Event FIFO Watermark; 0 Watermark interrupt disabled; 1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW); >32 Watermark interrupt disabled
23-22	RESERVED	R	0h	Reserved
21-16	EFS	R/WQ	0h	Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1.; 0 Tx Event FIFO disabled; 1-32 Number of Tx Event FIFO elements; >32 Values greater than 32 are interpreted as 32
15-2	EFSA	R/WQ	0h	Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address).
1-0	RESERVED	R	0h	Reserved

27.8.45 MCAN_TXEFS Register (Offset = F4h) [Reset = 00000000h]

MCAN_TXEFS is shown in Table 27-58.

Return to the Summary Table.

MCAN Tx Event FIFO Status

Table 27-58 MCAN_TXEFS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	TEFL	R	0h	Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.; 0 No Tx Event FIFO element lost; 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
24	EFF	R	0h	Event FIFO Full; 0 Tx Event FIFO not full; 1 Tx Event FIFO full
23-21	RESERVED	R	0h	Reserved
20-16	EFPI	R	0h	Event FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31.
15-13	RESERVED	R	0h	Reserved
12-8	EFGI	R	0h	Event FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31.
7-6	RESERVED	R	0h	Reserved
5-0	EFFL	R	0h	Event FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32.

27.8.46 MCAN_TXEFA Register (Offset = F8h) [Reset = 00000000h]

MCAN_TXEFA is shown in Table 27-59.

Return to the Summary Table.

MCAN Tx Event FIFO Acknowledge

Table 27-59 MCAN_TXEFA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4-0	EFAI	R/W	0h	Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.

27.8.47 MCANSS_PID Register (Offset = 200h) [Reset = 00000000h]

MCANSS_PID is shown in Table 27-60.

Return to the Summary Table.

MCAN Subsystem Revision Register

Table 27-60 MCANSS_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID Register Scheme
29-28	BU	R	2h	Business Unit: 0x2 = Processors
27-16	MODULE_ID	R	8E0h	Module Identification Number
15-11	RTL	R	9h	RTL revision. Will vary depending on release
10-8	MAJOR	R	1h	Major Revision of the MCAN Subsystem
7-6	CUSTOM	R	0h	Custom Value
5-0	MINOR	R	1h	Minor Revision of the MCAN Subsystem

27.8.48 MCANSS_CTRL Register (Offset = 204h) [Reset = 00000000h]

MCANSS_CTRL is shown in Table 27-61.

Return to the Summary Table.

MCAN Subsystem Control Register

Table 27-61 MCANSS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	EXT_TS_CNTR_EN	R/W	0h	External Timestamp Counter Enable. When disabled, the counter is reset back to zero.While enabled, the counter keeps incrementing.; 0 External timestamp counter disabled; 1 External timestamp counter enabled
5	AUTOWAKEUP	R/W	0h	Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request.; 0 Disable the automatic write to CCCR.INIT; 1 Enable the automatic write to CCCR.INIT
4	WAKEUPREQEN	R/W	0h	Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity.; 0 Disable wakeup request; 1 Enables wakeup request
3	DBGSUSP_FREE	R/W	1h	Debug Suspend Free Bit. Enables debug suspend.; 0 Disable debug suspend; 1 Enable debug suspend
2-0	RESERVED	R	0h	Reserved

27.8.49 MCANSS_STAT Register (Offset = 208h) [Reset = 00000000h]

MCANSS_STAT is shown in Table 27-62.

Return to the Summary Table.

MCAN Subsystem Status Register

Table 27-62 MCANSS_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	ENABLE_FDOE	R	0h	Flexible Datarate Operation Enable. Determines whether CAN FD operation can be enabled via the MCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the MCAN.; 0 MCAN is only capable of standard CAN communication; 1 MCAN may be configured to perform CAN FD communication
1	MEM_INIT_DONE	R	0h	Memory Initialization Done.; 0 Message RAM initialization is in progress; 1 Message RAM is initialized for use
0	RESERVED	R	0h	Reserved

27.8.50 MCANSS_ICS Register (Offset = 20Ch) [Reset = 00000000h]

MCANSS_ICS is shown in Table 27-63.

Return to the Summary Table.

MCAN Subsystem Interrupt Clear Shadow Register

Table 27-63 MCANSS_ICS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EXT_TS_CNTR_OVFL	R-0/W	0h	External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0.; 0 Write of '0' has no effect; 1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit

27.8.51 MCANSS_IRS Register (Offset = 210h) [Reset = 00000000h]

MCANSS_IRS is shown in Table 27-64.

Return to the Summary Table.

MCAN Subsystem Interrupt Raw Status Register

Table 27-64 MCANSS_IRS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EXT_TS_CNTR_OVFL	R/W	0h	External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit.; 0 External timestamp counter has not overflowed; 1 External timestamp counter has overflowed; ;When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1.

27.8.52 MCANSS_IECS Register (Offset = 214h) [Reset = 00000000h]

MCANSS_IECS is shown in Table 27-65.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Clear Shadow Register

Table 27-65 MCANSS_IECS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EXT_TS_CNTR_OVFL	R-0/W	0h	External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0.; 0 Write of '0' has no effect; 1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit

27.8.53 MCANSS_IE Register (Offset = 218h) [Reset = 00000000h]

MCANSS_IE is shown in Table 27-66.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Register

Table 27-66 MCANSS_IE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EXT_TS_CNTR_OVFL	R/W	0h	External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' unmasks the MCAN_IRS.EXT_EVT_CNTR_OVFLW and reflects the unmasked IRS value in MCAN_IES.EXT_TS_CNTR_OVFL

27.8.54 MCANSS_IES Register (Offset = 21Ch) [Reset = 00000000h]

MCANSS_IES is shown in Table 27-67.

Return to the Summary Table.

MCAN Subsystem Masked Interrupt Status. It is the logical AND of IRS and IE for the respecitve bits.

Table 27-67 MCANSS_IES Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EXT_TS_CNTR_OVFL	R	0h	External Timestamp Counter Overflow masked interrupt status.; 0 External timestamp counter overflow interrupt is cleared; 1 External timestamp counter overflow interrupt is set

27.8.55 MCANSS_EOI Register (Offset = 220h) [Reset = 00000000h]

MCANSS_EOI is shown in Table 27-68.

Return to the Summary Table.

MCAN Subsystem End of Interrupt

Table 27-68 MCANSS_EOI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	EOI	R-0/W	0h	End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated.; 0x00 External TS Interrupt is cleared; 0x01 MCAN(0) interrupt is cleared; 0x02 MCAN(1) interrupt is cleared; Other writes are ignored.

27.8.56 MCANSS_EXT_TS_PRESCALER Register (Offset = 224h) [Reset = 00000000h]

MCANSS_EXT_TS_PRESCALER is shown in Table 27-69.

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MCAN Subsystem External Timestamp Prescaler 0

Table 27-69 MCANSS_EXT_TS_PRESCALER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	PRESCALER	R/W	Xh	External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001.

27.8.57 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register (Offset = 228h) [Reset = 00000000h]

MCANSS_EXT_TS_UNSERVICED_INTR_CNTR is shown in Table 27-70.

Return to the Summary Table.

MCAN Subsystem External Timestamp Unserviced Interrupts Counter

Table 27-70 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4-0	EXT_TS_INTR_CNTR	R	0h	External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt.; ;The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field.

27.8.58 MCANERR_REV Register (Offset = 400h) [Reset = 00000000h]

MCANERR_REV is shown in Table 27-71.

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MCAN Error Aggregator Revision Register

Table 27-71 MCANERR_REV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID Register Scheme
29-28	BU	R	2h	Business Unit: 0x2 = Processors
27-16	MODULE_ID	R	6A0h	Module Identification Number
15-11	REVRTL	R	1Dh	RTL revision. Will vary depending on release
10-8	REVMAJ	R	2h	Major Revision of the Error Aggregator
7-6	REVCUSTOM	R	0h	Custom Revision of the Error Aggregator
5-0	REVMIN	R	0h	Minor Revision of the Error Aggregator

27.8.59 MCANERR_VECTOR Register (Offset = 408h) [Reset = 00000000h]

MCANERR_VECTOR is shown in Table 27-72.

Return to the Summary Table.

Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.

Table 27-72 MCANERR_VECTOR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RD_SVBUS_DONE	R	0h	Read Completion Flag
23-16	RD_SVBUS_ADDRESS	R/W	0h	Read Address Offset
15	RD_SVBUS	R-0/W	0h	Read Trigger
14-11	RESERVED	R	0h	Reserved
10-0	ECC_VECTOR	R/W	0h	ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.; 0x000 Message RAM ECC controller is selected; Others Reserved (do not use); ;Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing.

27.8.60 MCANERR_STAT Register (Offset = 40Ch) [Reset = 00000000h]

MCANERR_STAT is shown in Table 27-73.

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MCAN Error Misc Status

Table 27-73 MCANERR_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-0	NUM_RAMS	R	2h	Number of RAMs. Number of ECC RAMs serviced by the aggregator.