SPRADO8 March   2025 AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 User's Guide Usage Guidelines
      1. 1.1.1 Custom Board Design - Implementation References
      2. 1.1.2 Processor Family Specific User's Guide
      3. 1.1.3 Schematic Design Guidelines
      4. 1.1.4 Schematic Review Checklist
      5. 1.1.5 FAQ Reference for User's Guide Usage Guidelines
    2. 1.2 List of Processors
      1. 1.2.1 AM62Lx Processor Family
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Available and Applicable Collaterals
    2. 2.2 Hardware Design Considerations for Custom Board Design
  6. 3 Processor Selection
    1. 3.1 AM62Lx Processor Family Change Summary (With Respect to AM62x Processor Family)
    2. 3.2 Data Sheet Use Case and Version Referenced
    3. 3.3 Processor Selection (OPN Orderable Part Number)
    4. 3.4 Peripheral Instance Naming Convention
    5. 3.5 Unused Peripherals
    6. 3.6 Processor Ordering and Quality
    7. 3.7 Processor Selection Checklist
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM62Lx
        1. 4.1.1.1 Power Management IC (PMIC)
          1. 4.1.1.1.1 PMIC Based Power Architecture Checklist for TPS65214x
          2. 4.1.1.1.2 Additional References
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
          3. 4.1.1.2.3 Discrete Power Checklist
    2. 4.2 Power Control and Circuit Protection
      1. 4.2.1 Load Switch (Power Switching)
        1. 4.2.1.1 Load Switch Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (EVM)
      1. 5.1.1 Evaluation Module Checklist
    2. 5.2 Processor-Specific EVM Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistor
        7. 5.2.1.7 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding Reuse of EVM Design
        1. 5.2.2.1 Updated EVM Schematic With Design, Review and CAD Notes Added
        2. 5.2.2.2 EVM Design Files Reuse
          1. 5.2.2.2.1 Modular Schematic Sections
          2. 5.2.2.2.2 Reuse of EVM Design Checklist
    3. 5.3 Before Beginning the Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.3.4  RSVD Reserved Pin (Signal)
      5. 5.3.5  Note on PADCONFIG Registers
      6. 5.3.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.3.7  Reference to Processor-Specific EVM
      8. 5.3.8  High-Speed Interface Design Guidelines
      9. 5.3.9  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      10. 5.3.10 Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      11. 5.3.11 Queries and Clarifications Related to Processor During Custom Board Design
      12. 5.3.12 Before Beginning the Design Checklist
      13. 5.3.13 Device Recommendations
  9. 6 Processor-Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supply for Core and Peripherals
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling / Change
          2. 6.1.1.1.2 AM62Lx
          3. 6.1.1.1.3 Additional Information
          4. 6.1.1.1.4 Processor Core and Peripheral Core Power Supply Checklist
          5. 6.1.1.1.5 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 IO Supply for IO Groups
          1. 6.1.1.2.1 Dual-voltage 1.8V/3.3V IO Supply for IO Groups
            1. 6.1.1.2.1.1 Dual-voltage IO Supply for IO Groups Checklist
          2. 6.1.1.2.2 Fixed-voltage 1.8V IO Supply for (Peripheral) IO Groups
            1. 6.1.1.2.2.1 Fixed-voltage 1.8V IO Supply for (Peripheral) IO Groups Checklist
          3. 6.1.1.2.3 Additional Information
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 VPP Checklist
        4. 6.1.1.4 Supply Connection for Configuring Low-Power Modes
          1. 6.1.1.4.1 RTC Only Low-power Mode
            1. 6.1.1.4.1.1 RTC Only Mode Used
              1. 6.1.1.4.1.1.1 RTC_PORz Delay When RTC Only Mode is Used
              2. 6.1.1.4.1.1.2 EVM Implementation of RTC Only Mode Power Supply Architecture
            2. 6.1.1.4.1.2 RTC Only Mode Not Used
              1. 6.1.1.4.1.2.1 32kHz LFOSC0 Clock When RTC Mode is not Used
            3. 6.1.1.4.1.3 RTC Only Low-power Mode Checklist
          2. 6.1.1.4.2 RTC + IO + DDR Self-refresh Low-power Mode
            1. 6.1.1.4.2.1 RTC + IO + DDR Self-refresh Mode Used
            2. 6.1.1.4.2.2 RTC + IO + DDR Self-refresh Mode Not Used
            3. 6.1.1.4.2.3 RTC + IO + DDR Self-refresh Low-power Mode Checklist
          3. 6.1.1.4.3 DeepSleep, Standby
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62Lx
        2. 6.1.2.2 Additional Information
          1. 6.1.2.2.1 AM62Lx
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (WKUP_OSC0_XI / WKUP_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (LFOSC0_XI, LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
          4. 6.1.3.1.4 Additional Information
          5. 6.1.3.1.5 Clock Input Checklist - WKUP_OSC0
          6. 6.1.3.1.6 Clock Input Checklist - LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Input Checklist
        5. 6.1.4.5 Processor Reset Status Output Checklist
      5. 6.1.5 Configuration of Boot Modes for Processor
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG and EMU Used
      2. 6.2.2 JTAG and EMU Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for IO Supply for IO Groups
      1. 7.1.1 Dual-voltage IO Supplies and Fixed-voltage Supplies for IO Groups
      2. 7.1.2 Fixed 1.8V
      3. 7.1.3 Supply Connections for IO Supply for IO Groups Checklist
    2. 7.2 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD/SDIO), OSPI/QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 AM62Lx
            1. 7.2.1.1.1.1 Memory Interface Configuration
            2. 7.2.1.1.1.2 Routing Topology and Terminations
            3. 7.2.1.1.1.3 Resistors for Control and Calibration
            4. 7.2.1.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.1.1.5 Data Bit or Byte Swapping
            6. 7.2.1.1.1.6 VTT Termination Schematics Reference
            7. 7.2.1.1.1.7 DDR4 Implementation Checklist
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 AM62Lx
            1. 7.2.1.2.1.1 Memory Interface Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Resistors for Control and Calibration
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
            6. 7.2.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 AM62Lx
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC (Attached Device) Reset
            3. 7.2.2.1.1.3 Signals Connection
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.2.1.1.5 MMC0 (eMMC) Checklist
          2. 7.2.2.1.2 Additional Information on eMMC PHY
          3. 7.2.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.2.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.2.2.2.1 IO Power Supply
          2. 7.2.2.2.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.2.3 Signals Connection
          4. 7.2.2.2.4 ESD Protection
          5. 7.2.2.2.5 Capacitors for the Power Supply Rails
          6. 7.2.2.2.6 MMC1 SD Card Interface Checklist
        3. 7.2.2.3 MMC1 / MMC2 SDIO (Embedded) Interface
          1. 7.2.2.3.1 IO Power Supply
          2. 7.2.2.3.2 Signals Connection
          3. 7.2.2.3.3 MMC2 SDIO (Embedded) Interface Checklist
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 OSPI0 Interfaced to Single Device
          1. 7.2.3.1.1 IO Power Supply
          2. 7.2.3.1.2 OSPI or QSPI Device Reset
          3. 7.2.3.1.3 Signals Connection
          4. 7.2.3.1.4 Loopback Clock
        2. 7.2.3.2 Interfaced to x2 Devices
        3. 7.2.3.3 Capacitors for the Power Supply Rails
        4. 7.2.3.4 OSPI or QSPI Interface Implementation Checklist
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Connection
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
        6. 7.2.4.6 GPMC Interface Checklist
    3. 7.3 External Communication Interface (Ethernet (CPSW3G0), USB2.0, UART and MCAN)
      1. 7.3.1 Ethernet Interface Using CPSW3G0 (Common Platform Ethernet Switch 3-Port Gigabit)
        1. 7.3.1.1  IO Power Supply
        2. 7.3.1.2  Ethernet PHY Reset
        3. 7.3.1.3  Ethernet PHY Pin Strapping
        4. 7.3.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5  MAC (Data, Control and Clock) Interface Signals Connection
        6. 7.3.1.6  External Interrupt (EXTINTn)
          1. 7.3.1.6.1 External Interrupt (EXTINTn) Checklist
        7. 7.3.1.7  MAC (Media Access Controller) to MAC Interface
        8. 7.3.1.8  MDIO (Management Data Input/Output) Interface
        9. 7.3.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
        10. 7.3.1.10 Capacitors for the Power Supply Rails
        11. 7.3.1.11 Ethernet Interface Checklist
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USBn (n = 0-1) Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
          4. 7.3.2.1.4 USB Type-C®
        2. 7.3.2.2 USBn (n = 0-1) Not Used
        3. 7.3.2.3 Additional Information
        4. 7.3.2.4 USB Interface Checklist
      3. 7.3.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.3.3.1 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.3.4 Modular Controller Area Network (MCAN)
        1. 7.3.4.1 Modular Controller Area Network Checklist
    4. 7.4 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
        1. 7.4.1.1 MCSPI Checklist
        2. 7.4.1.2 MCASP Checklist
      2. 7.4.2 Inter-Integrated Circuit (I2C)
        1. 7.4.2.1 I2C (Open-drain Output Type Buffer) Interface Checklist
        2. 7.4.2.2 I2C (Emulated Open-drain Output Type Buffer) Interface Checklist
    5. 7.5 User Interface (DPI, DSI), GPIO and Hardware Diagnostics
      1. 7.5.1 Display Subsystem
        1. 7.5.1.1 Display Parallel Interface (DPI)
          1. 7.5.1.1.1 AM62Lx
            1. 7.5.1.1.1.1 IO Power Supply
            2. 7.5.1.1.1.2 DPI (Attached Device) Reset
            3. 7.5.1.1.1.3 Connection
            4. 7.5.1.1.1.4 Signals Connection
            5. 7.5.1.1.1.5 Capacitors for the Power Supply Rails
            6. 7.5.1.1.1.6 DPI (VOUT0) Checklist
        2. 7.5.1.2 Display Serial Interface (DSI)
          1. 7.5.1.2.1 AM62Lx
            1. 7.5.1.2.1.1 DSITX0 Used
              1. 7.5.1.2.1.1.1 DSITX0 Checklist
            2. 7.5.1.2.1.2 DSITX0 Not Used
      2. 7.5.2 General Purpose Input and Output (GPIO)
        1. 7.5.2.1 Availability of CLKOUT on Processor GPIO
        2. 7.5.2.2 Connection and External Buffering
        3. 7.5.2.3 Additional Information
        4. 7.5.2.4 GPIO Checklist
      3. 7.5.3 On-board Hardware Diagnostics
        1. 7.5.3.1 Internal Temperature Monitoring
    6. 7.6 Analog to Digital Converter (ADC)
      1. 7.6.1 ADC0 Used
      2. 7.6.2 ADC0 Not Used
      3. 7.6.3 ADC0 Checklist
    7. 7.7 Verifying Board Level Design Issues
      1. 7.7.1 Processor Pin Configuration Using PinMux Tool
      2. 7.7.2 Schematics Configurations
      3. 7.7.3 Connecting Supply Rails to Pullups
      4. 7.7.4 Peripheral (Subsystem) Clock Outputs
      5. 7.7.5 General Board Bring-up and Debug
        1. 7.7.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.7.5.2 Additional Information
        3. 7.7.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of the Custom Board Schematics Design
  12. 9 Layout Notes (Added on the Schematic)
    1. 9.1 Layout Checklist
  13. 10Custom Board Design Simulation
  14. 11Additional References
    1. 11.1 FAQ Covering AM6xx Processor Family
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Processor Attached Devices
  15. 12Summary
  16. 13Terminology

7.4.2.1 I2C (Open-drain Output Type Buffer) Interface Checklist

General

Review and verify the following for the custom schematic design:

  1. Above section including relevant application notes and FAQ links.
  2. Pin connectivity requirements, pin attributes and signal description.
  3. Electrical characteristics (fail-safe and slew rate requirements when pulled to 3.3V), timing parameters and any additional available information including exceptions.
  4. Add an RC at the input of the open-drain IOs for slew rate control when pulled to 3.3V.
  5. Attached device address pin connected to IO supply through a resistor (> 1kΩ).
  6. Verify the target I2C interface clock rates. The I2C bus can only be operated as fast as the slowest peripheral on the bus. If faster operation is required, move the slow devices to another I2C port.
  7. Verify that there are no I2C address conflicts on any of the I2C interface utilized. There are multiple I2C ports available on the processor, so if a conflict is seen, move the conflicting devices to a different I2C bus. If not possible, use an I2C bus switch.
  8. Do not place more than one set of pullup resistors on the I2C lines, can result in excessive loading and potential incorrect operation. Choose the pullup value commensurate with the bus speed being utilized.
  9. Make sure that the supply rail powering the processor I2C IO supply for IO group matches the supply voltage used for the pullup resistors and the attached I2C devices. Proper pullup can prevent device damage or incorrect operation due to voltage mismatch.

Schematic Review

Follow the below list for the custom schematic design:

  1. I2C2 (only when using the selected device package pins with "I2C OD FS" Buffer Type. Example: B8, D8 for ANB package) controllers have dedicated I2C compliant open-drain output type buffers.
  2. Verify the pullup values used. Compare with the EVM schematics or calculate based on the load.
  3. The I2C pullup supply amplitude connected follows the steady-state maximum voltage at all fail-safe IO pins requirements. The supply threshold depends on the supply voltage connected to IO supply for IO group.
  4. Provision for RC to limit slew rate and RC values.
  5. Processor VDDSHVx or VDDSx and the attached device IO sourced from the same supply.
  6. Supply rails connected follow the ROC.

Additional

  1. Verify recommendations as per the data sheet or EVM implementation have been considered for the attached device.
  2. Review the Timing and switching characteristics, I2C Exceptions sections of the data sheet during the design stage.