CDCLVP2104
- Dual 1:4 Differential Buffer
- Two Clock Inputs
- Universal Inputs Can Accept LVPECL,
LVDS, LVCMOS/LVTTL - Eight LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 78 mA
- Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range - 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum 15 ps Within Bank Output Skew
- LVPECL Reference Voltage, VAC_REF,
Available for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to +85°C
- Supports 105°C PCB Temperature (Measured with a Thermal Pad)
- Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
- ESD Protection Exceeds 2000 V (HBM)
The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. B) | PDF | HTML | 2013年 10月 25日 |
User guide | CDCLVP2104 User's Guide | 2009年 10月 21日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
CDCLVP2104EVM — CDCLVP2104 評估模組
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
---|---|---|
VQFN (RHD) | 28 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點