CDCLVP1208

現行

低抖動 2 輸入可選 1:8 通用至 LVPECL 緩衝器

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產品規格表

document-pdfAcrobat CDCLVP1208 Eight LVPECL Output, High-Performance Clock 2:8 Buffer datasheet (Rev. E) (英文) PDF | HTML

CDCLVP1208

現行

立即訂購

產品詳細資料

Number of outputs

8

Additive RMS jitter (typ) (fs)

57

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

8

Additive RMS jitter (typ) (fs)

57

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHD)

28

25 mm² (5 mm × 5 mm)

2:8 Differential Buffer
Selectable Clock Inputs Through Control terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
Eight LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 73 mA
Very Low Additive Jitter: <100 fs,rms in 10 kHz to
20 MHz Offset Range:
- 57 fs, rms (typical) at 122.88 MHz
- 48 fs, rms (typical) at 156.25 MHz
- 30 fs, rms (typical) at 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum Output Skew: 20 ps
LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Supports 105°C PCB Temperature
(Measured with a Thermal Pad)
ESD Protection Exceeds 2 kV (HBM)
Available in 5-mm × 5-mm QFN-28 (RHD)
Package

2:8 Differential Buffer
Selectable Clock Inputs Through Control terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
Eight LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 73 mA
Very Low Additive Jitter: <100 fs,rms in 10 kHz to
20 MHz Offset Range:
- 57 fs, rms (typical) at 122.88 MHz
- 48 fs, rms (typical) at 156.25 MHz
- 30 fs, rms (typical) at 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum Output Skew: 20 ps
LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Supports 105°C PCB Temperature
(Measured with a Thermal Pad)
ESD Protection Exceeds 2 kV (HBM)
Available in 5-mm × 5-mm QFN-28 (RHD)
Package

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	CDCLVP1208 Eight LVPECL Output, High-Performance Clock 2:8 Buffer datasheet (Rev. E)	PDF \| HTML		2015/11/23
	使用指南	CDCLVP1208 User's Guide			2009/10/21

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CDCLVP1208EVM — CDCLVP1208 評估模組

The CDCLVP1208 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL (...)

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