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LMK1D1216

現行

16 通道輸出 1.8-V、2.5-V 和 3.3-V LVDS 緩衝器

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LMK1D1216

現行
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產品詳細資料

Number of outputs 16 Additive RMS jitter (typ) (fs) 45 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Number of outputs 16 Additive RMS jitter (typ) (fs) 45 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RGZ) 48 49 mm² 7 x 7
  • High-performance LVDS clock buffer family: up to 2 GHz
    • 2:12 differential buffer (LMK1D1212)
    • 2:16 differential buffer (LMK1D1216)
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)
  • High-performance LVDS clock buffer family: up to 2 GHz
    • 2:12 differential buffer (LMK1D1212)
    • 2:16 differential buffer (LMK1D1216)
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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重要文件 類型 標題 格式選項 日期
* Data sheet LMK1D121x Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 2023年 4月 12日
Certificate LMK1D1216EVM EU RoHS Declaration of Conformity (DoC) 2021年 8月 19日

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LMK1D1216EVM — LMK1D1216 低抖動 2:16 LVDS 扇出緩衝器評估模組

LMK1D1216 是具有兩個差動輸入和 16 個 LVDS 輸出的高性能、低附加抖動 LVDS 時脈緩衝器。此評估模組 (EVM) 旨在示範 LMK1D1216 的電氣性能。此 EVM 也可評估 LMK1Dxxxx 系列內的其他 48 接腳裝置。LMK1D1216EVM 配備 50-Ω SMA 連接器和阻抗控制的 50-Ω 微帶傳輸線，以提供最佳性能。
使用指南: PDF | HTML
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LMK1DX IBIS Model (Rev. B)

SNAM251B.ZIP (67 KB) - IBIS Model
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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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