CDCLVP111-EP

現行

具可選輸入的 HiRel 1:10 LVPECL 緩衝器

立即訂購

產品規格表

document-pdfAcrobat CDCLVP111-EP Low-Voltage 1:10 LVPECL with Selectable Input Clock Driver.. datasheet (英文)

CDCLVP111-EP

現行

產品規格表

立即訂購

產品詳細資料

Number of outputs

10

Additive RMS jitter (typ) (fs)

40

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

50

Operating temperature range (°C)

-55 to 125

Rating

HiRel Enhanced Product

Output type

LVPECL

Input type

CML, LVDS, LVPECL, SSTL

Number of outputs

10

Additive RMS jitter (typ) (fs)

40

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

50

Operating temperature range (°C)

-55 to 125

Rating

HiRel Enhanced Product

Output type

LVPECL

Input type

CML, LVDS, LVPECL, SSTL

LQFP (VF)

32

81 mm² (9 mm × 9 mm)

Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
Fully Compatible With LVECL and LVPECL
Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
Selectable Clock Input Through CLK_SEL
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
- Additive Jitter Less Than 1 ps
- Propagation Delay Less Than 355 ps
- Open Input Default State
- LVDS, CML, SSTL input compatible
V_BB Reference Voltage Output for Single-Ended Clocking
Available in a 32-Pin LQFP Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
Fully Compatible With LVECL and LVPECL
Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
Selectable Clock Input Through CLK_SEL
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
- Additive Jitter Less Than 1 ps
- Propagation Delay Less Than 355 ps
- Open Input Default State
- LVDS, CML, SSTL input compatible
V_BB Reference Voltage Output for Single-Ended Clocking
Available in a 32-Pin LQFP Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 is characterized for operation from –55°C to 125°C.

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 is characterized for operation from –55°C to 125°C.

filter

尋找其它時鐘緩衝器

下載觀看有字幕稿的影片影片