SWCU195A December   2024  â€“ May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755P10 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

6.4.6 PMCTL Registers

Table 6-4 lists the memory-mapped registers for the PMCTL registers. All register offset addresses not listed in Table 6-4 should be considered as reserved locations and the register contents should not be modified.

Table 6-4 PMCTL Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register.Section 6.4.6.1
4hDESCEXExtended Description Register.Section 6.4.6.2
8hSHTDWNShutdown Register.Section 6.4.6.3
ChSLPCTLSleep Control Register.Section 6.4.6.4
10hWUSTAWakeup Status RegisterSection 6.4.6.5
14hVDDRCTLVDDR Control Register.Section 6.4.6.6
20hSYSFSETInternal. Only to be used through TI provided API.Section 6.4.6.7
24hSYSFCLRInternal. Only to be used through TI provided API.Section 6.4.6.8
28hSYSFSTAInternal. Only to be used through TI provided API.Section 6.4.6.9
2ChRSTCTLReset Control Register.Section 6.4.6.10
30hRSTSTAReset Status.Section 6.4.6.11
34hBOOTSTAInternal. Only to be used through TI provided API.Section 6.4.6.12
3ChAONRSTA1AON Register Status 1.Section 6.4.6.13
40hAONRSET1AON Register Set 1.Section 6.4.6.14
44hAONRCLR1AON register clear 1Section 6.4.6.15
4ChDELTADelta Time Register.Section 6.4.6.16
50hWUTIMEWakeUp Time Register.Section 6.4.6.17
54hPREPUCTLPre Power-Up Control Register.Section 6.4.6.18
58hSWSTMPSW Time Stamp Register.Section 6.4.6.19
64hETPPInternal. Only to be used through TI provided API.Section 6.4.6.20
7ChRETCFG0Internal. Only to be used through TI provided API.Section 6.4.6.21
80hRETCFG1Internal. Only to be used through TI provided API.Section 6.4.6.22
84hRETCFG2Internal. Only to be used through TI provided API.Section 6.4.6.23
88hRETCFG3Internal. Only to be used through TI provided API.Section 6.4.6.24
8ChRETCFG4Internal. Only to be used through TI provided API.Section 6.4.6.25
90hRETCFG5Internal. Only to be used through TI provided API.Section 6.4.6.26
94hRETCFG6Internal. Only to be used through TI provided API.Section 6.4.6.27
98hRETCFG7Internal. Only to be used through TI provided API.Section 6.4.6.28
A8hHFXTCTLHFXT Control Register.Section 6.4.6.29
AChLFCALLow Frequency Calibration Register.Section 6.4.6.30
B0hVREFCFGInternal. Only to be used through TI provided API.Section 6.4.6.31
B4hVREFSTAVREF Status Register.Section 6.4.6.32

Complex bit access types are encoded to fit into small table cells. Table 6-5 shows the codes that are used for access types in this section.

Table 6-5 PMCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.4.6.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 6-6.

Return to the Summary Table.

Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 6-6 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDRD741hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR0hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR2hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

6.4.6.2 DESCEX Register (Offset = 4h) [Reset = 00000000h]

DESCEX is shown in Table 6-7.

Return to the Summary Table.

Extended Description Register.
This register shows ULL IP availability and memory size configuration.

Table 6-7 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-30FLASHSZR3hSystem flash availability
  • 0h = Flash size set to level 0 (Min size)
  • 1h = Flash size set to level 1
  • 2h = Flash size set to level 2
  • 3h = Flash size set to level 3 (Max size)
29-28SRAMSZR3hSystem SRAM availability
  • 0h = SRAM size set to level 0 (Min size)
  • 1h = SRAM size set to level 1
  • 2h = SRAM size set to level 2
  • 3h = SRAM size set to level 3 (Max size)
27RESERVEDR0hReserved
26LPCMPR1hLPCMP (low power comparator) IP status on device
  • 0h = IP is unavailable
  • 1h = IP is available
25-0RESERVEDR0hReserved

6.4.6.3 SHTDWN Register (Offset = 8h) [Reset = 00000000h]

SHTDWN is shown in Table 6-8.

Return to the Summary Table.

Shutdown Register.
This register controls SHUTDOWN mode entry.

Table 6-8 SHTDWN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0KEYW0hSetting a valid key will trigger the device to enter SHUTDOWN mode.
  • A5A5h = This is the only valid key value that will trigger SHUTDOWN mode.;All other values are invalid and will have no effect.

6.4.6.4 SLPCTL Register (Offset = Ch) [Reset = 00000000h]

SLPCTL is shown in Table 6-9.

Return to the Summary Table.

Sleep Control Register.
This register controls I/O pad sleep mode. When I/O pad sleep mode is enabled all I/O pad outputs and I/O pad configurations are latched. Inputs are transparent if I/O pad is configured as input.

Table 6-9 SLPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SLPNR/W0hThe boot code will set this bit field and disable sleep mode, automatically unless waking up from a SHUTDOWN RSTSTA.SDDET is set.
Application software must reconfigure the state for all IO's before setting this bit field upon waking up from a SHUTDOWN to avoid glitches on pins.
  • 0h = I/O pad sleep mode is enabled
  • 1h = I/O pad sleep mode is disabled

6.4.6.5 WUSTA Register (Offset = 10h) [Reset = 00000000h]

WUSTA is shown in Table 6-10.

Return to the Summary Table.

Wakeup Status Register
This register shows the device wakeup source. Used to distinguish between wakeup from STANDBY, SHUTDOWN and reset.

Table 6-10 WUSTA Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SRCR1hThis field shows the device wakeup source.
  • 1h = Wakeup from system reset / SHUTDOWN mode. ;See RSTSTA for more status information.
  • 2h = Wakeup from STANDBY mode.

6.4.6.6 VDDRCTL Register (Offset = 14h) [Reset = 00000000h]

VDDRCTL is shown in Table 6-11.

Return to the Summary Table.

VDDR Control Register.
This register contains VDDR regulator settings for the device.

Table 6-11 VDDRCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1STBYR/W0hSelect between continuous or duty-cycled VDDR regulation in STANDBY mode.
  • 0h = Duty-cycled VDDR regulation in STANDBY mode.
  • 1h = Continuous VDDR regulation in STANDBY mode.
0SELECTR/W0hSelect between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY mode).
  • 0h = GLDO enabled for regulation of VDDR voltage
  • 1h = DCDC enabled for regulation of VDDR voltage

6.4.6.7 SYSFSET Register (Offset = 20h) [Reset = 00000000h]

SYSFSET is shown in Table 6-12.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-12 SYSFSET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2FLAG2W0hInternal. Only to be used through TI provided API.
1FLAG1W0hInternal. Only to be used through TI provided API.
0FLAG0W0hInternal. Only to be used through TI provided API.

6.4.6.8 SYSFCLR Register (Offset = 24h) [Reset = 00000000h]

SYSFCLR is shown in Table 6-13.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-13 SYSFCLR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2FLAG2W0hInternal. Only to be used through TI provided API.
1FLAG1W0hInternal. Only to be used through TI provided API.
0FLAG0W0hInternal. Only to be used through TI provided API.

6.4.6.9 SYSFSTA Register (Offset = 28h) [Reset = 00000000h]

SYSFSTA is shown in Table 6-14.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-14 SYSFSTA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2FLAG2R0hInternal. Only to be used through TI provided API.
1FLAG1R0hInternal. Only to be used through TI provided API.
0FLAG0R0hInternal. Only to be used through TI provided API.

6.4.6.10 RSTCTL Register (Offset = 2Ch) [Reset = 00000000h]

RSTCTL is shown in Table 6-15.

Return to the Summary Table.

Reset Control Register.
This register configures and controls system reset.

Table 6-15 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3VGMDLYNR/W0hVDD glitch monitor delay.
This bit configures if exit out of STANDBY will be stalled until VGM has settled or not.
When bypassed the CPU execution will potentially start before the VGM is ready.
  • 0h = Ensure that VGM has settled before we exit STANDBY.
  • 1h = VGM settling will not stall exit out of STANDBY.
2LFLOSSR/W0hLF clock loss reset enable.
Trigger system reset when LF clock loss is detected, which reset the entire device and causes a reboot of the system.
The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to LFLOSSEV.
  • 0h = LF clock loss detection will not trigger a system reset.
  • 1h = LF clock loss detection will trigger a system reset.
1TSDENR/W0hTSD (Thermal Shutdown) enable.
TSD will trigger an immediate system reset, which reset the entire device and causes a reboot of the system.
The device will be in reset until released by the TSD IP.
The system reset event is captured as RSTSTA.TSDEV flag set.
  • 0h = No effect
  • 1h = Temperature shutdown comparator enable. ;Note: If TSD IP not present, see DESCEX.TSD, enable will have no effect.
0SYSRSTR/W0hTrigger system reset, which will reset the entire device and causes a reboot of the system.
The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to SYSRSTEV.
  • 0h = No effect
  • 1h = Trigger a system reset.

6.4.6.11 RSTSTA Register (Offset = 30h) [Reset = 00000000h]

RSTSTA is shown in Table 6-16.

Return to the Summary Table.

Reset Status.
This register contains the reset source and SHUTDOWN wakeup source for the system.
Check WUSTA.SRC first to ensure that wakeup from STANDBY is not set.
The capture feature is not rearmed until all of the possible reset sources have been released and the result has been copied to this register.
During the copy and rearm process it is one 24MHz period in which an eventual new system reset will be reported as Power on reset regardless of the root cause.

Table 6-16 RSTSTA Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17SDDETR0hWakeup from SHUTDOWN flag.
Note: This flag will be cleared when SLPCTL.SLPN is asserted.
  • 0h = Wakeup from SHUTDOWN mode not triggered.
  • 1h = Wakeup from SHUTDOWN mode
16IOWUSDR0hWakeup from SHUTDOWN on an I/O event flag.
Note: This flag will be cleared when SLPCTL.SLPN is asserted.
  • 0h = Wakeup from SHUTDOWN not triggered by an I/O event.
  • 1h = Wakeup from SHUTDOWN triggered by an I/O event.
15RTCSTAR0hRTC TIME reset status.
This bit shows if the last system reset event cleared RTC TIME or not.
  • 0h = System reset event cleared RTC TIME
  • 1h = System reset event did not clear RTC TIME
14-8RESERVEDR0hReserved
7-4SYSSRCR0hShows which reset event that triggered SYSRESET in RESETSRC.
  • 0h = LF clock loss event
  • 1h = CPU reset event
  • 2h = CPU LOCKUP event
  • 3h = Watchdog timeout event
  • 4h = System reset event
  • 5h = Serial Wire Debug reset event
  • 6h = Analog FSM timeout event
  • 7h = Electromagnetic sensor event
  • 8h = Tamper event
  • 9h = SRAM parity error event
  • Eh = Analog Error reset event
  • Fh = Digital Error reset event
3TSDEVR0hSystem reset triggered by TSD event
  • 0h = TSD event not triggered
  • 1h = System reset triggered by TSD event
2-0RESETSRCR0hShows the root cause of the last system reset. More than one reported reset source can have been active during the last system reset, but only the root cause is reported.
If reset cause is SYSRESET or PINRESET, the other reset flags must be read to determine actual root cause.
  • 0h = Power on reset
  • 1h = Reset pin. TSD will also trigger a pin reset, so actual root cause is given by TSDEV reset flag status.
  • 2h = Brown out detect on VDDS
  • 4h = Brown out detect on VDDR
  • 6h = Digital system reset. Actual root cause is given by SYSSRC.
  • 7h = VDD glitch detection reset

6.4.6.12 BOOTSTA Register (Offset = 34h) [Reset = 00000000h]

BOOTSTA is shown in Table 6-17.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-17 BOOTSTA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0FLAGR/W0hInternal. Only to be used through TI provided API.

6.4.6.13 AONRSTA1 Register (Offset = 3Ch) [Reset = 00000000h]

AONRSTA1 is shown in Table 6-18.

Return to the Summary Table.

AON Register Status 1.
This register contains the general purpose AON flags for SW, and is updated through AONRSET1.FLAG and AONRCLR1.FLAG.
The register is only reset on a POR event.

Table 6-18 AONRSTA1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20VDDIOPGIOR0hVDDIO power good.
Controls the I/O pads on the VDDIO segment.
19-18RESERVEDR0hReserved
17-0FLAGRXhState of the AON register flags

6.4.6.14 AONRSET1 Register (Offset = 40h) [Reset = 00000000h]

AONRSET1 is shown in Table 6-19.

Return to the Summary Table.

AON Register Set 1.
This register sets the AON flags that can be read through AONRSTA1.FLAG.

Table 6-19 AONRSET1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20VDDIOPGIOW0hWrite 1 to set AONRSTA1.VDDIOPGIO.
  • 0h = No effect
  • 1h = Set flag
19-18RESERVEDR0hReserved
17-0FLAGWXhWrite 1 to set AONRSTA1.FLAG
  • 0h = No flags changed status
  • 0003FFFFh = Set all flags

6.4.6.15 AONRCLR1 Register (Offset = 44h) [Reset = 00000000h]

AONRCLR1 is shown in Table 6-20.

Return to the Summary Table.

AON register clear 1
Clear the AON flags that can be read through AONRSTA1.FLAG

Table 6-20 AONRCLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20VDDIOPGIOW0hWrite 1 to clear AONRSTA1.VDDIOPGIO.
  • 0h = No effect
  • 1h = Clear flag
19-18RESERVEDR0hReserved
17-0FLAGWXhWrite 1 to clear AONRSTA1.FLAG
  • 0h = No flags changed status
  • 0003FFFFh = Clear all flags

6.4.6.16 DELTA Register (Offset = 4Ch) [Reset = 00000000h]

DELTA is shown in Table 6-21.

Return to the Summary Table.

Delta Time Register.
This register contains the measured delta time during wakeup from STANDBY mode.

Table 6-21 DELTA Register Field Descriptions
BitFieldTypeResetDescription
31-30SLWPR0hSlow part.
States which of HFXT ready or SW ready that completed first during wakeup from STANDBY mode.
  • 0h = No valid measurement available
  • 1h = HFXT ready set before SW ready (SWSTMP.SWRDY)
  • 2h = HFXT ready set after SW ready (SWSTMP.SWRDY)
  • 3h = No valid measurement available
29-12RESERVEDR0hReserved
11-0TIMER0hDelta time.
Measured time in us between SWSTMP.SWRDY and HFXT ready.
This is a always a positive number, and SLWP is used to determine which event occurred first.
Measurement is enabled when PREPUCTL.WUTIMEN is set.

6.4.6.17 WUTIME Register (Offset = 50h) [Reset = 00000000h]

WUTIME is shown in Table 6-22.

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WakeUp Time Register.
This register contains the measured wakeup times from STANDBY mode.

Table 6-22 WUTIME Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16DIGWUR0hDigital wakeup time.
Gives the time (in us) from HFSOC is running until CPU execution starts.
Measurement is enabled when PREPUCTL.WUTIMEN is set.
15-8RESERVEDR0hReserved
7-0HFXTWUR0hHFXT wakeup time.
Gives the time (in us) from HFSOC is running until HFXT auto enable is triggered.
Measurement is enabled when PREPUCTL.WUTIMEN is set.

6.4.6.18 PREPUCTL Register (Offset = 54h) [Reset = 00000000h]

PREPUCTL is shown in Table 6-23.

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Pre Power-Up Control Register.
This register contains settings and control for pre-powerup, STANDBY and wakeup measurements.

Table 6-23 PREPUCTL Register Field Descriptions
BitFieldTypeResetDescription
31PREPUENR/W0hPre powerup Enable.
When this bit is set, the device will start the wakeup process in advance of the RTC wakeup event.
This to start HFXT settling earlier, so that HFXT can be ready when SW is ready.
Note that HFXTCTL.AUTO must be enabled to turn on HFXT.
  • 0h = Disable pre-powerup
  • 1h = Enable pre-powerup
30WUTIMENR/W0hWakeup time measurement enable.
When set will enable WUTIME.DIGWU, WUTIME.HFXTWU and DELTA.TIME time measurements.
  • 0h = Disable wakeup time measurement
  • 1h = Enable wakeup time measurement
29-16RESERVEDR0hReserved
15-8CONSR/W0hConservative pre-wakeup time.
When PREPUEN is set, the device will start the wakeup process in advance of the RTC wakeup event.
This field will give the conservative time in advance of a RTC event. Conservative value is used if a temperature change has been detected since STANDBY mode was entered.
The time unit for the value is 8us.
  • 0h = Smallest value
  • FEh = Highest possible value
7-0NOMR/W0hNominal pre-wakeup time.
When PREPUEN is set, the device will start the wakeup process in advance of the RTC wakeup event.
This field will give the nominal time in advance of a RTC event. Nominal value is used if no temperature change has been detected since STANDBY mode was entered.
The time unit for the value is 8us.
  • 0h = Smallest value
  • FEh = Highest possible value

6.4.6.19 SWSTMP Register (Offset = 58h) [Reset = 00000000h]

SWSTMP is shown in Table 6-24.

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SW Time Stamp Register.
This register is used to set the SW time stamp for the delta time measurement.

Table 6-24 SWSTMP Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SWRDYR/W0hSW ready.
Set by SW to indicate when SW is ready. Used to measure DELTA.TIME and DELTA.SLWP.
This bit is auto-cleared by HW.
  • 0h = No effect
  • 1h = Set SW ready time stamp. Auto-cleared by HW

6.4.6.20 ETPP Register (Offset = 64h) [Reset = 00000000h]

ETPP is shown in Table 6-25.

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Internal. Only to be used through TI provided API.

Table 6-25 ETPP Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

6.4.6.21 RETCFG0 Register (Offset = 7Ch) [Reset = 00000000h]

RETCFG0 is shown in Table 6-26.

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Internal. Only to be used through TI provided API.

Table 6-26 RETCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-1RESERVEDR0hReserved
0VALR/W1hInternal. Only to be used through TI provided API.

6.4.6.22 RETCFG1 Register (Offset = 80h) [Reset = 00000000h]

RETCFG1 is shown in Table 6-27.

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Internal. Only to be used through TI provided API.

Table 6-27 RETCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-1RESERVEDR0hReserved
0VALR/W1hInternal. Only to be used through TI provided API.

6.4.6.23 RETCFG2 Register (Offset = 84h) [Reset = 00000000h]

RETCFG2 is shown in Table 6-28.

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Internal. Only to be used through TI provided API.

Table 6-28 RETCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-1RESERVEDR0hReserved
0VALR/W1hInternal. Only to be used through TI provided API.

6.4.6.24 RETCFG3 Register (Offset = 88h) [Reset = 00000000h]

RETCFG3 is shown in Table 6-29.

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Internal. Only to be used through TI provided API.

Table 6-29 RETCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-1RESERVEDR0hReserved
0VALR/W0hInternal. Only to be used through TI provided API.

6.4.6.25 RETCFG4 Register (Offset = 8Ch) [Reset = 00000000h]

RETCFG4 is shown in Table 6-30.

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Internal. Only to be used through TI provided API.

Table 6-30 RETCFG4 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-3RESERVEDR0hReserved
2-0VALR/W0hInternal. Only to be used through TI provided API.

6.4.6.26 RETCFG5 Register (Offset = 90h) [Reset = 00000000h]

RETCFG5 is shown in Table 6-31.

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Internal. Only to be used through TI provided API.

Table 6-31 RETCFG5 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-2RESERVEDR0hReserved
1-0VALR/W1hInternal. Only to be used through TI provided API.

6.4.6.27 RETCFG6 Register (Offset = 94h) [Reset = 00000000h]

RETCFG6 is shown in Table 6-32.

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Internal. Only to be used through TI provided API.

Table 6-32 RETCFG6 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-2RESERVEDR0hReserved
1-0VALR/W0hInternal. Only to be used through TI provided API.

6.4.6.28 RETCFG7 Register (Offset = 98h) [Reset = 00000000h]

RETCFG7 is shown in Table 6-33.

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Internal. Only to be used through TI provided API.

Table 6-33 RETCFG7 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0hInternal. Only to be used through TI provided API.
30-3RESERVEDR0hReserved
2-0VALR/W1hInternal. Only to be used through TI provided API.

6.4.6.29 HFXTCTL Register (Offset = A8h) [Reset = 00000000h]

HFXTCTL is shown in Table 6-34.

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HFXT Control Register.
This register controls features to turn on/off HFXT automatically.

Table 6-34 HFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1LFCALR/W0hLF Calibration Enable.
Turn on/off HFXT periodically to perform LF oscillator calibration.
LF oscillator period and measurement time is configured through LFCAL.
  • 0h = HFXT on/off periodically for LF calibration is disabled.
  • 1h = HFXT on/off periodically for LF calibration is enabled.
0AUTOR/W1hTurn on/off HFXT during STANDBY entry/exit.
  • 0h = HFXT is neither turned on/off during STANDBY entry/exit
  • 1h = HFXT turned off when entring STANDBY and turned on when leaving STANDBY.

6.4.6.30 LFCAL Register (Offset = ACh) [Reset = 00000000h]

LFCAL is shown in Table 6-35.

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Low Frequency Calibration Register.
This register contains the period and measurement time setting used for LF oscillator calibration.
The LF calibartion feature is enabled through HFXTCTL.LFCAL.

Table 6-35 LFCAL Register Field Descriptions
BitFieldTypeResetDescription
31QUALR/W0hCKM qualifier configuration.
Used to qualify that LF calibration is completed before HFXT is request off.
  • 0h = Disable CKM qualifier
  • 1h = Enable CKM qualifier
30-24RESERVEDR0hReserved
23-16MEASR/W0hLFCAL measurment time, given in number of 32kHz periods.
  • FFh = Maximum LFCAL measurment time
15-8RESERVEDR0hReserved
7-0PERR/W0hLFCAL period time, given in number of 256 * 32kHz periods.
  • FFh = Maximum LFCAL period time

6.4.6.31 VREFCFG Register (Offset = B0h) [Reset = 00000000h]

VREFCFG is shown in Table 6-36.

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Internal. Only to be used through TI provided API.

Table 6-36 VREFCFG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0TIMEOUTR/W11hInternal. Only to be used through TI provided API.

6.4.6.32 VREFSTA Register (Offset = B4h) [Reset = 00000000h]

VREFSTA is shown in Table 6-37.

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VREF Status Register.
This register contains VREF settling status.

Table 6-37 VREFSTA Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0GOODR0hVREF settling / good status.
  • 0h = VREF voltage is not good.
  • 1h = VREF voltage is good.