SWCU195A December   2024  â€“ May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755P10 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

22.9 IOC Registers

Table 22-3 lists the memory-mapped registers for the IOC registers. All register offset addresses not listed in Table 22-3 should be considered as reserved locations and the register contents should not be modified.

Table 22-3 IOC Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionSection 22.9.1
4hDESCEXExtended Module DescriptionSection 22.9.2
100hIOC0ConfigurationSection 22.9.3
104hIOC1ConfigurationSection 22.9.4
108hIOC2ConfigurationSection 22.9.5
10ChIOC3ConfigurationSection 22.9.6
110hIOC4ConfigurationSection 22.9.7
114hIOC5ConfigurationSection 22.9.8
118hIOC6ConfigurationSection 22.9.9
11ChIOC7ConfigurationSection 22.9.10
120hIOC8ConfigurationSection 22.9.11
124hIOC9ConfigurationSection 22.9.12
128hIOC10ConfigurationSection 22.9.13
12ChIOC11ConfigurationSection 22.9.14
130hIOC12ConfigurationSection 22.9.15
134hIOC13ConfigurationSection 22.9.16
138hIOC14ConfigurationSection 22.9.17
13ChIOC15ConfigurationSection 22.9.18
140hIOC16ConfigurationSection 22.9.19
144hIOC17ConfigurationSection 22.9.20
148hIOC18ConfigurationSection 22.9.21
14ChIOC19ConfigurationSection 22.9.22
150hIOC20ConfigurationSection 22.9.23
154hIOC21ConfigurationSection 22.9.24
158hIOC22ConfigurationSection 22.9.25
15ChIOC23ConfigurationSection 22.9.26
160hIOC24ConfigurationSection 22.9.27
164hIOC25ConfigurationSection 22.9.28
168hIOC26ConfigurationSection 22.9.29
16ChIOC27ConfigurationSection 22.9.30
170hIOC28ConfigurationSection 22.9.31
174hIOC29ConfigurationSection 22.9.32
178hIOC30ConfigurationSection 22.9.33
C00hDTBCFGDTB configurationSection 22.9.34
C04hDTBOEDTB output enableSection 22.9.35
C08hEVTCFGEvent configurationSection 22.9.36
C0ChTESTTestSection 22.9.37
C10hDTBSTATDTB statusSection 22.9.38
C14hDTBMUXCFG0**DTB** mux configuration 0 register. This register is used to configure DTB level 0 and level 1 mux layers.Section 22.9.39
C18hDTBMUXCFG1**DTB** mux configuration 1 register. This register is used to configure DTB level 2 and level 3 mux layers.Section 22.9.40

Complex bit access types are encoded to fit into small table cells. Table 22-4 shows the codes that are used for access types in this section.

Table 22-4 IOC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

22.9.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 22-5.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 22-5 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDRD440hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

22.9.2 DESCEX Register (Offset = 4h) [Reset = 00000000h]

DESCEX is shown in Table 22-6.

Return to the Summary Table.

Extended Description Register. This register provides configuration details of the IP to software drivers and end users.

Table 22-6 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12NUMDTBIORFhNumber of DTB IOs supported. Total DTB IOs supported is NUMDTBIO value +1.
  • 0h = Smallest value
  • Fh = Highest possible value
11-7NUMHDIOR5hNumber of high drive IOs supported. Total high drive IOs supported is NUMHDIO value +1.
  • 0h = Smallest value
  • 1Fh = Highest possible value
6HDIOR1hHigh drive IO supported by IOC.
  • 0h = HD IO not supported by IOC
  • 1h = HD IO supported by IOC
5-0NUMDIOR1EhNumber of DIOs supported. Total DIOs supported is NUMDIO value +1.
  • 0h = Smallest value
  • 3Fh = Highest possible value

22.9.3 IOC0 Register (Offset = 100h) [Reset = 00000000h]

IOC0 is shown in Table 22-7.

Return to the Summary Table.

Configuration of DIO0

Table 22-7 IOC0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO0
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.4 IOC1 Register (Offset = 104h) [Reset = 00000000h]

IOC1 is shown in Table 22-8.

Return to the Summary Table.

Configuration of DIO1

Table 22-8 IOC1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO1
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.5 IOC2 Register (Offset = 108h) [Reset = 00000000h]

IOC2 is shown in Table 22-9.

Return to the Summary Table.

Configuration of DIO2

Table 22-9 IOC2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12SLEWREDR/W0hSlew rate configuration
  • 0h = Normal slew rate
  • 1h = Reduced slew rate
11-10IOCURRR/W0hOutput current configuration. Writing value 0x3 defaults to 2mA current setting.
  • 0h = 2mA
  • 1h = 4mA
  • 2h = 8mA
9-8IOSTRR/W0hDrive strength configuration
  • 0h = Automatic drive strength adjustment
  • 1h = Minimum drive stregnth
  • 2h = Medium drive strength
  • 3h = Maximum drive strength
7-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO2
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.6 IOC3 Register (Offset = 10Ch) [Reset = 00000000h]

IOC3 is shown in Table 22-10.

Return to the Summary Table.

Configuration of DIO3

Table 22-10 IOC3 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12SLEWREDR/W0hSlew rate configuration
  • 0h = Normal slew rate
  • 1h = Reduced slew rate
11-10IOCURRR/W0hOutput current configuration. Writing value 0x3 defaults to 2mA current setting.
  • 0h = 2mA
  • 1h = 4mA
  • 2h = 8mA
9-8IOSTRR/W0hDrive strength configuration
  • 0h = Automatic drive strength adjustment
  • 1h = Minimum drive stregnth
  • 2h = Medium drive strength
  • 3h = Maximum drive strength
7-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO3
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.7 IOC4 Register (Offset = 110h) [Reset = 00000000h]

IOC4 is shown in Table 22-11.

Return to the Summary Table.

Configuration of DIO4

Table 22-11 IOC4 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO4
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.8 IOC5 Register (Offset = 114h) [Reset = 00000000h]

IOC5 is shown in Table 22-12.

Return to the Summary Table.

Configuration of DIO5

Table 22-12 IOC5 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO5
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.9 IOC6 Register (Offset = 118h) [Reset = 00000000h]

IOC6 is shown in Table 22-13.

Return to the Summary Table.

Configuration of DIO6

Table 22-13 IOC6 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO6
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.10 IOC7 Register (Offset = 11Ch) [Reset = 00000000h]

IOC7 is shown in Table 22-14.

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Configuration of DIO7

Table 22-14 IOC7 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO7
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.11 IOC8 Register (Offset = 120h) [Reset = 00000000h]

IOC8 is shown in Table 22-15.

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Configuration of DIO8

Table 22-15 IOC8 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO8
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.12 IOC9 Register (Offset = 124h) [Reset = 00000000h]

IOC9 is shown in Table 22-16.

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Configuration of DIO9

Table 22-16 IOC9 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W2hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12SLEWREDR/W0hSlew rate configuration
  • 0h = Normal slew rate
  • 1h = Reduced slew rate
11-10IOCURRR/W0hOutput current configuration. Writing value 0x3 defaults to 2mA current setting.
  • 0h = 2mA
  • 1h = 4mA
  • 2h = 8mA
9-8IOSTRR/W0hDrive strength configuration
  • 0h = Automatic drive strength adjustment
  • 1h = Minimum drive stregnth
  • 2h = Medium drive strength
  • 3h = Maximum drive strength
7-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO9
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.13 IOC10 Register (Offset = 128h) [Reset = 00000000h]

IOC10 is shown in Table 22-17.

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Configuration of DIO10

Table 22-17 IOC10 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W1hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12SLEWREDR/W0hSlew rate configuration
  • 0h = Normal slew rate
  • 1h = Reduced slew rate
11-10IOCURRR/W0hOutput current configuration. Writing value 0x3 defaults to 2mA current setting.
  • 0h = 2mA
  • 1h = 4mA
  • 2h = 8mA
9-8IOSTRR/W0hDrive strength configuration
  • 0h = Automatic drive strength adjustment
  • 1h = Minimum drive stregnth
  • 2h = Medium drive strength
  • 3h = Maximum drive strength
7-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO10
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.14 IOC11 Register (Offset = 12Ch) [Reset = 00000000h]

IOC11 is shown in Table 22-18.

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Configuration of DIO11

Table 22-18 IOC11 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO11
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.15 IOC12 Register (Offset = 130h) [Reset = 00000000h]

IOC12 is shown in Table 22-19.

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Configuration of DIO12

Table 22-19 IOC12 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO12
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.16 IOC13 Register (Offset = 134h) [Reset = 00000000h]

IOC13 is shown in Table 22-20.

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Configuration of DIO13

Table 22-20 IOC13 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO13
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.17 IOC14 Register (Offset = 138h) [Reset = 00000000h]

IOC14 is shown in Table 22-21.

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Configuration of DIO14

Table 22-21 IOC14 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO14
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.18 IOC15 Register (Offset = 13Ch) [Reset = 00000000h]

IOC15 is shown in Table 22-22.

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Configuration of DIO15

Table 22-22 IOC15 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO15
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.19 IOC16 Register (Offset = 140h) [Reset = 00000000h]

IOC16 is shown in Table 22-23.

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Configuration of DIO16

Table 22-23 IOC16 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO16
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.20 IOC17 Register (Offset = 144h) [Reset = 00000000h]

IOC17 is shown in Table 22-24.

Return to the Summary Table.

Configuration of DIO17

Table 22-24 IOC17 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12SLEWREDR/W0hSlew rate configuration
  • 0h = Normal slew rate
  • 1h = Reduced slew rate
11-10IOCURRR/W0hOutput current configuration. Writing value 0x3 defaults to 2mA current setting.
  • 0h = 2mA
  • 1h = 4mA
  • 2h = 8mA
9-8IOSTRR/W0hDrive strength configuration
  • 0h = Automatic drive strength adjustment
  • 1h = Minimum drive stregnth
  • 2h = Medium drive strength
  • 3h = Maximum drive strength
7-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO17
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.21 IOC18 Register (Offset = 148h) [Reset = 00000000h]

IOC18 is shown in Table 22-25.

Return to the Summary Table.

Configuration of DIO18

Table 22-25 IOC18 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12SLEWREDR/W0hSlew rate configuration
  • 0h = Normal slew rate
  • 1h = Reduced slew rate
11-10IOCURRR/W0hOutput current configuration. Writing value 0x3 defaults to 2mA current setting.
  • 0h = 2mA
  • 1h = 4mA
  • 2h = 8mA
9-8IOSTRR/W0hDrive strength configuration
  • 0h = Automatic drive strength adjustment
  • 1h = Minimum drive stregnth
  • 2h = Medium drive strength
  • 3h = Maximum drive strength
7-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO18
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.22 IOC19 Register (Offset = 14Ch) [Reset = 00000000h]

IOC19 is shown in Table 22-26.

Return to the Summary Table.

Configuration of DIO19

Table 22-26 IOC19 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO19
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.23 IOC20 Register (Offset = 150h) [Reset = 00000000h]

IOC20 is shown in Table 22-27.

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Configuration of DIO20

Table 22-27 IOC20 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO20
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.24 IOC21 Register (Offset = 154h) [Reset = 00000000h]

IOC21 is shown in Table 22-28.

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Configuration of DIO21

Table 22-28 IOC21 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO21
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.25 IOC22 Register (Offset = 158h) [Reset = 00000000h]

IOC22 is shown in Table 22-29.

Return to the Summary Table.

Configuration of DIO22

Table 22-29 IOC22 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO22
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.26 IOC23 Register (Offset = 15Ch) [Reset = 00000000h]

IOC23 is shown in Table 22-30.

Return to the Summary Table.

Configuration of DIO23

Table 22-30 IOC23 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO23
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.27 IOC24 Register (Offset = 160h) [Reset = 00000000h]

IOC24 is shown in Table 22-31.

Return to the Summary Table.

Configuration of DIO24

Table 22-31 IOC24 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO24
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.28 IOC25 Register (Offset = 164h) [Reset = 00000000h]

IOC25 is shown in Table 22-32.

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Configuration of DIO25

Table 22-32 IOC25 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO25
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.29 IOC26 Register (Offset = 168h) [Reset = 00000000h]

IOC26 is shown in Table 22-33.

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Configuration of DIO26

Table 22-33 IOC26 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO26
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.30 IOC27 Register (Offset = 16Ch) [Reset = 00000000h]

IOC27 is shown in Table 22-34.

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Configuration of DIO27

Table 22-34 IOC27 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO27
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.31 IOC28 Register (Offset = 170h) [Reset = 00000000h]

IOC28 is shown in Table 22-35.

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Configuration of DIO28

Table 22-35 IOC28 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO28
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.32 IOC29 Register (Offset = 174h) [Reset = 00000000h]

IOC29 is shown in Table 22-36.

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Configuration of DIO29

Table 22-36 IOC29 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO29
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.33 IOC30 Register (Offset = 178h) [Reset = 00000000h]

IOC30 is shown in Table 22-37.

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Configuration of DIO30

Table 22-37 IOC30 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30HYSTENR/W0hThis field controls input hysteresis
  • 0h = Input hysteresis disabled
  • 1h = Input hysteresis enabled
29INPENR/W0hThis field controls the input capability of DIO
  • 0h = Input disabled
  • 1h = Input enabled
28-27RESERVEDR0hReserved
26-24IOMODER/W0hIO Mode. Setting this to value 0x6 or 0x7 will default to normal IO behavior.
  • 0h = Normal IO
  • 1h = Inverted IO
  • 2h = Open Drain, normal IO
  • 3h = Open Drain, inverted IO
  • 4h = Open Source, normal IO
  • 5h = Open Source, inverted IO
23-22RESERVEDR0hReserved
21-20WUCFGSDR/W0hWakeup configuration from shutdown
  • 0h = Wakeup disabled
  • 1h = Wakeup disabled
  • 2h = Wakeup triggered when pad level is low
  • 3h = Wakeup triggered when pad level is high
19RESERVEDR0hReserved
18WUENSBR/W0hWakeup enable from standby
  • 0h = Wakeup disabled
  • 1h = Wakeup enabled (effective only if EDGEDET is enabled)
17-16EDGEDETR/W0hEdge detect configuration
  • 0h = No edge detection
  • 1h = Negative edge detection
  • 2h = Positive edge detection
  • 3h = Positive and negative edge detection
15RESERVEDR0hReserved
14-13PULLCTLR/W0hPull control. Setting this to value 0x3 disables pull.
  • 0h = No pull
  • 1h = Pull down enabled
  • 2h = Pull up enabled
12-3RESERVEDR0hReserved
2-0PORTCFGR/W0hSelects usage of DIO30
  • 0h = Base function
  • 1h = Digital peripheral function-1
  • 2h = Digital peripheral function-2
  • 3h = Digital peripheral function-3
  • 4h = Digital peripheral function-4
  • 5h = Digital peripheral function-5
  • 6h = Analog function
  • 7h = Digital Test Bus function

22.9.34 DTBCFG Register (Offset = C00h) [Reset = 00000000h]

DTBCFG is shown in Table 22-38.

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DTB configuration

Table 22-38 DTBCFG Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-28DTB0DIVVALR/W0hThese bits are used to configure the DTB[0] divider value.
  • 0h = Divide by 2
  • 1h = Divide by 4
  • 2h = Divide by 8
  • 3h = Divide by 16
27-24RESERVEDR0hReserved
23DTB0DIVENR/W0hThis bit is used to enable the programmable divider on DTB[0].
  • 0h = Disable
  • 1h = Enable
22-19RESERVEDR0hReserved
18-16PADSELR/W0hSelects which 3 DTB lines out of total 16 are routed to DTB pins 15 to 13.
  • 0h = DTB[15:13] selected
  • 1h = DTB[14:12] selected
  • 2h = DTB[11:9] selected
  • 3h = DTB[8:6] selected
  • 4h = DTB[5:3] selected
  • 5h = DTB[2:0] selected
15-13RESERVEDR0hReserved
12-8ULLSELR/W0hULL DTB Mux selection
  • 0h = SVT IPs
  • 1h = CKMDIG IP
  • 2h = ULL Event IP
  • 3h = PM controller IP
  • 4h = PMUDLC IP
  • 5h = RTC IP
  • 6h = IO controller IP
  • 7h = PMU digital IP
  • 8h = Debug subsystem IP
  • 9h = SYS0 IP
7-5RESERVEDR0hReserved
4-0SVTSELR/W0hSVT DTB Mux selection
  • 0h = Disable
  • 1h = ADC IP
  • 2h = BUS IP
  • 3h = Clock controller IP
  • 4h = CPU subsystem IP
  • 5h = DMA IP
  • 6h = GPIO IP
  • 7h = I2C IP
  • 8h = AES IP
  • 9h = LGPT IP
  • Ah = LRF IP
  • Bh = FLASH(NVM) IP
  • Ch = SPI IP
  • Dh = SRAM IP
  • Eh = SVT Event IP
  • Fh = System timer IP
  • 10h = Instance 0 of UART IP
  • 11h = Instance 1 of UART IP
  • 12h = VIMS IP

22.9.35 DTBOE Register (Offset = C04h) [Reset = 00000000h]

DTBOE is shown in Table 22-39.

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DTB output enable

Table 22-39 DTBOE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15EN15R/W0hEnables DTB output 15
  • 0h = DTB output disabled
  • 1h = DTB output enabled
14EN14R/W0hEnables DTB output 14
  • 0h = DTB output disabled
  • 1h = DTB output enabled
13EN13R/W0hEnables DTB output 13
  • 0h = DTB output disabled
  • 1h = DTB output enabled
12EN12R/W0hEnables DTB output 12
  • 0h = DTB output disabled
  • 1h = DTB output enabled
11EN11R/W0hEnables DTB output 11
  • 0h = DTB output disabled
  • 1h = DTB output enabled
10EN10R/W0hEnables DTB output 10
  • 0h = DTB output disabled
  • 1h = DTB output enabled
9EN9R/W0hEnables DTB output 9
  • 0h = DTB output disabled
  • 1h = DTB output enabled
8EN8R/W0hEnables DTB output 8
  • 0h = DTB output disabled
  • 1h = DTB output enabled
7EN7R/W0hEnables DTB output 7
  • 0h = DTB output disabled
  • 1h = DTB output enabled
6EN6R/W0hEnables DTB output 6
  • 0h = DTB output disabled
  • 1h = DTB output enabled
5EN5R/W0hEnables DTB output 5
  • 0h = DTB output disabled
  • 1h = DTB output enabled
4EN4R/W0hEnables DTB output 4
  • 0h = DTB output disabled
  • 1h = DTB output enabled
3EN3R/W0hEnables DTB output 3
  • 0h = DTB output disabled
  • 1h = DTB output enabled
2EN2R/W0hEnables DTB output 2
  • 0h = DTB output disabled
  • 1h = DTB output enabled
1EN1R/W0hEnables DTB output 1
  • 0h = DTB output disabled
  • 1h = DTB output enabled
0EN0R/W0hEnables DTB output 0
  • 0h = DTB output disabled
  • 1h = DTB output enabled

22.9.36 EVTCFG Register (Offset = C08h) [Reset = 00000000h]

EVTCFG is shown in Table 22-40.

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Event configuration. This register is used to select DIO for IOC to publish event on ULL event fabric. It also contains enable bit that is used to mask the event and event flag bit.

Table 22-40 EVTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8EVTIFGR/W0hEvent flag. It is set when edge is detected on selected DIO.
Note: The edge detector flop is cleared for the selected DIO when EVTIFG is cleared by software.
  • 0h = Clear ULL event
  • 1h = Set ULL event
7EVTENR/W0hEnables IOC to publish event on AON event fabric when EVTIFG is set.
  • 0h = Disable
  • 1h = Enable
6RESERVEDR0hReserved
5-0DIOSELR/W0hThis is used to select DIO for event generation. For example, DIOSEL = 0x0 selects DIO0 and DIOSEL = 0x8 selects DIO8.

22.9.37 TEST Register (Offset = C0Ch) [Reset = 00000000h]

TEST is shown in Table 22-41.

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Test register.

Table 22-41 TEST Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SELR/W0hThis is used to drive SWDIO output data and output enable from debug sub-system onto TBD (TDO) pad.
  • 0h = Output data and output enable managed by IOC
  • 1h = Output data and output enable driven based on debug sub-system inputs

22.9.38 DTBSTAT Register (Offset = C10h) [Reset = 00000000h]

DTBSTAT is shown in Table 22-42.

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DTB status register. This register captures the value of DTBL3 mux layer output.

Table 22-42 DTBSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hThis bit field captures the final 16-bit value of DTB signals provided from IOC to DTB device pins.

22.9.39 DTBMUXCFG0 Register (Offset = C14h) [Reset = 00000000h]

DTBMUXCFG0 is shown in Table 22-43.

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DTB mux configuration 0 register. This register is used to configure DTB level 0 and level 1 mux layers.

Table 22-43 DTBMUXCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-28DTBL1SEL3R/W2hSelect bits for DTBL1 fourth mux
  • 0h = Selects PMCTL DTB[15:12]
  • 1h = Selects CKMD DTB[15:12]
  • 2h = Selects DTB[15:12]
  • 3h = Defaults to selection of DTB[15:12]
27-26RESERVEDR0hReserved
25-24DTBL1SEL2R/W2hSelect bits for DTBL1 third mux
  • 0h = Selects PMCTL DTB[11:8]
  • 1h = Selects CKMD DTB[11:8]
  • 2h = Selects DTB[11:8]
  • 3h = Defaults to selection of DTB[11:8]
23-22RESERVEDR0hReserved
21-20DTBL1SEL1R/W2hSelect bits for DTBL1 second mux
  • 0h = Selects PMCTL DTB[7:4]
  • 1h = Selects CKMD DTB[7:4]
  • 2h = Selects DTB[7:4]
  • 3h = Defaults to selection of DTB[7:4]
19-18RESERVEDR0hReserved
17-16DTBL1SEL0R/W2hSelect bits for DTBL1 first mux
  • 0h = Selects PMCTL DTB[3:0]
  • 1h = Selects CKMD DTB[3:0]
  • 2h = Selects DTB[3:0]
  • 3h = Defaults to selection of DTB[3:0]
15-14RESERVEDR0hReserved
13-12DTBL0SEL3R/W2hSelect bits for DTBL0 fourth mux
  • 0h = Selects PMCTL DTB[15:12]
  • 1h = Selects CKMD DTB[15:12]
  • 2h = Selects DTB[15:12]
  • 3h = Defaults to selection of DTB[15:12]
11-10RESERVEDR0hReserved
9-8DTBL0SEL2R/W2hSelect bits for DTBL0 third mux
  • 0h = Selects PMCTL DTB[11:8]
  • 1h = Selects CKMD DTB[11:8]
  • 2h = Selects DTB[11:8]
  • 3h = Defaults to selection of DTB[11:8]
7-6RESERVEDR0hReserved
5-4DTBL0SEL1R/W2hSelect bits for DTBL0 second mux
  • 0h = Selects PMCTL DTB[7:4]
  • 1h = Selects CKMD DTB[7:4]
  • 2h = Selects DTB[7:4]
  • 3h = Defaults to selection of DTB[7:4]
3-2RESERVEDR0hReserved
1-0DTBL0SEL0R/W2hSelect bits for DTBL0 first mux
  • 0h = Selects PMCTL DTB[3:0]
  • 1h = Selects CKMD DTB[3:0]
  • 2h = Selects DTB[3:0]
  • 3h = Defaults to selection of DTB[3:0]

22.9.40 DTBMUXCFG1 Register (Offset = C18h) [Reset = 00000000h]

DTBMUXCFG1 is shown in Table 22-44.

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DTB mux configuration 1 register. This register is used to configure DTB level 2 and level 3 mux layers.

Table 22-44 DTBMUXCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-28DTBL3SEL3R/W3hSelect bits for DTBL3 fourth mux
  • 0h = Selects DTBL2 first mux output
  • 1h = Selects DTBL2 second mux output
  • 2h = Selects DTBL2 third mux output
  • 3h = Selects DTBL2 fourth mux output
27-26RESERVEDR0hReserved
25-24DTBL3SEL2R/W2hSelect bits for DTBL3 third mux
  • 0h = Selects DTBL2 first mux output
  • 1h = Selects DTBL2 second mux output
  • 2h = Selects DTBL2 third mux output
  • 3h = Selects DTBL2 fourth mux output
23-22RESERVEDR0hReserved
21-20DTBL3SEL1R/W1hSelect bits for DTBL3 second mux
  • 0h = Selects DTBL2 first mux output
  • 1h = Selects DTBL2 second mux output
  • 2h = Selects DTBL2 third mux output
  • 3h = Selects DTBL2 fourth mux output
19-18RESERVEDR0hReserved
17-16DTBL3SEL0R/W0hSelect bits for DTBL3 first mux
  • 0h = Selects DTBL2 first mux output
  • 1h = Selects DTBL2 second mux output
  • 2h = Selects DTBL2 third mux output
  • 3h = Selects DTBL2 fourth mux output
15-14RESERVEDR0hReserved
13-12DTBL2SEL3R/W3hSelect bits for DTBL2 fourth mux
  • 0h = Selects DTBL1 first mux output
  • 1h = Selects DTBL1 second mux output
  • 2h = Selects DTBL1 third mux output
  • 3h = Selects DTBL1 fourth mux output
11-10RESERVEDR0hReserved
9-8DTBL2SEL2R/W2hSelect bits for DTBL2 third mux
  • 0h = Selects DTBL0 first mux output
  • 1h = Selects DTBL0 second mux output
  • 2h = Selects DTBL0 third mux output
  • 3h = Selects DTBL0 fourth mux output
7-6RESERVEDR0hReserved
5-4DTBL2SEL1R/W1hSelect bits for DTBL2 second mux
  • 0h = Selects DTB[3:0]
  • 1h = Selects DTB[7:4]
  • 2h = Selects DTB[11:8]
  • 3h = Selects DTB[15:12]
3-2RESERVEDR0hReserved
1-0DTBL2SEL0R/W0hSelect bits for DTBL2 first mux
  • 0h = Selects DTB[3:0]
  • 1h = Selects DTB[7:4]
  • 2h = Selects DTB[11:8]
  • 3h = Selects DTB[15:12]