LMX1204EVM is a prototype evaluation module and is available in limited quantities.
LMX1204EVM
Evaluation module for LMX1204, an RF buffer, multiplier, and divider with JESD204B/C SYSREF support
LMX1204EVM
Overview
The LMX1204 evaluation module (EVM) is designed to evaluate the performance of the LMX1204, which is a four-output, ultra-low additive-jitter RF buffer, divider, and multiplier. This EVM can buffer RF clocking inputs up to 12.8 GHz, multiply x2, x3, or x4 in the output range of 3.2 GHz to 6.4 GHz, and divide inputs by up to 8. A separate auxiliary clock divider is included for FPGAs and logic clocking, and each output includes a SYSREF complement with picosecond precision and delay tuning capability. Multiple devices can be synchronized for wide clock distribution trees.
Features
- 12.8-GHz buffer, up to 6.4-GHz multiplier and divide by up to 8
- -160-dBc/Hz noise floor at 6 GHz
- Four RF output/SYSREF pairs
- SYSREF Generator with per-output picosecond precision delay tuning capability
- Auxiliary divider for FPGA/Logic with SYSREF
- Supports multiple device synchronization
RF PLLs & synthesizers
Get started
- Order the LMX1204EVM
- Download and install TICSPRO-SW and PLLATINUMSIM-SW
- Read the LMX1204EVM user's guide
- Configure registers on TICSPRO-SW and simulate performance on PLLATINUMSIM-SW
Order & start development
Evaluation board
LMX1204EVM – Evaluation module for LMX1204, an RF buffer, multiplier, and divider with JESD204B/C SYSREF support
In stock
Limit: 3
Technical documentation
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| Type | Title | Date | |
|---|---|---|---|
| * | User guide | LMX1204EVM User's Guide | Jul. 15, 2021 |
| Certificate | LMX1204EVM EU RoHS Declaration of Conformity (DoC) | Aug. 11, 2021 |
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