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LMX2572EVM

6.4-GHz Low Power Wideband RF Synthesizer with Phase Synchronization and JESD204B Support

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LMX2572EVM

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Overview

This Evaluation Module is for the LMX2572, which is a low-power high-performance wideband synthesizer that can generate any frequency from 13 MHz to 6.4 GHz without using an internal doubler. The PLL delivers excellent performance while consuming just 75 mA from a single 3.3-V supply. This device supports JESD204B standard (it can generate or repeat the SYSREF signal) which makes it ideal to clock high speed data converters. By providing a SYNC signal, the user can synchronize the output phase across multiple LMX2572 devices. LMX2572 can also generate a frequency ramp which can be demonstrated in this evaluation module. Furthermore, LMX2572 supports direct digital FSK modulation. The serial interface can be configured as a SPI or I2S interface for this purpose. The kitted Refernce Pro module is used to provide a clean reference clock as well as to program the LMX2572 evaluation module.

Features
  • 13-MHz to 6.4-GHz Output Frequency
  • -106 dBc/Hz Phase Noise at 100 kHz Offset with 6.4 GHz Carrier
  • 75 mA operation current with one direct VCO output
  • Two differential outputs with programmable output power
  • This EVM has the complete circuit for the synthesizer, optimized and tested for performance, and includes a USB programming module
RF PLLs & synthesizers
LMX2572 — 6.4-GHz low-power wideband RF synthesizer
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Get started

  1. Order the LMX2572EVM
  2. Download and install TICSPRO-SW and PLLATINUMSIM-SW
  3. Read the LMX2572EVM user's guide
  4. Configure registers on TICSPRO-SW and simulate performance on PLLATINUMSIM-SW

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Evaluation board

LMX2572EVM — 6.4-GHz Low Power Wideband RF Synthesizer with Phase Synchronization and JESD204B Support

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

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Latest version
Version: 1.7.8.0
Release date: 10 Mar 2025
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Documentation

open-in-new TICS_Pro_Release_Notes.pdf

TICS Pro 1.7.8.0 Release Notes

open-in-new TICS_Pro_Manifest.htm

TICS Pro 1.7.8.0 Software Manifest

Release Infomation

Added

  • LMK5C23208A

Improvements

  • TCP server returns error descriptions
  • TICSPro_TCP.py updated for python ≥ 3.10. Remove type annotations if backward compatibility with older python versions is required.
  • LMK5B/5C:
  • Warn when GPIOx selects REFx monitor, but REFx is not programmed
  • Relative calculation of DPLLx_PH_OFFSET value
  • Added fields and improved frequency planning for 1-PPS outputs
  • PLLx_RDIV_MUX_SEL only sets recommended values when dropdown is changed; no longer changed by DPLL loop filter calculation or TCS file load
  • Advanced Options checkbox added on Getting Started page
  • GPIOx descriptions updated for accuracy
  • LMK5B12212, LMK5C12212A:
  • New step added to Start Page process to reduce current consumption and noise
  • SRAM sequence EEPROM generation sets optimized values from new step in Start Page process
  • LMK5B33414, LMK5C33414A:
  • Simplified programming sequence by combining writes for the output divider synchronization sequence generator

Bug Fixes

  • LMK5B12212, LMK5C12212A:
  • Some controls which were not register-backed have been updated to be register-backed.
  • LMK5B33414, LMK5C33414A:
  • Fixed "Set SYNC Enable" buttons on "SYNC/SYSREF/1-PPS" page

Known Issues

  • LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
  • LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
  • Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
  • User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
TI's Standard Terms and Conditions for Evaluation Items apply.

Technical documentation

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Type Title Date
* EVM User's guide LMX2572EVM Evaluation Instructions (Rev. B) 19 Jul 2019
Data sheet LMX2572 6.4-GHz Low power wideband RF synthesizer with phase synchronization and JESD204B support datasheet (Rev. B) PDF | HTML 29 Jan 2019
Certificate LMX2572EVM EU Declaration of Conformity (DoC) 02 Jan 2019

Related design resources

Hardware development

EVALUATION BOARD
XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules

Software development

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TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

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