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TDA4VM-Q1

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SoC mit Dual-Arm®-Cortex®-A72, 8 TOPS von KI, C7xDSP und GPU für visuelle Wahrnehmung und Analyti

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TDA4VM-Q1

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Produktdetails

CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 6 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, 1 EDP, 2 DPI Protocols Ethernet PCIe 4 PCIe Gen 3 switch Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 6 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, 1 EDP, 2 DPI Protocols Ethernet PCIe 4 PCIe Gen 3 switch Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
FCBGA (ALF) 827 576 mm² 24 x 24

Processor cores:

  • C7x floating point, vector DSP, up to 1.0GHz, 80 GFLOPS, 256 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Six Arm Cortex-R5F MCUs at up to 1.0GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four Arm Cortex-R5F MCUs in general compute partition
  • Two C66x floating point DSP, up to 1.35GHz, 40GFLOPS, 160GOPS
  • 3D GPU PowerVR Rogue 8XE GE8430, up to 750MHz, 96GFLOPS, 6Gpix/sec
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • 32-bit data bus with inline ECC
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SC-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Safety-related certifications
      • ISO 26262 certification up to ASIL-D by TÜV SÜD planned
      • IEC 61508 certification up to SIL-3 by TÜV SÜD planned
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • All ports support 2.5Gb SGMII
    • All ports support 1Gb SGMII/RGMII
    • All ports support 100Mb RMII
    • Any two ports support QSGMII (using 4 internal ports per QSGMII)
  • Up to four PCI-Express (PCIe) Gen3 controllers
    • Up to two lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Two USB 3.0 dual-role device (DRD) subsystem
    • Two enhanced SuperSpeed Gen1 Ports
    • Each port supports Type-C switching
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    Automotive interfaces:

  • Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Two CSI2.0 4L RX plus One CSI2.0 4L TX
    • 2.5Gbps RX throughput per lane (20Gbps total)

    Display subsystem:

  • One eDP/DP interface with Multi-Display Support (MST)
    • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
  • One DSI TX (up to 2.5K)
  • Up to two DPI

    Audio interfaces:

  • Twelve Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
  • Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
  • Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI and one QSPI flash interfaces
    • or one HyperBus™ and one QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • C7x floating point, vector DSP, up to 1.0GHz, 80 GFLOPS, 256 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Six Arm Cortex-R5F MCUs at up to 1.0GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four Arm Cortex-R5F MCUs in general compute partition
  • Two C66x floating point DSP, up to 1.35GHz, 40GFLOPS, 160GOPS
  • 3D GPU PowerVR Rogue 8XE GE8430, up to 750MHz, 96GFLOPS, 6Gpix/sec
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • 32-bit data bus with inline ECC
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SC-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Safety-related certifications
      • ISO 26262 certification up to ASIL-D by TÜV SÜD planned
      • IEC 61508 certification up to SIL-3 by TÜV SÜD planned
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • All ports support 2.5Gb SGMII
    • All ports support 1Gb SGMII/RGMII
    • All ports support 100Mb RMII
    • Any two ports support QSGMII (using 4 internal ports per QSGMII)
  • Up to four PCI-Express (PCIe) Gen3 controllers
    • Up to two lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Two USB 3.0 dual-role device (DRD) subsystem
    • Two enhanced SuperSpeed Gen1 Ports
    • Each port supports Type-C switching
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    Automotive interfaces:

  • Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Two CSI2.0 4L RX plus One CSI2.0 4L TX
    • 2.5Gbps RX throughput per lane (20Gbps total)

    Display subsystem:

  • One eDP/DP interface with Multi-Display Support (MST)
    • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
  • One DSI TX (up to 2.5K)
  • Up to two DPI

    Audio interfaces:

  • Twelve Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
  • Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
  • Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI and one QSPI flash interfaces
    • or one HyperBus™ and one QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The TDA4VM processor family targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in a functional safety compliant targeted architecture make the TDA4VM devices a great fit for several industrial applications, such as: Robotics, Machine Vision, Radar, and so on. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated “8XE GE8430” GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VM processor family targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in a functional safety compliant targeted architecture make the TDA4VM devices a great fit for several industrial applications, such as: Robotics, Machine Vision, Radar, and so on. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated “8XE GE8430” GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet TDA4VM Processors datasheet (Rev. K) PDF | HTML 22 Apr 2024
* Errata J721E DRA829/TDA4VM Processors Silicon Revision 2.0/1.1/1.0 (Rev. F) PDF | HTML 26 Feb 2025
* User guide J721E DRA829/TDA4VM Processors Silicon Revision 2.0, 1.1 Technical Reference Manual (Rev. D) PDF | HTML 16 Jan 2025
Application note Boot Flow Options on TDA4 Devices PDF | HTML 05 Jan 2026
Functional safety information J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 01 Okt 2025
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 25 Sep 2025
Functional safety information J721E, J721S2, J7200, J722S, J742S2, J784S4 MCAL TÜV SÜD Functional Safety Certificate (Rev. A) 25 Sep 2025
Application brief Ethernet Firmware Debug Guide PDF | HTML 29 Aug 2025
Functional safety information DRA829/TDA4VM TÜV SÜD Functional Safety Certificate - Automotive - PG2.0 (Rev. A) 28 Aug 2025
Functional safety information DRA829/TDA4VM TÜV SÜD Functional Safety Report - Automotive - PG2.0 (Rev. A) 28 Aug 2025
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17 Jun 2025
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26 Feb 2025
Application note Surround View System ECU PDF | HTML 25 Feb 2025
Application note MCAN Debug Guide PDF | HTML 18 Feb 2025
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 Aug 2024
Application brief The Importance of Third-Party Partner Networks When Solving Key Robotic System Design Challenges PDF | HTML 03 Jul 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 Jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 Jun 2024
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14 Mai 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 Apr 2024
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 Nov 2023
More literature Jacinto 7 EVM Quick Start Guide for TDA4VM and DRA829V Processors (Rev. A) PDF | HTML 09 Aug 2023
Application note Understanding TDA4VM or DRA829 Memory for Optimal Performance PDF | HTML 14 Jun 2023
User guide C6000-to-C7000 Migration User's Guide (Rev. E) PDF | HTML 29 Mär 2023
White paper Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13 Mär 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 Jan 2023
Application note TI Deep Learning Library Upgrade Solution PDF | HTML 21 Dez 2022
Functional safety information Jacinto Functional Safety Enablers (Rev. A) PDF | HTML 12 Dez 2022
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 15 Aug 2022
Certificate J721E SDL TUV Certification 08 Aug 2022
Application note Proof of Concept Enablement for Jacinto TDA4VM OpenVx Host on R5F MCU2_0 PDF | HTML 25 Jul 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 Apr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 Apr 2022
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 29 Mär 2022
User guide TPS65941213-Q1 and LP876411B4-Q1 PMIC User Guide for J721E, PDN-1A PDF | HTML 02 Feb 2022
User guide TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for J721E, PDN-0B (Rev. B) PDF | HTML 31 Jan 2022
Technical article How to simplify your embedded edge AI application development PDF | HTML 28 Jan 2022
Application note Jacinto7 HS Device Development PDF | HTML 13 Jan 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 Jan 2022
More literature Jacinto™ 7 automotive processors 14 Dez 2021
Application note Jacinto 7 Thermal Management Guide - Software Strategies PDF | HTML 10 Dez 2021
Application note Jacinto7 HS Device Flashing Solution PDF | HTML 09 Dez 2021
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 Okt 2021
Application note Performance and power benchmarking with TDA4 Edge AI processors PDF | HTML 01 Sep 2021
Application note TISCI Server Integration in Vector AUTOSAR PDF | HTML 16 Jul 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 Jul 2021
Application note Jacinto 7 Camera Capture and Imaging Subsystem PDF | HTML 07 Jul 2021
Application note J721E DDR Firewall Example PDF | HTML 01 Jul 2021
Application note Hardware Accelerated Structure From Motion on TDA4VM PDF | HTML 23 Apr 2021
Application note Efficient Visual Localization on TDA4VM (Rev. A) PDF | HTML 19 Apr 2021
Functional safety information Build safer, efficient, intelligent and autonomous robots 04 Mär 2021
Application note TDA4VMid VPAC ISP Tuning Overview (Rev. A) PDF | HTML 14 Jan 2021
White paper Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren 04 Jan 2021
White paper Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™ 22 Okt 2020
Application note OSPI Tuning Procedure PDF | HTML 08 Jul 2020
Technical article Making ADAS technology more accessible in vehicles PDF | HTML 07 Jan 2020
White paper A 360-degree view of surround-view and automated parking systems 10 Dez 2019
User guide VCOP Kernel-C to C7000 Migration Tool User's Guide (Rev. C) PDF | HTML 11 Aug 2019

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-J721E — Linux SDK for DRA829 & TDA4VM Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for TDA4VM and DRA829 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive (...)

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PROCESSOR-SDK-LINUX-RT-J721E — Linux-RT SDK for DRA829 & TDA4VM Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for TDA4VM and DRA829 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-QNX-J721E — QNX SDK for DRA829 & TDA4VM Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for TDA4VM and DRA829 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-J721E — RTOS SDK for DRA829 & TDA4VM Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for TDA4VM and DRA829 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive (...)

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Anwendungssoftware und Frameworks

EB-3P-TRESOS — Elektrobit EB tresos Classic AUTOSAR-Software

Mit jahrzehntelanger Erfahrung auf dem Gebiet der Basissoftware trägt Elektrobit mit seiner EB tresos Produktlinie und den maßgeschneiderten Classic AUTOSAR-Lösungen dazu bei, die spezifischen Anforderungen jedes Automobilherstellers zu erfüllen und modernste Software zu liefern. Elektrobit bietet (...)
Von: Elektrobit
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Anwendungssoftware und Frameworks

MOMENTA-3P-DL-ALGORITHMS — Momenta-Deep-Learning-Algorithmen für ADAS-Forward-Kameraanwendungen auf TDA4x Prozessoren

Momenta’s deep learning based algorithms for ADAS applications make full use of the DSP cores and accelerators on TDA4x for neural network processing. Designed to achieve market leading computational and power efficiency, Momenta’s algorithms offer an array of pre- and post-imaging (...)
Von: Momenta
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Anwendungssoftware und Frameworks

PAI-3P-PHANTOMVISION — Phantom-KI-Bildverarbeitungssoftware auf Jacinto-Prozessoren für ADAS-Automobilanwendungen

PhantomVision™ is a scalable, flexible and reliable deep learning based computer vision solution that provides a comprehensive suite of Euro NCAP compliant ADAS features. It is a visual perception engine that enables a single or multiple cameras to autonomously recognize road objects and (...)
Von: Phantom AI
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Anwendungssoftware und Frameworks

SV-3P-MULTIVISION — MultiVision – STRADVISION Software für die Fahrzeugwahrnehmung

MultiVision verwendet eine Kombination aus Front-, Rückfahr-, Seiten- und Rundumsicht- (Fischaugen)-Kameras, um eine umfassende Objekterkennung rund um das Fahrzeug sowohl auf öffentlichen Straßen als auch auf Parkplätzen zu ermöglichen. MultiVision unterstützt ADAS- und autonomes Fahren mit L2+ (...)
Von: Stradvision
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Anwendungssoftware und Frameworks

SV-3P-SURROUNDVISION — SurroundVision – STRADVISION Software für die Fahrzeugwahrnehmung

SurroundVision erkennt eine Vielzahl von Objekten in der Umgebung des Fahrzeugs, einschließlich Fahrzeugen, Fußgängern, Parklücken und Bordsteinen, aus den Bildern der Surround-View-Kamera als Eingabe. Mit seinen hochpräzisen Wahrnehmungsfähigkeiten ermöglicht es den Anwendern, (...)
Von: Stradvision
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Treiber oder Bibliothek

WIND-3P-VXWORKS-LINUX-OS — Wind-River-Prozessoren VxWorks und Linux-Betriebssysteme

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
Von: Wind River Systems
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Firmware

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM Firmware

Das SecIC-HSM wurde entwickelt, um die für MCU-/SoC-Chips erforderlichen Cybersicherheitsanforderungen zu erfüllen. Die HSM-Firmware kann in Bereichen wie Automobil, alternative Energieerzeugung, Photovoltaik, Robotik, Gesundheitswesen und Luftfahrt eingesetzt werden. Zu den bereitgestellten (...)
Von: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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Firmware

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC-Algorithmus-Firmware

Die Sicherheitslösungen von Uni-Sentry verwenden PQC-Algorithmen, die Entschlüsselungsbedrohungen durch Quantencomputer gegenüber herkömmlichen kryptografischen Algorithmen abwehren können. Die PQC-Firmware ist gemeinsam mit dem Hardware-Sicherheitsmodul (HSM) optimiert, sodass (...)
Von: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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IDE, Konfiguration, Compiler oder Debugger

C7000-CGT — C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

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C7000-SAFETI-CQKIT-RV — C7000 safety compiler qualification kit (leverages compiler release validations)

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development tool ecosystem. It is an integrated development environment (IDE) for TI's microcontrollers, processors, wireless connectivity devices and radar sensors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize (...)

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IDE, Konfiguration, Compiler oder Debugger

DDR-CONFIG-J721E — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE, Konfiguration, Compiler oder Debugger

EDGE-AI-STUDIO — Edge AI Studio

Edge AI Studio is part of the CCStudio™ development tool ecosystem.  Edge AI Studio is a collection of graphical and command line tools designed to accelerate edge AI development on TI processors, microcontrollers, connectivity devices and radar sensors.  It supports both AI-accelerated (...)

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IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Betriebssystem (BS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
Von: Green Hills Software
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Betriebssystem (BS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

Das QNX Neutrino® Realtime Operating System (RTOS) ist ein voll ausgestattetes und robustes RTOS, das die nächste Generation von Produkten für eingebettete Systeme in den Bereichen Automobilindustrie, Medizintechnik, Transport, Militär und Industrie ermöglicht. Das Mikrokernel-Design und die (...)
Von: QNX Software Systems
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Betriebssystem (BS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS Vorzertifiziertes Sicherheits-RTOS

SAFERTOS® ist ein einzigartiges Echtzeitbetriebssystem für Embedded-Prozessoren. Er ist vom TÜV SÜD nach den Normen IEC 61508 SIL3 und ISO 26262 ASILD vorzertifiziert. SAFERTOS® wurde vom Expertenteam von WHIS speziell auf Sicherheit ausgelegt und wird weltweit in sicherheitskritischen Anwendungen (...)
Von: WITTENSTEIN High Integrity Systems
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Support-Software

EXLFR-3P-ESYNC-OTA — Excelfore esync OTA Over-the-Air Updates für softwaredefinierte Fahrzeuge

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
eSync (...)
Von: ExcelFore
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Support-Software

EXLFR-3P-TSN — ExelFore's time sensitive network (TSN) automotive paths for safety-critical communications

Softwaredefinierte Fahrzeuge (Software Defined Vehicles, SDV) benötigen Hochleistungsnetzwerke, IP-Adressierung und Sicherheit, die mit Ethernet, aber nicht mit CAN verfügbar sind. Anwendungen in der Automobilindustrie erfordern außerdem garantierte Latenzen, Bandbreite und Redundanz für (...)
Von: ExcelFore
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Support-Software

VCTR-3P-MICROSAR — Vector MICROSAR AUTOSAR-Software für Mikrocontroller und Hochleistungscomputer (HPCs)

Die MICROSAR- und DaVinci-Produktfamilien vereinfachen die Steuergeräte-Entwicklung mit ausgefeilter Embedded-Software und leistungsstarken Entwicklungswerkzeugen für Mikrocontroller und HPCs. Mit fortschrittlicher Infrastruktursoftware schaffen Sie eine optimale Basis für Ihre Steuergeräte und (...)
Von: Vector Informatik GmbH
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Simulationsmodell

DRA829 and TDA4VM BSDL File

SPRM751.ZIP (14 KB) - BSDL Model
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Simulationsmodell

DRA829 and TDA4VM IBIS File

SPRM752.ZIP (1983 KB) - IBIS Model
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Simulationsmodell

DRA829 and TDA4VM Thermal Model

SPRM753.ZIP (1 KB) - Thermal Model
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCBGA (ALF) 827 Ultra Librarian
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