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AM3358-EP

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Sitara-Prozessor: Arm Cortex-A8, 3D, PRU-ICSS, HiRel, CAN

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AM3358-EP

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CPU 1 Arm Cortex-A8 Frequency (MHz) 800 Graphics acceleration 1 3D Display type 1 LCD Protocols Ethernet, ICSS, Profibus, Profinet Features General purpose Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 800 Graphics acceleration 1 3D Display type 1 LCD Protocols Ethernet, ICSS, Profibus, Profinet Features General purpose Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 105
NFBGA (GCZ) 324 225 mm² 15 x 15
  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch
  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet AM3358-EP Sitara™ Processor datasheet (Rev. B) PDF | HTML 18 Apr 2019
* Errata AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 03 Jan 2017
* User guide AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 14 Feb 2023
* VID AM3358-EP VID V6215602 21 Jun 2016
* Radiation & reliability report AM3358BGCZA80EP Reliability Report 17 Dez 2015
Application note Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 24 Nov 2025
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26 Feb 2025
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 31 Jul 2023
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24 Mai 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Design guide Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A) PDF | HTML 09 Nov 2021
Application note Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 07 Mai 2021
More literature From Start to Finish: A Product Development Roadmap for Sitara™ Processors 16 Dez 2020
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 28 Jul 2020
Application note AM335x Schematic Checklist (Rev. A) PDF | HTML 19 Dez 2019
Application note Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 13 Sep 2019
Product overview Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 30 Jul 2019
White paper Power optimization techniques for energy-efficient systems (Rev. A) 28 Jun 2019
Application note AM335x Hardware Design Guide PDF | HTML 03 Mai 2019
User guide Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 11 Apr 2019
Application note Common EOS pitfalls in board design 13 Feb 2019
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 10 Jan 2019
Application note PRU Read Latencies (Rev. A) 21 Dez 2018
White paper Ensuring real-time predictability (Rev. B) 04 Dez 2018
Application note PRU-ICSS EtherCAT Slave Troubleshooting Guide 07 Nov 2018
Application note PRU-ICSS / PRU_ICSSG Migration Guide 05 Nov 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
Application note Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 28 Mär 2018
User guide Powering the AM335x With the TPS650250 (Rev. B) 14 Mär 2018
White paper Data concentrators: The core of energy and data management (Rev. A) 21 Feb 2018
White paper POWERLINK on TI Sitara Processors (Rev. A) 10 Jan 2018
Product overview TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 19 Dez 2017
User guide TPS65910Ax User's Guide for AM335x Processors (Rev. F) 08 Dez 2017
Application note AM335x Reliability Considerations in PLC Applications (Rev. A) 27 Apr 2017
White paper Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 11 Aug 2016
White paper Building automation for enhanced energy and operational efficiency (Rev. A) 26 Okt 2015
White paper Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 03 Mär 2015
User guide G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 13 Nov 2014
User guide Powering the AM335x with the TPS65217x . (Rev. I) 06 Sep 2014
White paper Mainline Linux™ ensures stability and innovation 27 Mär 2014
White paper Linaro Speeds Development in TI Linux SDKs 27 Aug 2013
White paper The Yocto Project:Changing the way embedded Linux software solutions are develop 14 Mär 2013
White paper Smart thermostats are a cool addition to the connected home 27 Sep 2012

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Evaluierungsplatine

ADVAN-3P-SITARA-SOMS — Advantech Sitara-SOMs und SBCs

Advantech offers Sitara™ based embedded core computing solutions including computer-on-modules, single-board-computers and box computers. Their compact, low-power-consumption, and cost-effective Arm®-based platform solutions are designed to deliver easier system integration, better (...)
Von: Advantech
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BYTES-3P-SITARASOMS — Bytes at Work Sitara-SOMs

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


Von: bytes at work AG
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Evaluierungsplatine

COMPU-3P-SITARASOMS — Compulab Sitara-SOMs

CompuLab is a leading manufacturer of computer-on-module boards and miniature PC systems. CompuLab's products excel with an advanced set of features, outstanding level of integration, high reliability and affordable prices. Annual manufacturing rate of over 100,000 boards and systems positions (...)
Von: CompuLab
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Evaluierungsplatine

CRLNK-3P-SOMS — Critical Link system on modules for TI ARM-based Processors

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

Von: Critical Link LLC
Partner-Website besuchen
Evaluierungsplatine

FORLX-3P-SITARA-SOMS — Forlinx Sitara-SOMs

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
Von: Forlinx Embedded Tech. Co., Ltd
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Evaluierungsplatine

MYIR-3P-SITARASOMS — MYIR Sitara-SOMs

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
Von: MYIR Tech Limited
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Evaluierungsplatine

OCTVO-3P-AM335X — System-in-Package auf Basis von Octavo Systems AM335x

Octavo Systems ist führend in der Bereitstellung von System-in-Package (SiP)-basierten Lösungen für Innovatoren auf der ganzen Welt. Die SiP-Bausteinfamilie OSD335x bietet die schnellste und kostengünstigste Möglichkeit, hochleistungsfähige Embedded-Systeme auf Basis des Sitara™ AM335x Arm® (...)

Von: Octavo Systems
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Evaluierungsplatine

PHYTC-3P-PHYBOARD-AM335X — PHYTEC® phyBOARD®-AM335x Entwicklungskit für AM335x Arm®-basierte Sitara™ -Prozessoren

Das phyBOARD®-AM335x verfügt über ein phyCORE-AM335x System-on-Module (SOM), das auf dem Sitara™-Programm von TI basiert; AM335x, das direkt auf eine Trägerplatine gelötet wird. Dieser „Direct Solder Connect“ (DSC) der SOM-zu-Carrier-Platine reduziert die Systemkosten durch den Wegfall von (...)

Von: PHYTEC
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Evaluierungsplatine

PHYTC-3P-PHYCORE-AM335X — PHYTEC phyCORE-AM335x-System auf Modul

Das SOM phyCORE®-AM335x unterstützt die Prozessorfamilie Sitara™ AM335x von Texas Instruments. Es zeichnet sich durch hohe Verarbeitungsleistung, geringen Stromverbrauch und einen hochintegrierten Peripheriesatz aus, der mit modernster Grafikverarbeitung und Unterstützung von Echtzeitprotokollen (...)

Von: PHYTEC
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Evaluierungsplatine

TQ-3P-SITARASOMS — Sitara-SOMs der TQ-Gruppe

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
Von: TQ-Group
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Evaluierungsplatine

VANWS-3P-VGATEWAY — vGATEWAY reference design from Vanteon Wireless Solutions based on AM335x

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

Von: Vanteon Wireless Solutions
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Evaluierungsplatine

VAR-3P-SITARASOMS — Variscite Sitara-SOMs

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
Von: Variscite
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Tochterkarte

PRUCAPE — TI PRU-Cape

The TI PRU Cape is a BeagleBone Black add-on board that allows users get to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and AM437x family of devices.  The PRU core is (...)

Nicht verfügbar auf TI.com
Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Der XDS200 ist ein Debug-Tastkopf (Emulator) zum Debugging von Embedded-Bausteinen von TI. Für die meisten Bausteine wird die Verwendung der neueren, kostengünstigeren XDS110 (www.ti.com/tool/TMDSEMU110-U) empfohlen. Der XDS200 unterstützt eine große Zahl von Standards (IEEE1149.1, IEEE1149.7, SWD) (...)

Nicht verfügbar auf TI.com
Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

Nicht verfügbar auf TI.com
Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

Nicht verfügbar auf TI.com
Debug-Tastkopf

LB-3P-TRACE32-ARM — Debug- und Trace-System Lauterbach TRACE32® für Arm®-basierte Mikrocontroller und Prozessoren

Die TRACE32®-Tools von Lauterbach sind eine Suite hochmoderner Hardware- und Softwarekomponenten, mit denen Entwickler alle Arten von Arm®-basierten Mikrocontrollern und Prozessoren analysieren, optimieren und zertifizieren können. Die weltweit anerkannten Debugging- und Trace-Lösungen für (...)

Von: Lauterbach GmbH
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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-AM335X — Prozessor-SDK für AM335x Sitara-Prozessoren für Linux und TI-RTOS-Support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
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Software-Entwicklungskit (SDK)

TIBLUETOOTHSTACK-SDK — Dual-Mode Bluetooth®-Stack von TI

Der Dual-Mode-Bluetooth-Stack von TI ermöglicht Bluetooth + Bluetooth Low Energy und besteht aus Single-Mode- und Dual-Mode-Angeboten, welche die Bluetooth 4.0/4.1/4.2-Spezifikation implementieren. Der Bluetooth-Stack ist vollständig für Bluetooth Special Interest Group (SIG) qualifiziert, (...)
Benutzerhandbuch: PDF
Benutzerhandbuch: PDF | HTML
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Treiber oder Bibliothek

PRU-ICSS-INDUSTRIAL-SW — PRU-ICSS-Industriesoftware für Sitara™-Prozessoren

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)
Benutzerhandbuch: PDF
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Treiber oder Bibliothek

TI-15.4-STACK-GATEWAY-LINUX-SDK — TI 15.4-Stack Gateway Linux-Software Development Kit

The TI-15.4-Stack-Gateway-Linux Software Development Kit (SDK) provides a Linux software middleware for the TI 15.4-Stack companion solution. It includes a full Linux user-space software that runs on top of the TI Processor SDK for AM335x platform, which interfaces with the co-processor embedded (...)
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Treiber oder Bibliothek

WIND-3P-VXWORKS-LINUX-OS — Wind-River-Prozessoren VxWorks und Linux-Betriebssysteme

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
Von: Wind River Systems
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Treiber oder Bibliothek

WIT-3P-SITARABSP — Witekio Sitara Android- und Windows-Betriebssysteme

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
Von: Witekio
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Betriebssystem (BS)

MG-3P-NUCLEUS-RTOS — Mentor Grafik Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
Von: Mentor Graphics Corporation
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Betriebssystem (BS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

Das QNX Neutrino® Realtime Operating System (RTOS) ist ein voll ausgestattetes und robustes RTOS, das die nächste Generation von Produkten für eingebettete Systeme in den Bereichen Automobilindustrie, Medizintechnik, Transport, Militär und Industrie ermöglicht. Das Mikrokernel-Design und die (...)
Von: QNX
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Software-Programmiertool

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

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Software-Programmiertool

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is part of TI's extensive CCStudio™ development ecosystem and is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces and can be run on (...)

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Support-Software

AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III

The Sercos III Slave Communiction Stack allows to implement the Real-time Ethernet protocol Sercos III for any kind of slave devices. The source code includes SCP (Sercos Communication Profile) and GDP (General Device Profile). In addition, the stack already includes many optional function classes (...)
Von: AUTOMATA
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Simulationsmodell

AM335x Thermal Model

SPRM824.ZIP (10 KB) - Thermal Model
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Simulationsmodell

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS Model
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Simulationsmodell

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL Model
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Simulationsmodell

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL Model
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Simulationsmodell

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS Model
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Simulationsmodell

AM335x ZCZ Rev. 2.0 BSDL Model (Rev. A)

SPRM549A.ZIP (8 KB) - BSDL Model
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Simulationsmodell

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL Model
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Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
Benutzerhandbuch: PDF
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Berechnungstool

POWEREST — Tool zur Schätzung des Stromverbrauchs (Power Estimation Tool, PET)

Das Tool zur Schätzung des Stromverbrauchs (Power Estimation Tool, PET) bietet Benutzern die Möglichkeit, Einblicke in den Stromverbrauch ausgewählter TI-Prozessoren zu erhalten. Das Tool bietet dem Benutzer die Möglichkeit, mehrere Anwendungsszenarien auszuwählen und ein besseres Verständnis des (...)
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Berechnungstool

SITARA-DDR-CONFIG-TOOL — Sitara External Memory Interface (EMIF)-Tool

Das Sitara™ EMIF-Tool ist ein Softwaretool, das eine Schnittstelle zur Konfiguration der TI-Prozessoren für den Zugriff auf die externen DDR-Speicherbausteine bereitstellt. Das Tool optimiert auch die Delay Locked Loop (DLL)-Einstellungen, um Versatz beim Platinenlayout zu kompensieren. Die (...)
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Berechnungstool

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF Tool Spreadsheet

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

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Referenzdesigns

TIDEP0043 — Referenzdesign für Acontis EtherCAT Master Stack

The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performance TI Sitara MPUs,  it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT (...)
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
NFBGA (GCZ) 324 Ultra Librarian
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