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AMIC110

AKTIV

Sitara-Prozessor: Arm Cortex-A8, über 10 Ethernet-Protokolle

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AMIC110

AKTIV
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Produktdetails

CPU 1 Arm Cortex-A8 Frequency (MHz) 300 Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit Features Networking Rating Catalog Power supply solution TPS650250, TPS65216 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 300 Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit Features Networking Rating Catalog Power supply solution TPS650250, TPS65216 Operating temperature range (°C) -40 to 105
NFBGA (ZCZ) 324 225 mm² (15 mm × 15 mm)
  • Up to 300-MHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock (1))
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX](1), Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Package:
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

(1)The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.
  • Up to 300-MHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock (1))
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX](1), Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Package:
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

(1)The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt AMIC110 Sitara™ SoC datasheet (Rev. D) PDF | HTML 12.12.2019
* Errata AMIC110 Sitara SoC Silicon Errata (Rev. 2.1) 03.01.2017
Whitepaper PROFINET on TI’s Sitara™ processors (Rev. E) 13.04.2026
Anwendungshinweis Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 03.09.2025
Technischer Artikel How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory PDF | HTML 24.08.2020
Whitepaper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 28.07.2020
Whitepaper EtherCAT® on Sitara™ Processors (Rev. I) 28.07.2020
E-book Ein Techniker-Leitfaden für Industrieroboter-Designs Download English Version 25.03.2020
Benutzerhandbuch AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 13.12.2019
Anwendungshinweis AM335x EMIF Tools 20.09.2019
Benutzerhandbuch Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 PDF | HTML 11.04.2019
Whitepaper Ensuring real-time predictability (Rev. B) 04.12.2018
Anwendungshinweis PRU-ICSS EtherCAT Slave Troubleshooting Guide 07.11.2018
Whitepaper An inside look at industrial Ethernet communication protocols (Rev. B) 01.08.2018
Benutzerhandbuch Powering the AM335x With the TPS650250 (Rev. B) 14.03.2018
Technischer Artikel Delivering power to the industrial market with Ethernet PDF | HTML 08.03.2018
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Technischer Artikel Reducing factory downtime with predictive maintenance for industrial Ethernet PDF | HTML 07.09.2017
Whitepaper Connected sensors in industrial automation (Rev. B) 22.06.2017
Technischer Artikel Making industrial communication easy with AMIC110 SoCs PDF | HTML 06.06.2017
Technischer Artikel How to select the right industrial Ethernet standard: PROFIBUS PDF | HTML 27.09.2016
Technischer Artikel Start designing your next Sitara™ processor solution! PDF | HTML 28.07.2016
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Design und Entwicklung

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Verfügbare Lösungen für die Stromversorgung für den AMIC110 finden. TI bietet Stromversorgungslösungen für Ein-Chip-Systeme (SoCs), Prozessoren, Mikrocontroller, Sensoren und feldprogrammierbare Gate-Arrays (FPGAs) von TI und von Fremdherstellern an.

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TMDSEMU560V2STM-U — XDS560™-Software v2 – System-Trace-USB-Debug-Sonde

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-AMIC110 — Prozessor-SDK für AMIC110 Sitara-Prozessoren – TI-RTOS-Support

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit.  Alle Versionen des Prozessor-SDK lassen sich (...)

Unterstützte Produkte und Hardware
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-AM335X — TI-RTOS Processor SDK for AM335x and AMIC110 devices (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Unterstützte Produkte und Hardware
IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

Unterstützte Produkte und Hardware
IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

Unterstützte Produkte und Hardware
Onlineschulungen

BOOTL-3P-TRAINING — Schulung zur Embedded-Softwareentwicklung für Arm-basierte Prozessoren von TI

Von: Bootlin
Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-ETHERCAT-SLAVE — PRU-ICSS software for EtherCAT slave

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-ETHERNETIP-ADAPTER — PRU-ICSS software for EtherNetIP adapter

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-HSR-PRP-DAN — PRU-ICSS software for HSR/PRP

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-PROFIBUS-SLAVE — PRU-ICSS software for PROFIBUS slave

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-PROFINET-SLAVE — PRU-ICSS software for Profinet slave

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Software-Programmiertool

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

Das Sitara™ EMIF-Tool ist ein Softwaretool, das eine Schnittstelle zur Konfiguration der TI-Prozessoren für den Zugriff auf die externen DDR-Speicherbausteine bereitstellt. Das Tool optimiert auch die Delay Locked Loop (DLL)-Einstellungen, um Versatz beim Platinenlayout zu kompensieren. Die (...)

Unterstützte Produkte und Hardware
Software-Programmiertool

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash ist Teil des umfassenden CCStudio™-Entwicklungsökosystem von TI und ein Softwaretool zur Programmierung des integrierten Flash-Speichers von TI-Mikrocontrollern und drahtlosen Kommunikationsbausteinen sowie des integrierten Flash-Speichers für TI-Prozessoren. UniFlash bietet sowohl (...)

Unterstützte Produkte und Hardware
Simulationsmodell

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Simulationsmodell

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL-Modell
Unterstützte Produkte und Hardware
Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
Unterstützte Produkte und Hardware
Berechnungstool

POWEREST — Tool zur Schätzung des Stromverbrauchs (Power Estimation Tool, PET)

Das Tool zur Schätzung des Stromverbrauchs (Power Estimation Tool, PET) bietet Benutzern die Möglichkeit, Einblicke in den Stromverbrauch ausgewählter TI-Prozessoren zu erhalten. Das Tool bietet dem Benutzer die Möglichkeit, mehrere Anwendungsszenarien auszuwählen und ein besseres Verständnis des (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDA-00299 — Referenzdesign für EtherCAT® Slave- und Multiprotokoll-Industrial-Ethernet

Dieses Referenzdesign implementiert einen kostenoptimierten EtherCAT-Slave (zwei Ports) mit hoher EMV-Störfestigkeit und einer SPI-Schnittstelle zum Anwendungsprozessor. Das Hardwaredesign ermöglicht die Unterstützung von industriellen Multiprotokoll-Ethernet-und -Feldbussen unter Verwendung des (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDEP-0105 — Referenzdesign für DDR-losen EtherCAT®-Slave auf AMIC110

EtherCAT® (Ethernet for Control Automation Technology) wächst kontinuierlich und etabliert sich als dominantes industrielles Ethernet-Netzwerk. Das EtherCAT-Referenzdesign ohne DDR dienst als Referenz für eine völlig neue und kostengünstige, EtherCAT-Slave-Implementierung ohne DDR auf dem AMIC110, (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDEP0002 — Entwicklungsplattform: PROFIBUS-Kommunikation

Targeted for PROFIBUS slave communications, this development platform allows designers to implement PROFIBUS communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDEP0003 — Entwicklungsplattform: Ethernet/IP-Kommunikation

Targeted for Ethernet/IP secondary communications, this development platform allows you to implement Ethernet/IP communication standards in a broad range of industrial automation equipment. It enables low footprint designs in applications such as industrial automation, factory automation or (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDEP0008 — Entwicklungsplattform: PROFINET-Kommunikation

Targeted for PROFINET secondary communications, this reference design helps you implement PROFINET communications standards in a broad range of industrial automation equipment. It enables low-footprint designs in applications such as industrial automation, factory automation or (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDEP0029 — Zertifiziertes Profinet IRT V2.3-Gerät mit 1-GHz-ARM-Anwendungsprozessor

This reference design integrates industrial Ethernet Phys, Profinet IRT switch, Profinet IRT stack and application examples in one package. Profinet is the leading industrial Ethernet standard used by many industrial segments and end-equipment which require real-time deterministic exchange of IO (...)

Unterstützte Produkte und Hardware
Referenzdesign

TIDEP0049 — „Fast Startup“-Funktion von Industrial Ethernet für AM335x

This reference design is an integrated multi-protocol industrial Ethernet communication on Sitara processors. Fast start-up occurs after device power-up has been defined by various industrial Ethernet standards. This reference design describes a system-level approach to support fast startup (...)

Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
NFBGA (ZCZ) 324 Ultra Librarian
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