SPRUIM2 User guide

Table 5-1014 lists the memory-mapped registers for the PLL0_CFG. All register offset addresses not listed in Table 5-1014 should be considered as reserved locations and the register contents should not be modified.

Table 5-1013 PLL0_CFG Instances

Instance	Base Address
PLL0_CFG	0068 0000h

Table 5-1014 PLL0_CFG Registers

Offset	Acronym	Register Name	PLL0_CFG Physical Address
0h	PLL0_PID	Peripheral Identification Register	0068 0000h
8h	PLL0_CFG	PLL0 Configuration	0068 0008h
10h	PLL0_LOCKKEY0	PLL0 Lock Key 0 Register	0068 0010h
14h	PLL0_LOCKKEY1	PLL0 Lock Key 1 Register	0068 0014h
20h	PLL0_CTRL	PLL0 Control	0068 0020h
24h	PLL0_STAT	PLL0 Status	0068 0024h
30h	PLL0_FREQ_CTRL0	PLL0 Frequency Control 0 Register	0068 0030h
34h	PLL0_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 0034h
38h	PLL0_DIV_CTRL	PLL0 Output Clock Divider Register	0068 0038h
40h	PLL0_SS_CTRL	PLL0 Spread Spectrum Modulator Control Register	0068 0040h
44h	PLL0_SS_SPREAD	PLL0 Spread Spectrum Modulator Frequency Control Register	0068 0044h
60h	PLL0_CAL_CTRL	PLL0 Calibration Control Register	0068 0060h
64h	PLL0_CAL_STAT	PLL0 Calibration Status Register	0068 0064h
80h	PLL0_HSDIV_CTRL0	PLL0 High Speed Divider Control 0 Register	0068 0080h
84h	PLL0_HSDIV_CTRL1	PLL0 High Speed Divider Control 1 Register	0068 0084h
88h	PLL0_HSDIV_CTRL2	PLL0 High Speed Divider Control 2 Register	0068 0088h
8Ch	PLL0_HSDIV_CTRL3	PLL0 High Speed Divider Control 3 Register	0068 008Ch
90h	PLL0_HSDIV_CTRL4	PLL0 High Speed Divider Control 4 Register	0068 0090h
94h	PLL0_HSDIV_CTRL5	PLL0 High Speed Divider Control 5 Register	0068 0094h
98h	PLL0_HSDIV_CTRL6	PLL0 High Speed Divider Control 6 Register	0068 0098h
9Ch	PLL0_HSDIV_CTRL7	PLL0 High Speed Divider Control 7 Register	0068 009Ch
A0h	PLL0_HSDIV_CTRL8	PLL0 High Speed Divider Control 8 Register	0068 00A0h
A4h	PLL0_HSDIV_CTRL9	PLL0 High Speed Divider Control 9 Register	0068 00A4h
1000h	PLL1_PID	Peripheral Identification Register	0068 1000h
1008h	PLL1_CFG	PLL1 Configuration	0068 1008h
1010h	PLL1_LOCKKEY0	PLL1 Lock Key 0 Register	0068 1010h
1014h	PLL1_LOCKKEY1	PLL1 Lock Key 1 Register	0068 1014h
1020h	PLL1_CTRL	PLL1 Control	0068 1020h
1024h	PLL1_STAT	PLL1 Status	0068 1024h
1030h	PLL1_FREQ_CTRL0	PLL1 Frequency Control 0 Register	0068 1030h
1034h	PLL1_FREQ_CTRL1	PLL1 Frequency Control 1 Register	0068 1034h
1038h	PLL1_DIV_CTRL	PLL1 Output Clock Divider Register	0068 1038h
1040h	PLL1_SS_CTRL	PLL1 Spread Spectrum Modulator Control Register	0068 1040h
1044h	PLL1_SS_SPREAD	PLL1 Spread Spectrum Modulator Frequency Control Register	0068 1044h
1060h	PLL1_CAL_CTRL	PLL1 Calibration Control Register	0068 1060h
1064h	PLL1_CAL_STAT	PLL1 Calibration Status Register	0068 1064h
1080h	PLL1_HSDIV_CTRL0	PLL1 High Speed Divider Control 0 Register	0068 1080h
1084h	PLL1_HSDIV_CTRL1	PLL1 High Speed Divider Control 1 Register	0068 1084h
1088h	PLL1_HSDIV_CTRL2	PLL1 High Speed Divider Control 2 Register	0068 1088h
108Ch	PLL1_HSDIV_CTRL3	PLL1 High Speed Divider Control 3 Register	0068 108Ch
1090h	PLL1_HSDIV_CTRL4	PLL1 High Speed Divider Control 4 Register	0068 1090h
1094h	PLL1_HSDIV_CTRL5	PLL1 High Speed Divider Control 5 Register	0068 1094h
1098h	PLL1_HSDIV_CTRL6	PLL1 High Speed Divider Control 6 Register	0068 1098h
2000h	PLL2_PID	Peripheral Identification Register	0068 2000h
2008h	PLL2_CFG	PLL2 Configuration	0068 2008h
2010h	PLL2_LOCKKEY0	PLL2 Lock Key 0 Register	0068 2010h
2014h	PLL2_LOCKKEY1	PLL2 Lock Key 1 Register	0068 2014h
2020h	PLL2_CTRL	PLL2 Control	0068 2020h
2024h	PLL2_STAT	PLL2 Status	0068 2024h
2030h	PLL2_FREQ_CTRL0	PLL2 Frequency Control 0 Register	0068 2030h
2034h	PLL2_FREQ_CTRL1	PLL2 Frequency Control 1 Register	0068 2034h
2038h	PLL2_DIV_CTRL	PLL2 Output Clock Divider Register	0068 2038h
2040h	PLL2_SS_CTRL	PLL2 Spread Spectrum Modulator Control Register	0068 2040h
2044h	PLL2_SS_SPREAD	PLL2 Spread Spectrum Modulator Frequency Control Register	0068 2044h
2060h	PLL2_CAL_CTRL	PLL2 Calibration Control Register	0068 2060h
2064h	PLL2_CAL_STAT	PLL2 Calibration Status Register	0068 2064h
2080h	PLL2_HSDIV_CTRL0	PLL2 High Speed Divider Control 0 Register	0068 2080h
2084h	PLL2_HSDIV_CTRL1	PLL2 High Speed Divider Control 1 Register	0068 2084h
2088h	PLL2_HSDIV_CTRL2	PLL2 High Speed Divider Control 2 Register	0068 2088h
208Ch	PLL2_HSDIV_CTRL3	PLL2 High Speed Divider Control 3 Register	0068 208Ch
2090h	PLL2_HSDIV_CTRL4	PLL2 High Speed Divider Control 4 Register	0068 2090h
2094h	PLL2_HSDIV_CTRL5	PLL2 High Speed Divider Control 5 Register	0068 2094h
2098h	PLL2_HSDIV_CTRL6	PLL2 High Speed Divider Control 6 Register	0068 2098h
209Ch	PLL2_HSDIV_CTRL7	PLL2 High Speed Divider Control 7 Register	0068 209Ch
20A0h	PLL2_HSDIV_CTRL8	PLL2 High Speed Divider Control 8 Register	0068 20A0h
20A4h	PLL2_HSDIV_CTRL9	PLL2 High Speed Divider Control 9 Register	0068 20A4h
8000h	PLL8_PID	Peripheral Identification Register	0068 8000h
8008h	PLL8_CFG	PLL8 Configuration	0068 8008h
8010h	PLL8_LOCKKEY0	PLL8 Lock Key 0 Register	0068 8010h
8014h	PLL8_LOCKKEY1	PLL8 Lock Key 1 Register	0068 8014h
8020h	PLL8_CTRL	PLL8 Control	0068 8020h
8024h	PLL8_STAT	PLL8 Status	0068 8024h
8030h	PLL8_FREQ_CTRL0	PLL8 Frequency Control 0 Register	0068 8030h
8034h	PLL8_FREQ_CTRL1	PLL8 Frequency Control 1 Register	0068 8034h
8038h	PLL8_DIV_CTRL	PLL8 Output Clock Divider Register	0068 8038h
8040h	PLL8_SS_CTRL	PLL8 Spread Spectrum Modulator Control Register	0068 8040h
8044h	PLL8_SS_SPREAD	PLL8 Spread Spectrum Modulator Frequency Control Register	0068 8044h
8060h	PLL8_CAL_CTRL	PLL8 Calibration Control Register	0068 8060h
8064h	PLL8_CAL_STAT	PLL8 Calibration Status Register	0068 8064h
8080h	PLL8_HSDIV_CTRL0	PLL8 High Speed Divider Control 0 Register	0068 8080h
C000h	PLL12_PID	Peripheral Identification Register	0068 C000h
C008h	PLL12_CFG	PLL12 Configuration	0068 C008h
C010h	PLL12_LOCKKEY0	PLL12 Lock Key 0 Register	0068 C010h
C014h	PLL12_LOCKKEY1	PLL12 Lock Key 1 Register	0068 C014h
C020h	PLL12_CTRL	PLL12 Control	0068 C020h
C024h	PLL12_STAT	PLL12 Status	0068 C024h
C030h	PLL12_FREQ_CTRL0	PLL12 Frequency Control 0 Register	0068 C030h
C034h	PLL12_FREQ_CTRL1	PLL12 Frequency Control 1 Register	0068 C034h
C038h	PLL12_DIV_CTRL	PLL12 Output Clock Divider Register	0068 C038h
C040h	PLL12_SS_CTRL	PLL12 Spread Spectrum Modulator Control Register	0068 C040h
C044h	PLL12_SS_SPREAD	PLL12 Spread Spectrum Modulator Frequency Control Register	0068 C044h
C060h	PLL12_CAL_CTRL	PLL12 Calibration Control Register	0068 C060h
C064h	PLL12_CAL_STAT	PLL12 Calibration Status Register	0068 C064h
C080h	PLL12_HSDIV_CTRL0	PLL12 High Speed Divider Control 0 Register	0068 C080h
E000h	PLL14_PID	Peripheral Identification Register	0068 E000h
E008h	PLL14_CFG	PLL14 Configuration	0068 E008h
E010h	PLL14_LOCKKEY0	PLL14 Lock Key 0 Register	0068 E010h
E014h	PLL14_LOCKKEY1	PLL14 Lock Key 1 Register	0068 E014h
E020h	PLL14_CTRL	PLL14 Control	0068 E020h
E024h	PLL14_STAT	PLL14 Status	0068 E024h
E030h	PLL14_FREQ_CTRL0	PLL14 Frequency Control 0 Register	0068 E030h
E034h	PLL14_FREQ_CTRL1	PLL14 Frequency Control 1 Register	0068 E034h
E038h	PLL14_DIV_CTRL	PLL14 Output Clock Divider Register	0068 E038h
E040h	PLL14_SS_CTRL	PLL14 Spread Spectrum Modulator Control Register	0068 E040h
E044h	PLL14_SS_SPREAD	PLL14 Spread Spectrum Modulator Frequency Control Register	0068 E044h
E060h	PLL14_CAL_CTRL	PLL14 Calibration Control Register	0068 E060h
E064h	PLL14_CAL_STAT	PLL14 Calibration Status Register	0068 E064h
E080h	PLL14_HSDIV_CTRL0	PLL14 High Speed Divider Control 0 Register	0068 E080h
E084h	PLL14_HSDIV_CTRL1	PLL14 High Speed Divider Control 1 Register	0068 E084h

4.6.2.1 PLL0_PID Register (Offset = 0h) [reset = 61820000h]

PLL0_PID is shown in Figure 5-507 and described in Table 5-1016.

Return to Summary Table.

Peripheral release details.

Table 5-1015 PLL0_PID Instances

Instance	Physical Address
PLL0_CFG	0068 0000h

Figure 5-507 PLL0_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1016 PLL0_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.2.2 PLL0_CFG Register (Offset = 8h) [reset = 3FF0801h]

PLL0_CFG is shown in Figure 5-508 and described in Table 5-1018.

Return to Summary Table.

Indicates the configuration of this PLL.

Table 5-1017 PLL0_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 0008h

Figure 5-508 PLL0_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-3FFh

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-3FFh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1018 PLL0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	3FFh	High Speed Divider Presence Each bit Indicates the presence of corresponding High Speed divider 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.2.3 PLL0_LOCKKEY0 Register (Offset = 10h) [reset = 0h]

PLL0_LOCKKEY0 is shown in Figure 5-509 and described in Table 5-1020.

Return to Summary Table.

Lower 32-bits of PLL0 register write lock key This register must be written with the designated key value followed by a write to PLL0_KICK1 with its key value before PLL0 registers can be written.

Table 5-1019 PLL0_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 0010h

Figure 5-509 PLL0_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1020 PLL0_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.4 PLL0_LOCKKEY1 Register (Offset = 14h) [reset = 0h]

PLL0_LOCKKEY1 is shown in Figure 5-510 and described in Table 5-1022.

Return to Summary Table.

Upper 32-bits of PLL0 register write lock key This register must be written with the designated key value following a write to PLL0_KICK0 with its key value before PLL0 registers can be written.

Table 5-1021 PLL0_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 0014h

Figure 5-510 PLL0_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1022 PLL0_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

4.6.2.5 PLL0_CTRL Register (Offset = 20h) [reset = 80010011h]

PLL0_CTRL is shown in Figure 5-511 and described in Table 5-1024.

Return to Summary Table.

Controls PLL operation.

Table 5-1023 PLL0_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0020h

Figure 5-511 PLL0_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1024 PLL0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.6 PLL0_STAT Register (Offset = 24h) [reset = X]

PLL0_STAT is shown in Figure 5-512 and described in Table 5-1026.

Return to Summary Table.

Indicates PLL status.

Table 5-1025 PLL0_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 0024h

Figure 5-512 PLL0_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1026 PLL0_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.2.7 PLL0_FREQ_CTRL0 Register (Offset = 30h) [reset = 10h]

PLL0_FREQ_CTRL0 is shown in Figure 5-513 and described in Table 5-1028.

Return to Summary Table.

PLL frequency programming values.

Table 5-1027 PLL0_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 0030h

Figure 5-513 PLL0_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1028 PLL0_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 …. 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.8 PLL0_FREQ_CTRL1 Register (Offset = 34h) [reset = 0h]

PLL0_FREQ_CTRL1 is shown in Figure 5-514 and described in Table 5-1030.

Return to Summary Table.

PLL frequency programming values.

Table 5-1029 PLL0_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 0034h

Figure 5-514 PLL0_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1030 PLL0_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.2.9 PLL0_DIV_CTRL Register (Offset = 38h) [reset = 1020001h]

PLL0_DIV_CTRL is shown in Figure 5-515 and described in Table 5-1032.

Return to Summary Table.

Divider values for the PLL output clocks.

Table 5-1031 PLL0_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0038h

Figure 5-515 PLL0_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1032 PLL0_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3Fh - Divide by 63

4.6.2.10 PLL0_SS_CTRL Register (Offset = 40h) [reset = 80000000h]

PLL0_SS_CTRL is shown in Figure 5-516 and described in Table 5-1034.

Return to Summary Table.

Controls the operation of the spread spectrum modulator.

Table 5-1033 PLL0_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0040h

Figure 5-516 PLL0_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1034 PLL0_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 0h - Use 128 point triangle wave table 1h - Use external wave table

4.6.2.11 PLL0_SS_SPREAD Register (Offset = 44h) [reset = 10001h]

PLL0_SS_SPREAD is shown in Figure 5-517 and described in Table 5-1036.

Return to Summary Table.

Defines the spread spectrum modulation frequency.

Table 5-1035 PLL0_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 0044h

Figure 5-517 PLL0_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1036 PLL0_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% …. 10h - 1.6% 1Fh - 3.1%

4.6.2.12 PLL0_CAL_CTRL Register (Offset = 60h) [reset = 20000h]

PLL0_CAL_CTRL is shown in Figure 5-518 and described in Table 5-1038.

Return to Summary Table.

Controls calibration of the Fractional F PLL.

Table 5-1037 PLL0_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0060h

Figure 5-518 PLL0_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1038 PLL0_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.13 PLL0_CAL_STAT Register (Offset = 64h) [reset = X]

PLL0_CAL_STAT is shown in Figure 5-519 and described in Table 5-1040.

Return to Summary Table.

Indicates Fractional F PLL calibration status.

Table 5-1039 PLL0_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 0064h

Figure 5-519 PLL0_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1040 PLL0_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.2.14 PLL0_HSDIV_CTRL0 Register (Offset = 80h) [reset = 0h]

PLL0_HSDIV_CTRL0 is shown in Figure 5-520 and described in Table 5-1042.

Return to Summary Table.

Controls the PLL0 HSDIVIDER0 features and mode of operation.

Table 5-1041 PLL0_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 0080h

Figure 5-520 PLL0_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1042 PLL0_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.15 PLL0_HSDIV_CTRL1 Register (Offset = 84h) [reset = 0h]

PLL0_HSDIV_CTRL1 is shown in Figure 5-521 and described in Table 5-1044.

Return to Summary Table.

Controls the PLL0 HSDIVIDER1 features and mode of operation.

Table 5-1043 PLL0_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 0084h

Figure 5-521 PLL0_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1044 PLL0_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.16 PLL0_HSDIV_CTRL2 Register (Offset = 88h) [reset = 0h]

PLL0_HSDIV_CTRL2 is shown in Figure 5-522 and described in Table 5-1046.

Return to Summary Table.

Controls the PLL0 HSDIVIDER2 features and mode of operation.

Table 5-1045 PLL0_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 0088h

Figure 5-522 PLL0_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1046 PLL0_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.17 PLL0_HSDIV_CTRL3 Register (Offset = 8Ch) [reset = 0h]

PLL0_HSDIV_CTRL3 is shown in Figure 5-523 and described in Table 5-1048.

Return to Summary Table.

Controls the PLL0 HSDIVIDER3 features and mode of operation.

Table 5-1047 PLL0_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 008Ch

Figure 5-523 PLL0_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1048 PLL0_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.18 PLL0_HSDIV_CTRL4 Register (Offset = 90h) [reset = 0h]

PLL0_HSDIV_CTRL4 is shown in Figure 5-524 and described in Table 5-1050.

Return to Summary Table.

Controls the PLL0 HSDIVIDER4 features and mode of operation.

Table 5-1049 PLL0_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 0090h

Figure 5-524 PLL0_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1050 PLL0_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.19 PLL0_HSDIV_CTRL5 Register (Offset = 94h) [reset = 0h]

PLL0_HSDIV_CTRL5 is shown in Figure 5-525 and described in Table 5-1052.

Return to Summary Table.

Controls the PLL0 HSDIVIDER5 features and mode of operation.

Table 5-1051 PLL0_HSDIV_CTRL5 Instances

Instance	Physical Address
PLL0_CFG	0068 0094h

Figure 5-525 PLL0_HSDIV_CTRL5 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1052 PLL0_HSDIV_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.20 PLL0_HSDIV_CTRL6 Register (Offset = 98h) [reset = 0h]

PLL0_HSDIV_CTRL6 is shown in Figure 5-526 and described in Table 5-1054.

Return to Summary Table.

Controls the PLL0 HSDIVIDER6 features and mode of operation.

Table 5-1053 PLL0_HSDIV_CTRL6 Instances

Instance	Physical Address
PLL0_CFG	0068 0098h

Figure 5-526 PLL0_HSDIV_CTRL6 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1054 PLL0_HSDIV_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.21 PLL0_HSDIV_CTRL7 Register (Offset = 9Ch) [reset = 0h]

PLL0_HSDIV_CTRL7 is shown in Figure 5-527 and described in Table 5-1056.

Return to Summary Table.

Controls the PLL0 HSDIVIDER7 features and mode of operation.

Table 5-1055 PLL0_HSDIV_CTRL7 Instances

Instance	Physical Address
PLL0_CFG	0068 009Ch

Figure 5-527 PLL0_HSDIV_CTRL7 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1056 PLL0_HSDIV_CTRL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.22 PLL0_HSDIV_CTRL8 Register (Offset = A0h) [reset = 0h]

PLL0_HSDIV_CTRL8 is shown in Figure 5-528 and described in Table 5-1058.

Return to Summary Table.

Controls the PLL0 HSDIVIDER8 features and mode of operation.

Table 5-1057 PLL0_HSDIV_CTRL8 Instances

Instance	Physical Address
PLL0_CFG	0068 00A0h

Figure 5-528 PLL0_HSDIV_CTRL8 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1058 PLL0_HSDIV_CTRL8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.23 PLL0_HSDIV_CTRL9 Register (Offset = A4h) [reset = 0h]

PLL0_HSDIV_CTRL9 is shown in Figure 5-529 and described in Table 5-1060.

Return to Summary Table.

Controls the PLL0 HSDIVIDER9 features and mode of operation.

Table 5-1059 PLL0_HSDIV_CTRL9 Instances

Instance	Physical Address
PLL0_CFG	0068 00A4h

Figure 5-529 PLL0_HSDIV_CTRL9 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1060 PLL0_HSDIV_CTRL9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.24 PLL1_PID Register (Offset = 1000h) [reset = 61820000h]

PLL1_PID is shown in Figure 5-530 and described in Table 5-1062.

Return to Summary Table.

Peripheral release details.

Table 5-1061 PLL1_PID Instances

Instance	Physical Address
PLL0_CFG	0068 1000h

Figure 5-530 PLL1_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1062 PLL1_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.2.25 PLL1_CFG Register (Offset = 1008h) [reset = 7F0801h]

PLL1_CFG is shown in Figure 5-531 and described in Table 5-1064.

Return to Summary Table.

Indicates the configuration of this PLL.

Table 5-1063 PLL1_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 1008h

Figure 5-531 PLL1_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-7Fh

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-7Fh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1064 PLL1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	7Fh	High Speed Divider Presence Each bit Indicates the presence of corresponding High Speed divider 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock.
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.2.26 PLL1_LOCKKEY0 Register (Offset = 1010h) [reset = 0h]

PLL1_LOCKKEY0 is shown in Figure 5-532 and described in Table 5-1066.

Return to Summary Table.

Lower 32-bits of PLL1 register write lock key This register must be written with the designated key value followed by a write to PLL1_KICK1 with its key value before PLL1 registers can be written.

Table 5-1065 PLL1_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 1010h

Figure 5-532 PLL1_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1066 PLL1_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.27 PLL1_LOCKKEY1 Register (Offset = 1014h) [reset = 0h]

PLL1_LOCKKEY1 is shown in Figure 5-533 and described in Table 5-1068.

Return to Summary Table.

Upper 32-bits of PLL1 register write lock key This register must be written with the designated key value following a write to PLL1_KICK0 with its key value before PLL1 registers can be written.

Table 5-1067 PLL1_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 1014h

Figure 5-533 PLL1_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1068 PLL1_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers

4.6.2.28 PLL1_CTRL Register (Offset = 1020h) [reset = 80010011h]

PLL1_CTRL is shown in Figure 5-534 and described in Table 5-1070.

Return to Summary Table.

Controls PLL operation.

Table 5-1069 PLL1_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1020h

Figure 5-534 PLL1_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1070 PLL1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.29 PLL1_STAT Register (Offset = 1024h) [reset = X]

PLL1_STAT is shown in Figure 5-535 and described in Table 5-1072.

Return to Summary Table.

Indicates PLL status.

Table 5-1071 PLL1_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 1024h

Figure 5-535 PLL1_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1072 PLL1_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.2.30 PLL1_FREQ_CTRL0 Register (Offset = 1030h) [reset = 10h]

PLL1_FREQ_CTRL0 is shown in Figure 5-536 and described in Table 5-1074.

Return to Summary Table.

PLL frequency programming values.

Table 5-1073 PLL1_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 1030h

Figure 5-536 PLL1_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1074 PLL1_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 …. 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.31 PLL1_FREQ_CTRL1 Register (Offset = 1034h) [reset = 0h]

PLL1_FREQ_CTRL1 is shown in Figure 5-537 and described in Table 5-1076.

Return to Summary Table.

PLL frequency programming values.

Table 5-1075 PLL1_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 1034h

Figure 5-537 PLL1_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1076 PLL1_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.2.32 PLL1_DIV_CTRL Register (Offset = 1038h) [reset = 1020001h]

PLL1_DIV_CTRL is shown in Figure 5-538 and described in Table 5-1078.

Return to Summary Table.

Divider values for the PLL output clocks.

Table 5-1077 PLL1_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1038h

Figure 5-538 PLL1_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1078 PLL1_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 …. 3Fh - Divide by 63

4.6.2.33 PLL1_SS_CTRL Register (Offset = 1040h) [reset = 80000000h]

PLL1_SS_CTRL is shown in Figure 5-539 and described in Table 5-1080.

Return to Summary Table.

Controls the operation of the spread spectrum modulator.

Table 5-1079 PLL1_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1040h

Figure 5-539 PLL1_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1080 PLL1_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 0h - Use 128 point triangle wave table 1h - Use external wave table

4.6.2.34 PLL1_SS_SPREAD Register (Offset = 1044h) [reset = 10001h]

PLL1_SS_SPREAD is shown in Figure 5-540 and described in Table 5-1082.

Return to Summary Table.

Defines the spread spectrum modulation frequency.

Table 5-1081 PLL1_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 1044h

Figure 5-540 PLL1_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1082 PLL1_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% …. 10h - 1.6% 1Fh - 3.1%

4.6.2.35 PLL1_CAL_CTRL Register (Offset = 1060h) [reset = 20000h]

PLL1_CAL_CTRL is shown in Figure 5-541 and described in Table 5-1084.

Return to Summary Table.

Controls calibration of the Fractional F PLL.

Table 5-1083 PLL1_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1060h

Figure 5-541 PLL1_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1084 PLL1_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2*cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.36 PLL1_CAL_STAT Register (Offset = 1064h) [reset = X]

PLL1_CAL_STAT is shown in Figure 5-542 and described in Table 5-1086.

Return to Summary Table.

Indicates Fractional F PLL calibration status.

Table 5-1085 PLL1_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 1064h

Figure 5-542 PLL1_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1086 PLL1_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.2.37 PLL1_HSDIV_CTRL0 Register (Offset = 1080h) [reset = 0h]

PLL1_HSDIV_CTRL0 is shown in Figure 5-543 and described in Table 5-1088.

Return to Summary Table.

Controls the PLL1 HSDIVIDER0 features and mode of operation.

Table 5-1087 PLL1_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 1080h

Figure 5-543 PLL1_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1088 PLL1_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.38 PLL1_HSDIV_CTRL1 Register (Offset = 1084h) [reset = 0h]

PLL1_HSDIV_CTRL1 is shown in Figure 5-544 and described in Table 5-1090.

Return to Summary Table.

Controls the PLL1 HSDIVIDER1 features and mode of operation.

Table 5-1089 PLL1_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 1084h

Figure 5-544 PLL1_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1090 PLL1_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.39 PLL1_HSDIV_CTRL2 Register (Offset = 1088h) [reset = 0h]

PLL1_HSDIV_CTRL2 is shown in Figure 5-545 and described in Table 5-1092.

Return to Summary Table.

Controls the PLL1 HSDIVIDER2 features and mode of operation.

Table 5-1091 PLL1_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 1088h

Figure 5-545 PLL1_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1092 PLL1_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.40 PLL1_HSDIV_CTRL3 Register (Offset = 108Ch) [reset = 0h]

PLL1_HSDIV_CTRL3 is shown in Figure 5-546 and described in Table 5-1094.

Return to Summary Table.

Controls the PLL1 HSDIVIDER3 features and mode of operation.

Table 5-1093 PLL1_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 108Ch

Figure 5-546 PLL1_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1094 PLL1_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.41 PLL1_HSDIV_CTRL4 Register (Offset = 1090h) [reset = 0h]

PLL1_HSDIV_CTRL4 is shown in Figure 5-547 and described in Table 5-1096.

Return to Summary Table.

Controls the PLL1 HSDIVIDER4 features and mode of operation.

Table 5-1095 PLL1_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 1090h

Figure 5-547 PLL1_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1096 PLL1_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.42 PLL1_HSDIV_CTRL5 Register (Offset = 1094h) [reset = 0h]

PLL1_HSDIV_CTRL5 is shown in Figure 5-548 and described in Table 5-1098.

Return to Summary Table.

Controls the PLL1 HSDIVIDER5 features and mode of operation.

Table 5-1097 PLL1_HSDIV_CTRL5 Instances

Instance	Physical Address
PLL0_CFG	0068 1094h

Figure 5-548 PLL1_HSDIV_CTRL5 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1098 PLL1_HSDIV_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.43 PLL1_HSDIV_CTRL6 Register (Offset = 1098h) [reset = 0h]

PLL1_HSDIV_CTRL6 is shown in Figure 5-549 and described in Table 5-1100.

Return to Summary Table.

Controls the PLL1 HSDIVIDER6 features and mode of operation.

Table 5-1099 PLL1_HSDIV_CTRL6 Instances

Instance	Physical Address
PLL0_CFG	0068 1098h

Figure 5-549 PLL1_HSDIV_CTRL6 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1100 PLL1_HSDIV_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.44 PLL2_PID Register (Offset = 2000h) [reset = 61820000h]

PLL2_PID is shown in Figure 5-550 and described in Table 5-1102.

Return to Summary Table.

Peripheral release details.

Table 5-1101 PLL2_PID Instances

Instance	Physical Address
PLL0_CFG	0068 2000h

Figure 5-550 PLL2_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1102 PLL2_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.2.45 PLL2_CFG Register (Offset = 2008h) [reset = 3FF0801h]

PLL2_CFG is shown in Figure 5-551 and described in Table 5-1104.

Return to Summary Table.

Indicates the configuration of this PLL.

Table 5-1103 PLL2_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 2008h

Figure 5-551 PLL2_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-3FFh

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-3FFh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1104 PLL2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	3FFh	High Speed Divider Presence Each bit Indicates the presence of corresponding High Speed divider 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.2.46 PLL2_LOCKKEY0 Register (Offset = 2010h) [reset = 0h]

PLL2_LOCKKEY0 is shown in Figure 5-552 and described in Table 5-1106.

Return to Summary Table.

Lower 32-bits of PLL2 register write lock key This register must be written with the designated key value followed by a write to PLL2_KICK1 with its key value before PLL2 registers can be written.

Table 5-1105 PLL2_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 2010h

Figure 5-552 PLL2_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1106 PLL2_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.47 PLL2_LOCKKEY1 Register (Offset = 2014h) [reset = 0h]

PLL2_LOCKKEY1 is shown in Figure 5-553 and described in Table 5-1108.

Return to Summary Table.

Upper 32-bits of PLL2 register write lock key This register must be written with the designated key value following a write to PLL2_KICK0 with its key value before PLL2 registers can be written.

Table 5-1107 PLL2_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 2014h

Figure 5-553 PLL2_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1108 PLL2_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers

4.6.2.48 PLL2_CTRL Register (Offset = 2020h) [reset = 80010011h]

PLL2_CTRL is shown in Figure 5-554 and described in Table 5-1110.

Return to Summary Table.

Controls PLL operation.

Table 5-1109 PLL2_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2020h

Figure 5-554 PLL2_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1110 PLL2_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.49 PLL2_STAT Register (Offset = 2024h) [reset = X]

PLL2_STAT is shown in Figure 5-555 and described in Table 5-1112.

Return to Summary Table.

Indicates PLL status.

Table 5-1111 PLL2_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 2024h

Figure 5-555 PLL2_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1112 PLL2_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.2.50 PLL2_FREQ_CTRL0 Register (Offset = 2030h) [reset = 10h]

PLL2_FREQ_CTRL0 is shown in Figure 5-556 and described in Table 5-1114.

Return to Summary Table.

PLL frequency programming values.

Table 5-1113 PLL2_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 2030h

Figure 5-556 PLL2_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1114 PLL2_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 …. 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.51 PLL2_FREQ_CTRL1 Register (Offset = 2034h) [reset = 0h]

PLL2_FREQ_CTRL1 is shown in Figure 5-557 and described in Table 5-1116.

Return to Summary Table.

PLL frequency programming values.

Table 5-1115 PLL2_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 2034h

Figure 5-557 PLL2_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1116 PLL2_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.2.52 PLL2_DIV_CTRL Register (Offset = 2038h) [reset = 1020001h]

PLL2_DIV_CTRL is shown in Figure 5-558 and described in Table 5-1118.

Return to Summary Table.

Divider values for the PLL output clocks.

Table 5-1117 PLL2_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2038h

Figure 5-558 PLL2_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1118 PLL2_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3Fh - Divide by 63

4.6.2.53 PLL2_SS_CTRL Register (Offset = 2040h) [reset = 80000000h]

PLL2_SS_CTRL is shown in Figure 5-559 and described in Table 5-1120.

Return to Summary Table.

Controls the operation of the spread spectrum modulator.

Table 5-1119 PLL2_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2040h

Figure 5-559 PLL2_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1120 PLL2_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 0h - Use 128 point triangle wave table 1h - Use external wave table

4.6.2.54 PLL2_SS_SPREAD Register (Offset = 2044h) [reset = 10001h]

PLL2_SS_SPREAD is shown in Figure 5-560 and described in Table 5-1122.

Return to Summary Table.

Defines the spread spectrum modulation frequency.

Table 5-1121 PLL2_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 2044h

Figure 5-560 PLL2_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1122 PLL2_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% …. 10h - 1.6% 1Fh - 3.1%

4.6.2.55 PLL2_CAL_CTRL Register (Offset = 2060h) [reset = 20000h]

PLL2_CAL_CTRL is shown in Figure 5-561 and described in Table 5-1124.

Return to Summary Table.

Controls calibration of the Fractional F PLL.

Table 5-1123 PLL2_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2060h

Figure 5-561 PLL2_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1124 PLL2_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.56 PLL2_CAL_STAT Register (Offset = 2064h) [reset = X]

PLL2_CAL_STAT is shown in Figure 5-562 and described in Table 5-1126.

Return to Summary Table.

Indicates Fractional F PLL calibration status.

Table 5-1125 PLL2_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 2064h

Figure 5-562 PLL2_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1126 PLL2_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.2.57 PLL2_HSDIV_CTRL0 Register (Offset = 2080h) [reset = 0h]

PLL2_HSDIV_CTRL0 is shown in Figure 5-563 and described in Table 5-1128.

Return to Summary Table.

Controls the PLL2 HSDIVIDER0 features and mode of operation.

Table 5-1127 PLL2_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 2080h

Figure 5-563 PLL2_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1128 PLL2_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.58 PLL2_HSDIV_CTRL1 Register (Offset = 2084h) [reset = 0h]

PLL2_HSDIV_CTRL1 is shown in Figure 5-564 and described in Table 5-1130.

Return to Summary Table.

Controls the PLL2 HSDIVIDER1 features and mode of operation.

Table 5-1129 PLL2_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 2084h

Figure 5-564 PLL2_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1130 PLL2_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.59 PLL2_HSDIV_CTRL2 Register (Offset = 2088h) [reset = 0h]

PLL2_HSDIV_CTRL2 is shown in Figure 5-565 and described in Table 5-1132.

Return to Summary Table.

Controls the PLL2 HSDIVIDER2 features and mode of operation.

Table 5-1131 PLL2_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 2088h

Figure 5-565 PLL2_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1132 PLL2_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.60 PLL2_HSDIV_CTRL3 Register (Offset = 208Ch) [reset = 0h]

PLL2_HSDIV_CTRL3 is shown in Figure 5-566 and described in Table 5-1134.

Return to Summary Table.

Controls the PLL2 HSDIVIDER3 features and mode of operation.

Table 5-1133 PLL2_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 208Ch

Figure 5-566 PLL2_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1134 PLL2_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.61 PLL2_HSDIV_CTRL4 Register (Offset = 2090h) [reset = 0h]

PLL2_HSDIV_CTRL4 is shown in Figure 5-567 and described in Table 5-1136.

Return to Summary Table.

Controls the PLL2 HSDIVIDER4 features and mode of operation.

Table 5-1135 PLL2_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 2090h

Figure 5-567 PLL2_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1136 PLL2_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.62 PLL2_HSDIV_CTRL5 Register (Offset = 2094h) [reset = 0h]

PLL2_HSDIV_CTRL5 is shown in Figure 5-568 and described in Table 5-1138.

Return to Summary Table.

Controls the PLL2 HSDIVIDER5 features and mode of operation.

Table 5-1137 PLL2_HSDIV_CTRL5 Instances

Instance	Physical Address
PLL0_CFG	0068 2094h

Figure 5-568 PLL2_HSDIV_CTRL5 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1138 PLL2_HSDIV_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.63 PLL2_HSDIV_CTRL6 Register (Offset = 2098h) [reset = 0h]

PLL2_HSDIV_CTRL6 is shown in Figure 5-569 and described in Table 5-1140.

Return to Summary Table.

Controls the PLL2 HSDIVIDER6 features and mode of operation.

Table 5-1139 PLL2_HSDIV_CTRL6 Instances

Instance	Physical Address
PLL0_CFG	0068 2098h

Figure 5-569 PLL2_HSDIV_CTRL6 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1140 PLL2_HSDIV_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.64 PLL2_HSDIV_CTRL7 Register (Offset = 209Ch) [reset = 0h]

PLL2_HSDIV_CTRL7 is shown in Figure 5-570 and described in Table 5-1142.

Return to Summary Table.

Controls the PLL2 HSDIVIDER7 features and mode of operation.

Table 5-1141 PLL2_HSDIV_CTRL7 Instances

Instance	Physical Address
PLL0_CFG	0068 209Ch

Figure 5-570 PLL2_HSDIV_CTRL7 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1142 PLL2_HSDIV_CTRL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.65 PLL2_HSDIV_CTRL8 Register (Offset = 20A0h) [reset = 0h]

PLL2_HSDIV_CTRL8 is shown in Figure 5-571 and described in Table 5-1144.

Return to Summary Table.

Controls the PLL2 HSDIVIDER8 features and mode of operation.

Table 5-1143 PLL2_HSDIV_CTRL8 Instances

Instance	Physical Address
PLL0_CFG	0068 20A0h

Figure 5-571 PLL2_HSDIV_CTRL8 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1144 PLL2_HSDIV_CTRL8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.66 PLL2_HSDIV_CTRL9 Register (Offset = 20A4h) [reset = 0h]

PLL2_HSDIV_CTRL9 is shown in Figure 5-572 and described in Table 5-1146.

Return to Summary Table.

Controls the PLL2 HSDIVIDER9 features and mode of operation.

Table 5-1145 PLL2_HSDIV_CTRL9 Instances

Instance	Physical Address
PLL0_CFG	0068 20A4h

Figure 5-572 PLL2_HSDIV_CTRL9 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1146 PLL2_HSDIV_CTRL9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.67 PLL8_PID Register (Offset = 8000h) [reset = 61820000h]

PLL8_PID is shown in Figure 5-573 and described in Table 5-1148.

Return to Summary Table.

Peripheral release details.

Table 5-1147 PLL8_PID Instances

Instance	Physical Address
PLL0_CFG	0068 8000h

Figure 5-573 PLL8_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1148 PLL8_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.2.68 PLL8_CFG Register (Offset = 8008h) [reset = 10801h]

PLL8_CFG is shown in Figure 5-574 and described in Table 5-1150.

Return to Summary Table.

Indicates the configuration of this PLL.

Table 5-1149 PLL8_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 8008h

Figure 5-574 PLL8_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-1h

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-1h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1150 PLL8_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	1h	High Speed Divider Presence Each bit Indicates the presence of corresponding High Speed divider 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.2.69 PLL8_LOCKKEY0 Register (Offset = 8010h) [reset = 0h]

PLL8_LOCKKEY0 is shown in Figure 5-575 and described in Table 5-1152.

Return to Summary Table.

Lower 32-bits of PLL8 register write lock key This register must be written with the designated key value followed by a write to PLL8_KICK1 with its key value before PLL8 registers can be written.

Table 5-1151 PLL8_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 8010h

Figure 5-575 PLL8_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1152 PLL8_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.70 PLL8_LOCKKEY1 Register (Offset = 8014h) [reset = 0h]

PLL8_LOCKKEY1 is shown in Figure 5-576 and described in Table 5-1154.

Return to Summary Table.

Upper 32-bits of PLL8 register write lock key This register must be written with the designated key value following a write to PLL8_KICK0 with its key value before PLL8 registers can be written.

Table 5-1153 PLL8_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 8014h

Figure 5-576 PLL8_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1154 PLL8_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition8 registers

4.6.2.71 PLL8_CTRL Register (Offset = 8020h) [reset = 80010011h]

PLL8_CTRL is shown in Figure 5-577 and described in Table 5-1156.

Return to Summary Table.

Controls PLL operation.

Table 5-1155 PLL8_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8020h

Figure 5-577 PLL8_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1156 PLL8_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.72 PLL8_STAT Register (Offset = 8024h) [reset = X]

PLL8_STAT is shown in Figure 5-578 and described in Table 5-1158.

Return to Summary Table.

Indicates PLL status.

Table 5-1157 PLL8_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 8024h

Figure 5-578 PLL8_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1158 PLL8_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.2.73 PLL8_FREQ_CTRL0 Register (Offset = 8030h) [reset = 10h]

PLL8_FREQ_CTRL0 is shown in Figure 5-579 and described in Table 5-1160.

Return to Summary Table.

PLL frequency programming values.

Table 5-1159 PLL8_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 8030h

Figure 5-579 PLL8_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1160 PLL8_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.74 PLL8_FREQ_CTRL1 Register (Offset = 8034h) [reset = 0h]

PLL8_FREQ_CTRL1 is shown in Figure 5-580 and described in Table 5-1162.

Return to Summary Table.

PLL frequency programming values.

Table 5-1161 PLL8_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 8034h

Figure 5-580 PLL8_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1162 PLL8_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.2.75 PLL8_DIV_CTRL Register (Offset = 8038h) [reset = 1020001h]

PLL8_DIV_CTRL is shown in Figure 5-581 and described in Table 5-1164.

Return to Summary Table.

Divider values for the PLL output clocks.

Table 5-1163 PLL8_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8038h

Figure 5-581 PLL8_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1164 PLL8_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3Fh - Divide by 63

4.6.2.76 PLL8_SS_CTRL Register (Offset = 8040h) [reset = 80000000h]

PLL8_SS_CTRL is shown in Figure 5-582 and described in Table 5-1166.

Return to Summary Table.

Controls the operation of the spread spectrum modulator.

Table 5-1165 PLL8_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8040h

Figure 5-582 PLL8_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			HSDIV_CLK_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1166 PLL8_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	HSDIV_CLK_SEL	R/W	0h	Repurposed wave_sel bit to bypass HSDIV for high frequency PLL clock 0h - HSDIV is bypassed. Required setting for PLL FOUTVCO > 1.5 GHz 1h - HSDIV is enabled. PLL FOUTVCO is routed through HSDIV.

4.6.2.77 PLL8_SS_SPREAD Register (Offset = 8044h) [reset = 10001h]

PLL8_SS_SPREAD is shown in Figure 5-583 and described in Table 5-1168.

Return to Summary Table.

Defines the spread spectrum modulation frequency.

Table 5-1167 PLL8_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 8044h

Figure 5-583 PLL8_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1168 PLL8_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% …. 10h - 1.6% 1Fh - 3.1%

4.6.2.78 PLL8_CAL_CTRL Register (Offset = 8060h) [reset = 20000h]

PLL8_CAL_CTRL is shown in Figure 5-584 and described in Table 5-1170.

Return to Summary Table.

Controls calibration of the Fractional F PLL.

Table 5-1169 PLL8_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8060h

Figure 5-584 PLL8_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1170 PLL8_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.79 PLL8_CAL_STAT Register (Offset = 8064h) [reset = X]

PLL8_CAL_STAT is shown in Figure 5-585 and described in Table 5-1172.

Return to Summary Table.

Indicates Fractional F PLL calibration status.

Table 5-1171 PLL8_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 8064h

Figure 5-585 PLL8_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1172 PLL8_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.2.80 PLL8_HSDIV_CTRL0 Register (Offset = 8080h) [reset = 0h]

PLL8_HSDIV_CTRL0 is shown in Figure 5-586 and described in Table 5-1174.

Return to Summary Table.

Controls the PLL8 HSDIVIDER0 features and mode of operation.

Table 5-1173 PLL8_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 8080h

Figure 5-586 PLL8_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1174 PLL8_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.81 PLL12_PID Register (Offset = C000h) [reset = 61820000h]

PLL12_PID is shown in Figure 5-587 and described in Table 5-1176.

Return to Summary Table.

Peripheral release details.

Table 5-1175 PLL12_PID Instances

Instance	Physical Address
PLL0_CFG	0068 C000h

Figure 5-587 PLL12_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1176 PLL12_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.2.82 PLL12_CFG Register (Offset = C008h) [reset = 10801h]

PLL12_CFG is shown in Figure 5-588 and described in Table 5-1178.

Return to Summary Table.

Indicates the configuration of this PLL.

Table 5-1177 PLL12_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 C008h

Figure 5-588 PLL12_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-1h

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-1h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1178 PLL12_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	1h	High Speed Divider Presence Each bit Indicates the presence of corresponding High Speed divider 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.2.83 PLL12_LOCKKEY0 Register (Offset = C010h) [reset = 0h]

PLL12_LOCKKEY0 is shown in Figure 5-589 and described in Table 5-1180.

Return to Summary Table.

Lower 32-bits of PLL12 register write lock key This register must be written with the designated key value followed by a write to PLL12_KICK1 with its key value before PLL12 registers can be written.

Table 5-1179 PLL12_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 C010h

Figure 5-589 PLL12_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1180 PLL12_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.84 PLL12_LOCKKEY1 Register (Offset = C014h) [reset = 0h]

PLL12_LOCKKEY1 is shown in Figure 5-590 and described in Table 5-1182.

Return to Summary Table.

Upper 32-bits of PLL12 register write lock key This register must be written with the designated key value following a write to PLL12_KICK0 with its key value before PLL12 registers can be written.

Table 5-1181 PLL12_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 C014h

Figure 5-590 PLL12_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1182 PLL12_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition12 registers

4.6.2.85 PLL12_CTRL Register (Offset = C020h) [reset = 80010011h]

PLL12_CTRL is shown in Figure 5-591 and described in Table 5-1184.

Return to Summary Table.

Controls PLL operation.

Table 5-1183 PLL12_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C020h

Figure 5-591 PLL12_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1184 PLL12_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.86 PLL12_STAT Register (Offset = C024h) [reset = X]

PLL12_STAT is shown in Figure 5-592 and described in Table 5-1186.

Return to Summary Table.

Indicates PLL status.

Table 5-1185 PLL12_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 C024h

Figure 5-592 PLL12_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1186 PLL12_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.2.87 PLL12_FREQ_CTRL0 Register (Offset = C030h) [reset = 10h]

PLL12_FREQ_CTRL0 is shown in Figure 5-593 and described in Table 5-1188.

Return to Summary Table.

PLL frequency programming values.

Table 5-1187 PLL12_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 C030h

Figure 5-593 PLL12_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1188 PLL12_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.88 PLL12_FREQ_CTRL1 Register (Offset = C034h) [reset = 0h]

PLL12_FREQ_CTRL1 is shown in Figure 5-594 and described in Table 5-1190.

Return to Summary Table.

PLL frequency programming values.

Table 5-1189 PLL12_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 C034h

Figure 5-594 PLL12_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1190 PLL12_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.2.89 PLL12_DIV_CTRL Register (Offset = C038h) [reset = 1020001h]

PLL12_DIV_CTRL is shown in Figure 5-595 and described in Table 5-1192.

Return to Summary Table.

Divider values for the PLL output clocks.

Table 5-1191 PLL12_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C038h

Figure 5-595 PLL12_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1192 PLL12_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3Fh - Divide by 63

4.6.2.90 PLL12_SS_CTRL Register (Offset = C040h) [reset = 80000000h]

PLL12_SS_CTRL is shown in Figure 5-596 and described in Table 5-1194.

Return to Summary Table.

Controls the operation of the spread spectrum modulator.

Table 5-1193 PLL12_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C040h

Figure 5-596 PLL12_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1194 PLL12_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 0h - Use 128 point triangle wave table 1h - Use external wave table

4.6.2.91 PLL12_SS_SPREAD Register (Offset = C044h) [reset = 10001h]

PLL12_SS_SPREAD is shown in Figure 5-597 and described in Table 5-1196.

Return to Summary Table.

Defines the spread spectrum modulation frequency.

Table 5-1195 PLL12_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 C044h

Figure 5-597 PLL12_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1196 PLL12_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% …. 10h - 1.6% 1Fh - 3.1%

4.6.2.92 PLL12_CAL_CTRL Register (Offset = C060h) [reset = 20000h]

PLL12_CAL_CTRL is shown in Figure 5-598 and described in Table 5-1198.

Return to Summary Table.

Controls calibration of the Fractional F PLL.

Table 5-1197 PLL12_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C060h

Figure 5-598 PLL12_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1198 PLL12_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.93 PLL12_CAL_STAT Register (Offset = C064h) [reset = X]

PLL12_CAL_STAT is shown in Figure 5-599 and described in Table 5-1200.

Return to Summary Table.

Indicates Fractional F PLL calibration status.

Table 5-1199 PLL12_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 C064h

Figure 5-599 PLL12_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1200 PLL12_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.2.94 PLL12_HSDIV_CTRL0 Register (Offset = C080h) [reset = 0h]

PLL12_HSDIV_CTRL0 is shown in Figure 5-600 and described in Table 5-1202.

Return to Summary Table.

Controls the PLL12 HSDIVIDER0 features and mode of operation.

Table 5-1201 PLL12_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 C080h

Figure 5-600 PLL12_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1202 PLL12_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.95 PLL14_PID Register (Offset = E000h) [reset = 61820000h]

PLL14_PID is shown in Figure 5-601 and described in Table 5-1204.

Return to Summary Table.

Peripheral release details.

Table 5-1203 PLL14_PID Instances

Instance	Physical Address
PLL0_CFG	0068 E000h

Figure 5-601 PLL14_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1204 PLL14_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.2.96 PLL14_CFG Register (Offset = E008h) [reset = 30801h]

PLL14_CFG is shown in Figure 5-602 and described in Table 5-1206.

Return to Summary Table.

Indicates the configuration of this PLL.

Table 5-1205 PLL14_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 E008h

Figure 5-602 PLL14_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-3h

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-3h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1206 PLL14_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	3h	High Speed Divider Presence Each bit Indicates the presence of corresponding High Speed divider 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.2.97 PLL14_LOCKKEY0 Register (Offset = E010h) [reset = 0h]

PLL14_LOCKKEY0 is shown in Figure 5-603 and described in Table 5-1208.

Return to Summary Table.

Lower 32-bits of PLL14 register write lock key This register must be written with the designated key value followed by a write to PLL14_KICK1 with its key value before PLL14 registers can be written.

Table 5-1207 PLL14_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 E010h

Figure 5-603 PLL14_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1208 PLL14_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition14 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.98 PLL14_LOCKKEY1 Register (Offset = E014h) [reset = 0h]

PLL14_LOCKKEY1 is shown in Figure 5-604 and described in Table 5-1210.

Return to Summary Table.

Upper 32-bits of PLL14 register write lock key This register must be written with the designated key value following a write to PLL14_KICK0 with its key value before PLL14 registers can be written.

Table 5-1209 PLL14_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 E014h

Figure 5-604 PLL14_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1210 PLL14_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition14 registers

4.6.2.99 PLL14_CTRL Register (Offset = E020h) [reset = 80010011h]

PLL14_CTRL is shown in Figure 5-605 and described in Table 5-1212.

Return to Summary Table.

Controls PLL operation.

Table 5-1211 PLL14_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E020h

Figure 5-605 PLL14_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1212 PLL14_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.100 PLL14_STAT Register (Offset = E024h) [reset = X]

PLL14_STAT is shown in Figure 5-606 and described in Table 5-1214.

Return to Summary Table.

Indicates PLL status.

Table 5-1213 PLL14_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 E024h

Figure 5-606 PLL14_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1214 PLL14_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.2.101 PLL14_FREQ_CTRL0 Register (Offset = E030h) [reset = 10h]

PLL14_FREQ_CTRL0 is shown in Figure 5-607 and described in Table 5-1216.

Return to Summary Table.

PLL frequency programming values.

Table 5-1215 PLL14_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 E030h

Figure 5-607 PLL14_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1216 PLL14_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.102 PLL14_FREQ_CTRL1 Register (Offset = E034h) [reset = 0h]

PLL14_FREQ_CTRL1 is shown in Figure 5-608 and described in Table 5-1218.

Return to Summary Table.

PLL frequency programming values.

Table 5-1217 PLL14_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 E034h

Figure 5-608 PLL14_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1218 PLL14_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.2.103 PLL14_DIV_CTRL Register (Offset = E038h) [reset = 1020001h]

PLL14_DIV_CTRL is shown in Figure 5-609 and described in Table 5-1220.

Return to Summary Table.

Divider values for the PLL output clocks.

Table 5-1219 PLL14_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E038h

Figure 5-609 PLL14_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1220 PLL14_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 …. 3Fh - Divide by 63

4.6.2.104 PLL14_SS_CTRL Register (Offset = E040h) [reset = 80000000h]

PLL14_SS_CTRL is shown in Figure 5-610 and described in Table 5-1222.

Return to Summary Table.

Controls the operation of the spread spectrum modulator.

Table 5-1221 PLL14_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E040h

Figure 5-610 PLL14_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1222 PLL14_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 0h - Use 128 point triangle wave table 1h - Use external wave table

4.6.2.105 PLL14_SS_SPREAD Register (Offset = E044h) [reset = 10001h]

PLL14_SS_SPREAD is shown in Figure 5-611 and described in Table 5-1224.

Return to Summary Table.

Defines the spread spectrum modulation frequency.

Table 5-1223 PLL14_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 E044h

Figure 5-611 PLL14_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1224 PLL14_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% 10h - 1.6% 1Fh - 3.1%

4.6.2.106 PLL14_CAL_CTRL Register (Offset = E060h) [reset = 20000h]

PLL14_CAL_CTRL is shown in Figure 5-612 and described in Table 5-1226.

Return to Summary Table.

Controls calibration of the Fractional F PLL.

Table 5-1225 PLL14_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E060h

Figure 5-612 PLL14_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1226 PLL14_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.107 PLL14_CAL_STAT Register (Offset = E064h) [reset = X]

PLL14_CAL_STAT is shown in Figure 5-613 and described in Table 5-1228.

Return to Summary Table.

Indicates Fractional F PLL calibration status.

Table 5-1227 PLL14_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 E064h

Figure 5-613 PLL14_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1228 PLL14_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.2.108 PLL14_HSDIV_CTRL0 Register (Offset = E080h) [reset = 0h]

PLL14_HSDIV_CTRL0 is shown in Figure 5-614 and described in Table 5-1230.

Return to Summary Table.

Controls the PLL14 HSDIVIDER0 features and mode of operation.

Table 5-1229 PLL14_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 E080h

Figure 5-614 PLL14_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1230 PLL14_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.109 PLL14_HSDIV_CTRL1 Register (Offset = E084h) [reset = 0h]

PLL14_HSDIV_CTRL1 is shown in Figure 5-615 and described in Table 5-1232.

Return to Summary Table.

Controls the PLL14 HSDIVIDER1 features and mode of operation.

Table 5-1231 PLL14_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 E084h

Figure 5-615 PLL14_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1232 PLL14_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT enable 0h - Synchronously disable CLKOUT 1h - Synchronously enable CLKOUT
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT divider value (HSDIV1+1) Allowed values are 0-127

5.4.6.2 PLL0_CFG Registers

4.6.2.1 PLL0_PID Register (Offset = 0h) [reset = 61820000h]

4.6.2.2 PLL0_CFG Register (Offset = 8h) [reset = 3FF0801h]

4.6.2.3 PLL0_LOCKKEY0 Register (Offset = 10h) [reset = 0h]

4.6.2.4 PLL0_LOCKKEY1 Register (Offset = 14h) [reset = 0h]

4.6.2.5 PLL0_CTRL Register (Offset = 20h) [reset = 80010011h]

4.6.2.6 PLL0_STAT Register (Offset = 24h) [reset = X]

4.6.2.7 PLL0_FREQ_CTRL0 Register (Offset = 30h) [reset = 10h]

4.6.2.8 PLL0_FREQ_CTRL1 Register (Offset = 34h) [reset = 0h]

4.6.2.9 PLL0_DIV_CTRL Register (Offset = 38h) [reset = 1020001h]

4.6.2.10 PLL0_SS_CTRL Register (Offset = 40h) [reset = 80000000h]

4.6.2.11 PLL0_SS_SPREAD Register (Offset = 44h) [reset = 10001h]

4.6.2.12 PLL0_CAL_CTRL Register (Offset = 60h) [reset = 20000h]

4.6.2.13 PLL0_CAL_STAT Register (Offset = 64h) [reset = X]

4.6.2.14 PLL0_HSDIV_CTRL0 Register (Offset = 80h) [reset = 0h]

4.6.2.15 PLL0_HSDIV_CTRL1 Register (Offset = 84h) [reset = 0h]

4.6.2.16 PLL0_HSDIV_CTRL2 Register (Offset = 88h) [reset = 0h]

4.6.2.17 PLL0_HSDIV_CTRL3 Register (Offset = 8Ch) [reset = 0h]

4.6.2.18 PLL0_HSDIV_CTRL4 Register (Offset = 90h) [reset = 0h]

4.6.2.19 PLL0_HSDIV_CTRL5 Register (Offset = 94h) [reset = 0h]

4.6.2.20 PLL0_HSDIV_CTRL6 Register (Offset = 98h) [reset = 0h]

4.6.2.21 PLL0_HSDIV_CTRL7 Register (Offset = 9Ch) [reset = 0h]

4.6.2.22 PLL0_HSDIV_CTRL8 Register (Offset = A0h) [reset = 0h]

4.6.2.23 PLL0_HSDIV_CTRL9 Register (Offset = A4h) [reset = 0h]

4.6.2.24 PLL1_PID Register (Offset = 1000h) [reset = 61820000h]

4.6.2.25 PLL1_CFG Register (Offset = 1008h) [reset = 7F0801h]

4.6.2.26 PLL1_LOCKKEY0 Register (Offset = 1010h) [reset = 0h]

4.6.2.27 PLL1_LOCKKEY1 Register (Offset = 1014h) [reset = 0h]

4.6.2.28 PLL1_CTRL Register (Offset = 1020h) [reset = 80010011h]

4.6.2.29 PLL1_STAT Register (Offset = 1024h) [reset = X]

4.6.2.30 PLL1_FREQ_CTRL0 Register (Offset = 1030h) [reset = 10h]

4.6.2.31 PLL1_FREQ_CTRL1 Register (Offset = 1034h) [reset = 0h]

4.6.2.32 PLL1_DIV_CTRL Register (Offset = 1038h) [reset = 1020001h]

4.6.2.33 PLL1_SS_CTRL Register (Offset = 1040h) [reset = 80000000h]

4.6.2.34 PLL1_SS_SPREAD Register (Offset = 1044h) [reset = 10001h]

4.6.2.35 PLL1_CAL_CTRL Register (Offset = 1060h) [reset = 20000h]

4.6.2.36 PLL1_CAL_STAT Register (Offset = 1064h) [reset = X]

4.6.2.37 PLL1_HSDIV_CTRL0 Register (Offset = 1080h) [reset = 0h]

4.6.2.38 PLL1_HSDIV_CTRL1 Register (Offset = 1084h) [reset = 0h]

4.6.2.39 PLL1_HSDIV_CTRL2 Register (Offset = 1088h) [reset = 0h]

4.6.2.40 PLL1_HSDIV_CTRL3 Register (Offset = 108Ch) [reset = 0h]

4.6.2.41 PLL1_HSDIV_CTRL4 Register (Offset = 1090h) [reset = 0h]

4.6.2.42 PLL1_HSDIV_CTRL5 Register (Offset = 1094h) [reset = 0h]

4.6.2.43 PLL1_HSDIV_CTRL6 Register (Offset = 1098h) [reset = 0h]

4.6.2.44 PLL2_PID Register (Offset = 2000h) [reset = 61820000h]

4.6.2.45 PLL2_CFG Register (Offset = 2008h) [reset = 3FF0801h]

4.6.2.46 PLL2_LOCKKEY0 Register (Offset = 2010h) [reset = 0h]

4.6.2.47 PLL2_LOCKKEY1 Register (Offset = 2014h) [reset = 0h]

4.6.2.48 PLL2_CTRL Register (Offset = 2020h) [reset = 80010011h]

4.6.2.49 PLL2_STAT Register (Offset = 2024h) [reset = X]

4.6.2.50 PLL2_FREQ_CTRL0 Register (Offset = 2030h) [reset = 10h]

4.6.2.51 PLL2_FREQ_CTRL1 Register (Offset = 2034h) [reset = 0h]

4.6.2.52 PLL2_DIV_CTRL Register (Offset = 2038h) [reset = 1020001h]

4.6.2.53 PLL2_SS_CTRL Register (Offset = 2040h) [reset = 80000000h]

4.6.2.54 PLL2_SS_SPREAD Register (Offset = 2044h) [reset = 10001h]

4.6.2.55 PLL2_CAL_CTRL Register (Offset = 2060h) [reset = 20000h]

4.6.2.56 PLL2_CAL_STAT Register (Offset = 2064h) [reset = X]

4.6.2.57 PLL2_HSDIV_CTRL0 Register (Offset = 2080h) [reset = 0h]

4.6.2.58 PLL2_HSDIV_CTRL1 Register (Offset = 2084h) [reset = 0h]

4.6.2.59 PLL2_HSDIV_CTRL2 Register (Offset = 2088h) [reset = 0h]

4.6.2.60 PLL2_HSDIV_CTRL3 Register (Offset = 208Ch) [reset = 0h]

4.6.2.61 PLL2_HSDIV_CTRL4 Register (Offset = 2090h) [reset = 0h]

4.6.2.62 PLL2_HSDIV_CTRL5 Register (Offset = 2094h) [reset = 0h]

4.6.2.63 PLL2_HSDIV_CTRL6 Register (Offset = 2098h) [reset = 0h]

4.6.2.64 PLL2_HSDIV_CTRL7 Register (Offset = 209Ch) [reset = 0h]

4.6.2.65 PLL2_HSDIV_CTRL8 Register (Offset = 20A0h) [reset = 0h]

4.6.2.66 PLL2_HSDIV_CTRL9 Register (Offset = 20A4h) [reset = 0h]

4.6.2.67 PLL8_PID Register (Offset = 8000h) [reset = 61820000h]

4.6.2.68 PLL8_CFG Register (Offset = 8008h) [reset = 10801h]

4.6.2.69 PLL8_LOCKKEY0 Register (Offset = 8010h) [reset = 0h]

4.6.2.70 PLL8_LOCKKEY1 Register (Offset = 8014h) [reset = 0h]

4.6.2.71 PLL8_CTRL Register (Offset = 8020h) [reset = 80010011h]

4.6.2.72 PLL8_STAT Register (Offset = 8024h) [reset = X]

4.6.2.73 PLL8_FREQ_CTRL0 Register (Offset = 8030h) [reset = 10h]

4.6.2.74 PLL8_FREQ_CTRL1 Register (Offset = 8034h) [reset = 0h]

4.6.2.75 PLL8_DIV_CTRL Register (Offset = 8038h) [reset = 1020001h]

4.6.2.76 PLL8_SS_CTRL Register (Offset = 8040h) [reset = 80000000h]

4.6.2.77 PLL8_SS_SPREAD Register (Offset = 8044h) [reset = 10001h]

4.6.2.78 PLL8_CAL_CTRL Register (Offset = 8060h) [reset = 20000h]

4.6.2.79 PLL8_CAL_STAT Register (Offset = 8064h) [reset = X]