SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
A single instance of an Enhanced Capture event module (ECAP0) is integrated in each device PRU_ICSSG0 and PRU_ICSSG1 subsystem.
For more details on the PRU_ICSSG0 and PRU_ICSSG1 ECAP0 I/O signals available at device level, refer to the PRU_ICSSG Environment.
For PRU_ICSSG0 and PRU_ICSSG1 ECAP0 integration details and functionalities, controlled at PRU_ICSSG top level (functional clock control, etc.), refer to the PRU_ICSSG Integration and the PRU-ICSS Top Level Resources Functional Description.
The PRU_ICSSG0 and PRU_ICSSG1 ECAP0 "SYNC In" hardware event synchronization input and "SYNC Out" hardware synchronization output are implemented in the device PRU_ICSSG0 and PRU_ICSSG1 respectively. However, a software-forced synchronization via bit ECAP_ECCTL2_ECCTL1[24] SWSYNC, can be used as an alternative, provided that ECAP_ECCTL2_ECCTL1[21] SYNCI_EN bit is set to 1h.
For full description of the PRU_ICSSG0, PRU_ICSSG1 and PRU_ICSSG2 ECAP0 modules and functionalities, refer to the Enhanced Capture (eCAP) Module.