SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The CORE block uses two multiplexers to allow software to select one of three source clocks (ICSSGn_CORE_CLK, ICSSGn_ICLK or ICSSGn_IEP_CLK) for the final clock source of the CORE block. The user needs to configure ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN bit and ICSSG_IEPCLK_REG[0] IEP_OCP_CLK_EN bit to 1 if CORE_CLK and IEP_CLK respectively needs to be synchronous to ICLK (250 MHz).