SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 11-671 lists the memory-mapped registers for the PDMA1. All register offset addresses not listed in Table 11-671 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PDMA1_REGS | 00C0 1000h |
Offset | Acronym | Register Name | PDMA1_REGS Physical Address |
---|---|---|---|
0h | PDMA1_ECC_REV | Aggregator revision register | 00C0 1000h |
8h | PDMA1_ECC_VECTOR | ECC vector register | 00C0 1008h |
Ch | PDMA1_ECC_STAT | Misc status register | 00C0 100Ch |
3Ch | PDMA1_ECC_SEC_EOI_REG | SEC EOI register | 00C0 103Ch |
40h | PDMA1_ECC_SEC_STATUS_REG0 | SEC interrupt status register 0 | 00C0 1040h |
80h | PDMA1_ECC_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 00C0 1080h |
C0h | PDMA1_ECC_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 00C0 10C0h |
13Ch | PDMA1_ECC_DED_EOI_REG | DED EOI register | 00C0 113Ch |
140h | PDMA1_ECC_DED_STATUS_REG0 | DED interrupt status register 0 | 00C0 1140h |
180h | PDMA1_ECC_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 00C0 1180h |
1C0h | PDMA1_ECC_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 00C0 11C0h |
200h | PDMA1_ECC_AGGR_ENABLE_SET | AGGR interrupt enable set register | 00C0 1200h |
204h | PDMA1_ECC_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 00C0 1204h |
208h | PDMA1_ECC_AGGR_STATUS_SET | AGGR interrupt status set register | 00C0 1208h |
20Ch | PDMA1_ECC_AGGR_STATUS_CLR | AGGR interrupt status clear register | 00C0 120Ch |
PDMA1_ECC_REV is shown in Figure 11-284 and described in Table 11-673.
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IP revision register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A03201h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A03201h | TI internal data. Identifies revision of peripheral. |
PDMA1_ECC_VECTOR is shown in Figure 11-285 and described in Table 11-675.
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ECC vector register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
PDMA1_ECC_STAT is shown in Figure 11-286 and described in Table 11-677.
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Misc status register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 100Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-4h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 4h | Indicates the number of RAMs serviced by the ECC aggregator |
PDMA1_ECC_SEC_EOI_REG is shown in Figure 11-287 and described in Table 11-679.
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SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 103Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
PDMA1_ECC_SEC_STATUS_REG0 is shown in Figure 11-288 and described in Table 11-681.
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SEC interrupt status register 0.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_PEND | RPCF0_RAMECC_PEND | TPCF1_RAMECC_PEND | TPCF0_RAMECC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf0_ramecc_pend |
PDMA1_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 11-289 and described in Table 11-683.
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SEC interrupt enable set register 0.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_SET | RPCF0_RAMECC_ENABLE_SET | TPCF1_RAMECC_ENABLE_SET | TPCF0_RAMECC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf0_ramecc_pend |
PDMA1_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 11-290 and described in Table 11-685.
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SEC interrupt enable clear register 0.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 10C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_CLR | RPCF0_RAMECC_ENABLE_CLR | TPCF1_RAMECC_ENABLE_CLR | TPCF0_RAMECC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf0_ramecc_pend |
PDMA1_ECC_DED_EOI_REG is shown in Figure 11-291 and described in Table 11-687.
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DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 113Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
PDMA1_ECC_DED_STATUS_REG0 is shown in Figure 11-292 and described in Table 11-689.
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DED interrupt status register 0.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_PEND | RPCF0_RAMECC_PEND | TPCF1_RAMECC_PEND | TPCF0_RAMECC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf0_ramecc_pend |
PDMA1_ECC_DED_ENABLE_SET_REG0 is shown in Figure 11-293 and described in Table 11-691.
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DED interrupt enable set register 0.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_SET | RPCF0_RAMECC_ENABLE_SET | TPCF1_RAMECC_ENABLE_SET | TPCF0_RAMECC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf0_ramecc_pend |
PDMA1_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 11-294 and described in Table 11-693.
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DED interrupt enable clear register 0.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 11C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_CLR | RPCF0_RAMECC_ENABLE_CLR | TPCF1_RAMECC_ENABLE_CLR | TPCF0_RAMECC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf0_ramecc_pend |
PDMA1_ECC_AGGR_ENABLE_SET is shown in Figure 11-295 and described in Table 11-695.
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AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
PDMA1_ECC_AGGR_ENABLE_CLR is shown in Figure 11-296 and described in Table 11-697.
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AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
PDMA1_ECC_AGGR_STATUS_SET is shown in Figure 11-297 and described in Table 11-699.
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AGGR interrupt status set register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 1208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
PDMA1_ECC_AGGR_STATUS_CLR is shown in Figure 11-298 and described in Table 11-701.
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AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
PDMA1_REGS | 00C0 120Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |