SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-1391 lists the memory-mapped registers for the CPSW0_PCSR. All register offset addresses not listed in Table 12-1391 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPSW0_NUSS_PCSR | 0800 0000h |
Offset | Acronym | Register Name | CPSW0_NUSS_PCSR Physical Address |
---|---|---|---|
2100h | CPSW_PCSR_TX_CTL_REG | PCSR Transmit Control Register | 0800 2100h |
2104h | CPSW_PCSR_TX_STATUS_REG | PCSR Transmit Status Register | 0800 2104h |
2108h | CPSW_PCSR_RX_CTL_REG | PCSR Receive Control Register | 0800 2108h |
210Ch | CPSW_PCSR_RX_STATUS_REG | PCSR Receive Status Register | 0800 210Ch |
2110h | CPSW_PCSR_SEED_A_LO_REG | PCSR Seed A Low Register | 0800 2110h |
2114h | CPSW_PCSR_SEED_A_HI_REG | PCSR SEED A High Register | 0800 2114h |
2118h | CPSW_PCSR_SEED_B_LO_REG | PCSR Seed B Low Register | 0800 2118h |
211Ch | CPSW_PCSR_SEED_B_HI_REG | PCSR SEED B High Register | 0800 211Ch |
2120h | CPSW_PCSR_FEC_REG | PCSR FEC Register | 0800 2120h |
2124h | CPSW_PCSR_CTL_REG | PCSR CTL Register | 0800 2124h |
2128h | CPSW_PCSR_FEC_CNT_REG | PCSR FEC Count Register | 0800 2128h |
212Ch | CPSW_PCSR_ERROR_FIFO_REG | PCSR Error FIFO Register | 0800 212Ch |
CPSW_PCSR_TX_CTL_REG is shown in Figure 12-719 and described in Table 12-1393.
Return to Summary Table.
PCSR Transmit Control Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TX_DATAPATH_EN | ||||||
R/W-X | R/W-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_SCR_BPYASS | TX_TEST_EN | TX_TEST_SEL | TX_TEST_DAT_SEL | TX_PRBS31_EN | TX_PRBS9_EN | TX_LOOPBACK_EN | TX_SCR_LOOPBK_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | TX_DATAPATH_EN | R/W | 1h | PCSR Transmit Datapath Enable. |
7 | TX_SCR_BPYASS | R/W | 0h | PCSR Transmit SCR Bypass. |
6 | TX_TEST_EN | R/W | 0h | PCSR Transmit Test Enable. |
5 | TX_TEST_SEL | R/W | 0h | PCSR Transmit Test Select. |
4 | TX_TEST_DAT_SEL | R/W | 0h | PCSR Transmit Test Data Select. |
3 | TX_PRBS31_EN | R/W | 0h | PCSR Transmit PRBS31 Enable. |
2 | TX_PRBS9_EN | R/W | 0h | PCSR Transmit PRBS9 Enable. |
1 | TX_LOOPBACK_EN | R/W | 0h | PCSR Transmit Loopback Enable. |
0 | TX_SCR_LOOPBK_EN | R/W | 0h | PCSR Transmit SCR Loopback Enable. |
CPSW_PCSR_TX_STATUS_REG is shown in Figure 12-720 and described in Table 12-1395.
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PCSR Transmit Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TX_FAULT | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | TX_FAULT | R/W | 0h | PCSR Transmit Fault Hold Register - write 1 to clear. |
7-0 | RESERVED | R/W | X |
CPSW_PCSR_RX_CTL_REG is shown in Figure 12-721 and described in Table 12-1397.
Return to Summary Table.
PCSR Receive Control Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_PRBS9_EN | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_TEST_EN | RX_TEST_DAT_SEL | RX_PRBS31_EN | RX_ERR_BLK_CNT_RST | RX_BER_CNT_RST | RX_TEST_CNT_PRE | RX_TEST_CNT_125US | RX_TPTER_CNT_RST |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | RX_PRBS9_EN | R/W | 0h | PCSR Receive PRBS9 Enable. |
7 | RX_TEST_EN | R/W | 0h | PCSR Receive Test Enable. |
6 | RX_TEST_DAT_SEL | R/W | 0h | PCSR Receive Test Data Select. |
5 | RX_PRBS31_EN | R/W | 0h | PCSR Receive PRBS31 Enable. |
4 | RX_ERR_BLK_CNT_RST | R/W | 0h | PCSR Receive Error Block Count Reset. |
3 | RX_BER_CNT_RST | R/W | 0h | PCSR Receive BER Count Reset. |
2 | RX_TEST_CNT_PRE | R/W | 0h | PCSR Receive Test Count Pre. |
1 | RX_TEST_CNT_125US | R/W | 0h | PCSR Receive Test Count 125us. |
0 | RX_TPTER_CNT_RST | R/W | 0h | PCSR Receive TPTER Count Reset |
CPSW_PCSR_RX_STATUS_REG is shown in Figure 12-722 and described in Table 12-1399.
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PCSR Receive Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 210Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RX_HI_BER | RX_BLOCK_LOCK | RX_BER_COUNT | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_ERR_BLK_CNT | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_TPT_ERR_CNT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_TPT_ERR_CNT | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RX_HI_BER | R | 0h | PCSR Receive High BER. |
30 | RX_BLOCK_LOCK | R | 0h | PCSR Receive Block Lock. |
29-24 | RX_BER_COUNT | R | 0h | PCSR Receive BER Count. |
23-16 | RX_ERR_BLK_CNT | R | 0h | PCSR Error Block Count. |
15-0 | RX_TPT_ERR_CNT | R | 0h | PCSR TPT Error Count. |
CPSW_PCSR_SEED_A_LO_REG is shown in Figure 12-723 and described in Table 12-1401.
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PCSR Seed A Low Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEED_A_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SEED_A_LO | R/W | 0h | PCSR Seed A Low. |
CPSW_PCSR_SEED_A_HI_REG is shown in Figure 12-724 and described in Table 12-1403.
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PCSR Seed A High Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEED_A_HI | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-0 | SEED_A_HI | R/W | 0h | PCSR Seed A High. |
CPSW_PCSR_SEED_B_LO_REG is shown in Figure 12-725 and described in Table 12-1405.
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PCSR Seed B Low Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2118h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEED_B_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SEED_B_LO | R/W | 0h | PCSR Seed B Low. |
CPSW_PCSR_SEED_B_HI_REG is shown in Figure 12-726 and described in Table 12-1407.
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PCSR Seed B High Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 211Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEED_B_HI | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-0 | SEED_B_HI | R/W | 0h | PCSR Seed B High. |
CPSW_PCSR_FEC_REG is shown in Figure 12-727 and described in Table 12-1409.
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PCSR FEC Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FEC_ENA_ERR_IND | FEC_ENABLE | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | FEC_ENA_ERR_IND | R/W | 0h | PCSR FEC ENA Error Ind. |
0 | FEC_ENABLE | R/W | 0h | PCSR FEC Enable. |
CPSW_PCSR_CTL_REG is shown in Figure 12-728 and described in Table 12-1411.
Return to Summary Table.
PCSR Control Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2124h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIGNAL_OK_EN | SIGNAL_OK | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | SIGNAL_OK_EN | R/W | 0h | PCSR Signal OK Enable. |
0 | SIGNAL_OK | R/W | 0h | PCSR Signal OK. |
CPSW_PCSR_FEC_CNT_REG is shown in Figure 12-729 and described in Table 12-1413.
Return to Summary Table.
PCSR FEC Count Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 2128h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEC_CORR_CNT | FEC_UNCORRCNT | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FEC_CORR_CNT | R/W | 0h | PCSR FEC Corrected Error Count. |
15-0 | FEC_UNCORRCNT | R/W | 0h | PCSR FEC Uncorrected Error Count. |
CPSW_PCSR_ERROR_FIFO_REG is shown in Figure 12-730 and described in Table 12-1415.
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PCSR Error FIFO Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_PCSR | 0800 212Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERROR_FIFO_CTC | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | ERROR_FIFO_CTC | R/W | 0h | PCSR Error FIFO CTC. |