SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

8.1.2 DDRSS Environment

Please refer to the AM64x DDR Board Design and Layout Guidelines application note for detailed information on DDR interface connections to LPDDR4 and DDR4 memory devices

Table 8-2 describes the DDRSS0 I/O signals used for connection to SDRAM devices.

Table 8-2 DDRSS0 I/O signals

Module Pin	Device Level Signal	I/O⁽¹⁾	Description	Module Pin Reset Value⁽²⁾
RESETN	DDR0_RESET0_n	O	SDRAM reset	0x0
CK	DDR0_CK0	O	SDRAM differential clock pair	0x0
CKN	DDR0_CK0_n	O	SDRAM differential clock pair	0x1
ALERTN	DDR0_ALERT_n	IO	SDRAM parity error output	HiZ
A[13-0]	DDR0_A[13-0]	O	SDRAM address and command bus	HiZ
WEN	DDR0_WE_n	O	SDRAM write enable	0x0
CASN	DDR0_CAS_n	O	SDRAM column address strobe	0x0
RASN	DDR0_RAS_n	O	SDRAM row address strobe	0x0
ACTN	DDR0_ACT_n	O	SDRAM activate	0x0
BA[1-0]	DDR0_BA[1-0]	O	SDRAM bank address	0x0
BG[1-0]	DDR0_BG[1-0]	O	SDRAM bank group	0x0
PAR	DDR0_PAR	O	SDRAM command parity	0x0
CSN[1-0]	DDR0_CS[1-0]_n	O	SDRAM chip select	0x0
ODT[1-0]	DDR0_ODT[1-0]	O	SDRAM on-die termination	0x0
CKE[1-0]	DDR0_CKE[1-0]	O	SDRAM CKE	0x0
DQ[15-0]	DDR0_DQ[15-0]	IO	SDRAM data bus	HiZ
DM[1-0]	DDR0_DM[1-0]	IO	SDRAM data and mask/DBI	HiZ
DQS[1-0]	DDR0_DQS[1-0]	IO	SDRAM data strobe	HiZ
DQSN[1-0]	DDR0_DQS[1-0]_n	IO	SDRAM data strobe invert	HiZ

(1) I = Input; O = Output

(2) HiZ = High Impedance

Note:

For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.