It may be desirable to isolate the
reset only to PCIe subsystem when it is operating as an End Point. Such resets may
be implemented when a Hot Reset command is received from upstream device
(Root
Complex or Switch). The sequence to be followed is as outlined
below.
- Hot Reset is received. The
“Request Reset” interrupt is triggered.
- The PCIe subsystem will
automatically enter Flush Mode. The PCIe Link Training and Status State
Machine (LTSSM) will be disabled automatically.
- PCIe subsystem will complete
all controller transactions and any completion data from pending
transactions will be accepted and discarded. It will also start issuing
error response for new target transactions.
- Upon receipt of the reset
interrupt from PCIe subsystem, the system software must immediately start
preparing for shut down of PCIe subsystem. The DMA or software process
accessing PCIe subsystem should gracefully suspend operations. Otherwise,
step #3 may continue for unduly long time and
Root
Complex may assume that the EP is non-responsive to its
link re-training attempts.
- Read the Reset Command
register (PCIE_USER_RSTCMD) to check if the bridge activity flush bit is
zero. This indicates that it is safe to issue warm reset to PCIe
subsystem.
- Initiate Clock Stop sequence.
This will ensure no outstanding transactions exist.
- Issue a PCIe subsystem
Reset.
- Resume initialization
sequence.