SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-5085 lists the memory-mapped registers for an ECC Aggregator (ECC_AGGR). All register offset addresses not listed in Table 12-5085 should be considered as reserved locations and the register contents should not be modified.
This section shows all possible registers and bits which an ECC aggregator may have. For specific physical addresses and particular ECC aggregator registers associated with each ECC protected module or subsystem, see the corresponding Registers section.
Offset | Acronym | Register Name |
---|---|---|
0h | ECC_REV | Aggregator Revision Register |
8h | ECC_VECTOR | ECC Vector Register |
Ch | ECC_STAT | Misc Status Register |
ECC Wrapper Registers | ||
10h | ECC_WRAP_REV | ECC Wrapper Revision Register |
14h | ECC_CTRL | ECC RAM Control Register |
18h | ECC_ERR_CTRL1 | ECC RAM Error Control 1 Register |
1Ch | ECC_ERR_CTRL2 | ECC RAM Error Control 2 Register |
20h | ECC_ERR_STAT1 | ECC RAM Error Status 1 Register |
24h | ECC_ERR_STAT2 | ECC RAM Error Status 2 Register |
28h | ECC_ERR_STAT3 | ECC RAM Error Status 3 Register |
Interconnect ECC Component Registers | ||
10h | ECC_CBASS_REV | Interconnect ECC Component Revision Register |
14h | ECC_CBASS_CTRL | Interconnect ECC Component Control Register |
18h | ECC_CBASS_ERR_CTRL1 | Interconnect ECC Component Error Control 1 Register |
1Ch | ECC_CBASS_ERR_CTRL2 | Interconnect ECC Component Error Control 2 Register |
20h | ECC_CBASS_ERR_STAT1 | Interconnect ECC Component Error Status 1 Register |
24h | ECC_CBASS_ERR_STAT2 | Interconnect ECC Component Error Status 2 Register |
3Ch | ECC_SEC_EOI_REG | EOI Register for Correctable Error |
40h | ECC_SEC_STATUS_REG0 | Interrupt Status Register 0 for Correctable Error |
44h | ECC_SEC_STATUS_REG1 | Interrupt Status Register 1 for Correctable Error |
48h | ECC_SEC_STATUS_REG2 | Interrupt Status Register 2 for Correctable Error |
4Ch | ECC_SEC_STATUS_REG3 | Interrupt Status Register 3 for Correctable Error |
50h | ECC_SEC_STATUS_REG4 | Interrupt Status Register 4 for Correctable Error |
54h | ECC_SEC_STATUS_REG5 | Interrupt Status Register 5 for Correctable Error |
58h | ECC_SEC_STATUS_REG6 | Interrupt Status Register 6 for Correctable Error |
5Ch | ECC_SEC_STATUS_REG7 | Interrupt Status Register 7 for Correctable Error |
80h | ECC_SEC_ENABLE_SET_REG0 | Interrupt Enable Register 0 for Correctable Error |
84h | ECC_SEC_ENABLE_SET_REG1 | Interrupt Enable Register 1 for Correctable Error |
88h | ECC_SEC_ENABLE_SET_REG2 | Interrupt Enable Register 2 for Correctable Error |
8Ch | ECC_SEC_ENABLE_SET_REG3 | Interrupt Enable Register 3 for Correctable Error |
90h | ECC_SEC_ENABLE_SET_REG4 | Interrupt Enable Register 4 for Correctable Error |
94h | ECC_SEC_ENABLE_SET_REG5 | Interrupt Enable Register 5 for Correctable Error |
98h | ECC_SEC_ENABLE_SET_REG6 | Interrupt Enable Register 6 for Correctable Error |
9Ch | ECC_SEC_ENABLE_SET_REG7 | Interrupt Enable Register 7 for Correctable Error |
C0h | ECC_SEC_ENABLE_CLR_REG0 | Interrupt Disable Register 0 for Correctable Error |
C4h | ECC_SEC_ENABLE_CLR_REG1 | Interrupt Disable Register 1 for Correctable Error |
C8h | ECC_SEC_ENABLE_CLR_REG2 | Interrupt Disable Register 2 for Correctable Error |
CCh | ECC_SEC_ENABLE_CLR_REG3 | Interrupt Disable Register 3 for Correctable Error |
D0h | ECC_SEC_ENABLE_CLR_REG4 | Interrupt Disable Register 4 for Correctable Error |
D4h | ECC_SEC_ENABLE_CLR_REG5 | Interrupt Disable Register 5 for Correctable Error |
D8h | ECC_SEC_ENABLE_CLR_REG6 | Interrupt Disable Register 6 for Correctable Error |
DCh | ECC_SEC_ENABLE_CLR_REG7 | Interrupt Disable Register 7 for Correctable Error |
13Ch | ECC_DED_EOI_REG | EOI Register for Non-correctable Error |
140h | ECC_DED_STATUS_REG0 | Interrupt Status Register 0 for Non-correctable Error |
144h | ECC_DED_STATUS_REG1 | Interrupt Status Register 1 for Non-correctable Error |
148h | ECC_DED_STATUS_REG2 | Interrupt Status Register 2 for Non-correctable Error |
14Ch | ECC_DED_STATUS_REG3 | Interrupt Status Register 3 for Non-correctable Error |
150h | ECC_DED_STATUS_REG4 | Interrupt Status Register 4 for Non-correctable Error |
154h | ECC_DED_STATUS_REG5 | Interrupt Status Register 5 for Non-correctable Error |
158h | ECC_DED_STATUS_REG6 | Interrupt Status Register 6 for Non-correctable Error |
15Ch | ECC_DED_STATUS_REG7 | Interrupt Status Register 7 for Non-correctable Error |
180h | ECC_DED_ENABLE_SET_REG0 | Interrupt Enable Register 0 for Non-correctable Error |
184h | ECC_DED_ENABLE_SET_REG1 | Interrupt Enable Register 1 for Non-correctable Error |
188h | ECC_DED_ENABLE_SET_REG2 | Interrupt Enable Register 2 for Non-correctable Error |
18Ch | ECC_DED_ENABLE_SET_REG3 | Interrupt Enable Register 3 for Non-correctable Error |
190h | ECC_DED_ENABLE_SET_REG4 | Interrupt Enable Register 4 for Non-correctable Error |
194h | ECC_DED_ENABLE_SET_REG5 | Interrupt Enable Register 5 for Non-correctable Error |
198h | ECC_DED_ENABLE_SET_REG6 | Interrupt Enable Register 6 for Non-correctable Error |
19Ch | ECC_DED_ENABLE_SET_REG7 | Interrupt Enable Register 7 for Non-correctable Error |
1C0h | ECC_DED_ENABLE_CLR_REG0 | Interrupt Disable Register 0 for Non-correctable Error |
1C4h | ECC_DED_ENABLE_CLR_REG1 | Interrupt Disable Register 1 for Non-correctable Error |
1C8h | ECC_DED_ENABLE_CLR_REG2 | Interrupt Disable Register 2 for Non-correctable Error |
1CCh | ECC_DED_ENABLE_CLR_REG3 | Interrupt Disable Register 3 for Non-correctable Error |
1D0h | ECC_DED_ENABLE_CLR_REG4 | Interrupt Disable Register 4 for Non-correctable Error |
1D4h | ECC_DED_ENABLE_CLR_REG5 | Interrupt Disable Register 5 for Non-correctable Error |
1D8h | ECC_DED_ENABLE_CLR_REG6 | Interrupt Disable Register 6 for Non-correctable Error |
1DCh | ECC_DED_ENABLE_CLR_REG7 | Interrupt Disable Register 7 for Non-correctable Error |
200h | ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Register |
204h | ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Disable Register |
208h | ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register |
20Ch | ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register |
ECC_REV is shown in Figure 12-2638 and described in Table 12-5086.
Return to Summary Table.
Aggregator Revision Register
Revision parameters.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A0A600h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A0A600h | TI internal data. |
ECC_VECTOR is shown in Figure 12-2639 and described in Table 12-5087.
Return to Summary Table.
ECC Vector Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0 | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on the ECC serial interface is complete. Write of any value clears this bit. 0h - Read not complete 1h - Read complete |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address. Can be any of the registers (0x10 - 0x24). |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger. Write 1h to trigger a read on the ECC serial interface. Note: NOTE: In normal operation (that is, in ECC mode), this bit is 1h only for a single cycle and thus cannot be read back. |
14-11 | RESERVED | R | 0 | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC endpoint ID. Value written to select which ECC endpoint to control or read status from. |
ECC_STAT is shown in Figure 12-2640 and described in Table 12-5088.
Return to Summary Table.
Misc Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-Xh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0 | Reserved |
10-0 | NUM_RAMS | R | Xh | Indicates the number of ECC endpoints serviced by the ECC aggregator. |
ECC_WRAP_REV is shown in Figure 12-2641 and described in Table 12-5089.
Return to Summary Table.
ECC Wrapper Revision Register
Revision parameters.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A49A02h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A49A02h | TI internal data. |
ECC_CTRL is shown in Figure 12-2642 and described in Table 12-5090.
Return to Summary Table.
ECC RAM Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHECK_SVBUS_TIMEOUT | ||||||
R-0h | R/W-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHECK_PARITY | ERROR_ONCE | FORCE_N_ROW | FORCE_DED | FORCE_SEC | ENABLE_RMW | ECC_CHECK | ECC_ENABLE |
R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0 | Reserved |
8 | CHECK_SVBUS_TIMEOUT | R/W | 1h | Enable ECC serial interface timeout mechanism 0h - Timeout mechanism disabled 1h - Timeout mechanism enabled |
7 | CHECK_PARITY | R/W | 1h | Enables parity checking on internal data 0h - Parity checking disabled 1h - Parity checking enabled |
6 | ERROR_ONCE | R/W | 0h | Force error only once. If this bit is set to 1h, the FORCE_SEC/FORCE_DED injects an error to the specified row only once. The FORCE_SEC bit is cleared the cycle after the error is generated. For double-bit errors, the FORCE_DED bit is cleared the cycle following the double-bit error. Any subsequent reads do not force an error. |
5 | FORCE_N_ROW | R/W | 0h | Force error on any RAM read Force single or double-bit error on the next RAM access. For write through mode this applies to writes as well as reads. |
4 | FORCE_DED | R/W | 0h | Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is 1h. For write through mode this applies to writes as well as reads. |
3 | FORCE_SEC | R/W | 0h | Force single-bit error. Cleared the cycle following the error if ERROR_ONCE is 1h. For write through mode this applies to writes as well as reads. |
2 | ENABLE_RMW | R/W | 1h | Enable read-modify-write on partial word writes. 0h - Read-modify-write disabled 1h - Read-modify-write enabled Note: NOTE: If disabled, ECC detection and correction does no longer work and if re-enabled the RAM contents must all be rewritten to correct ECC codes. The reset value of this bit is 0h in inject only mode and 1h in ECC mode. |
1 | ECC_CHECK | R/W | 1h | Enable ECC check. 0h - ECC check disabled 1h - ECC check enabled Note: NOTE: ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are 0h. The reset value of this bit is 0h in inject only mode and 1h in ECC mode. |
0 | ECC_ENABLE | R/W | 1h | Enable ECC generation. 0h - ECC generation disabled 1h - ECC generation enabled |
ECC_ERR_CTRL1 is shown in Figure 12-2643 and described in Table 12-5091.
Return to Summary Table.
ECC RAM Error Control 1 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ROW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ECC_ROW | R/W | 0h | Row address where single or double-bit error needs to be applied. This is ignored if ECC_CTRL[5] FORCE_N_ROW bit is set to 1h. |
ECC_ERR_CTRL2 is shown in Figure 12-2644 and described in Table 12-5092.
Return to Summary Table.
ECC RAM Error Control 2 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_BIT2 | ECC_BIT1 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ECC_BIT2 | R/W | 0h | Data bit that needs to be flipped if double-bit error has to be forced. The ECC_CTRL[4] FORCE_DED bit must be set to 1h for these values to take affect. |
15-0 | ECC_BIT1 | R/W | 0h | Data bit that needs to be flipped if single-bit error has to be forced. The ECC_CTRL[3] FORCE_SEC bit must be set to 1h for these values to take affect. |
ECC_ERR_STAT1 is shown in Figure 12-2645 and described in Table 12-5093.
Return to Summary Table.
ECC RAM Error Status 1 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ECC_BIT1 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECC_BIT1 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLR_CTRL_REG_ERR | CLR_PARITY_ERR | CLR_ECC_OTHER | CLR_ECC_DED | CLR_ECC_SEC | |||
R/W1C-0h | R/W-0h | R/W1C-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTR_REG_ERR | PARITY_ERR | ECC_OTHER | ECC_DED | ECC_SEC | |||
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ECC_BIT1 | R | 0h | Indicates the bit position in the RAM data that is in error. For example, a value of 1h indicates that bit [1] in the RAM data is in error. This is valid only for single-bit errors. Note: NOTE: Not used in inject only mode. Always read as 0h. |
15 | CLR_CTRL_REG_ERR | R/W1C | 0h | Clear the CTR_REG_ERR bit. A write of 1h clears this bit and the CTR_REG_ERR bit, but if the redundancy protected bits in the ECC_CTRL register have not been written to a known state to correct the error, this flag is immediately set again. |
14-13 | CLR_PARITY_ERR | R/W | 0h | A write of a non-zero value to this field decrements the CLR_ECC_DED and ECC_DED fields by that value. If the value written is less than the current one, the non-correctable interrupt (ECC_DED_INT) stays asserted. If the value to decrement is more than the current value, the result is 0. 0h - No parity errors have occurred 1h - 1 parity error has occurred 2h - 2 parity errors have occurred 3h - 3 or more parity errors have occurred |
12 | CLR_ECC_OTHER | R/W1C | 0h | Clear other error status. 1h indicates a successive single-bit error. Writing 1h clears the status bit. |
11-10 | CLR_ECC_DED | R/W | 0h | A write of a non-zero value to this field decrements it and the ECC_DED field by that value. If the value written is less than the current one, the non-correctable interrupt (ECC_DED_INT) stays asserted. If the value to decrement is more than the current value, the result is 0. 0h - No double-bit errors have occurred 1h - 1 double-bit has error occurred 2h - 2 double-bit have errors occurred 3h - 3 or more double-bit errors have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
9-8 | CLR_ECC_SEC | R/W | 0h | A write of a non-zero value to this field decrements it and the ECC_SEC field by that value. If the value written is less than the current one, the correctable interrupt (ECC_SEC_INT) stays asserted. If the value to decrement is more than the current value, the result is 0. 0h - No single-bit errors have occurred 1h - 1 single-bit has occurred 2h - 2 single-bit have occurred 3h - 3 or more single-bit have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
7 | CTR_REG_ERR | R/W1S | 0h | Indicates that a redundancy protected bit in the ECC_CTRL register has been flipped. This means that the redundancy logic have detected a state where not all values are the same and has defaulted to the reset state. Software needs to re-write these registers to a known state. A write of 1h sets this bit. 0h - Bit not flipped 1h - Bit flipped |
6-5 | PARITY_ERR | R/W1S | 0h | 2-bit saturating counter for the number of parity errors that have occurred since last cleared. This is also a status set register and a non-zero value sets the level interrupt. Software can also write a value to the CLR_PARITY_ERR field to decrement this counter. 0h - No parity errors have occurred 1h - 1 parity error has occurred 2h - 2 parity errors have occurred 3h - 3 or more parity errors have occurred |
4 | ECC_OTHER | R/W1S | 0h | 1h - Indicates that successive single-bit errors have occurred while a write-back is still pending. Software can also write 1h to set the pending status and write 1h to the corresponding clear bit to clear the status. Note: NOTE: Not used in inject only mode. Always read as 0h. |
3-2 | ECC_DED | R/W | 0h | 2-bit saturating counter for the number of double-bit errors that have occurred since last cleared. This is also a status set register and a non-zero value sets the level interrupt. Software can also write a value to the CLR_ECC_SEC field to decrement this counter. 0h - No double-bit errors have occurred 1h - 1 double-bit has error occurred 2h - 2 double-bit have errors occurred 3h - 3 or more double-bit errors have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
1-0 | ECC_SEC | R/W | 0h | 2-bit saturating counter for the number of single-bit errors that have occurred since last cleared. This is also a status set register and a non-zero value sets the level interrupt. Software can also write a value to the CLR_ECC_SEC field to decrement this counter. 0h - No single-bit errors have occurred 1h - 1 single-bit has occurred 2h - 2 single-bit have occurred 3h - 3 or more single-bit have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
ECC_ERR_STAT2 is shown in Figure 12-2646 and described in Table 12-5094.
Return to Summary Table.
ECC RAM Error Status 2 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ROW | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ECC_ROW | R | 0h | Row address where the single or double-bit error has occurred. Note: NOTE: Not used in inject only mode. Always read as 0h. |
ECC_ERR_STAT3 is shown in Figure 12-2647 and described in Table 12-5095.
Return to Summary Table.
ECC RAM Error Status 3 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLR_SVBUS_TIMEOUT_ERR | RESERVED | |||||
R-0h | R/W1C-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SVBUS_TIMEOUT_ERR | WB_PEND | |||||
R-0h | R/W1S-0h | R-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0 | Reserved |
9 | CLR_SVBUS_TIMEOUT_ERR | R/W1C | 0h | Clear ECC serial interface timeout error status 0h - No effect 1h - Clears this bit and the SVBUS_TIMEOUT_ERR bit |
8-2 | RESERVED | R | 0 | Reserved |
1 | SVBUS_TIMEOUT_ERR | R/W1S | 0h | ECC serial interface timeout error. Write a 1h to set the flag 0h - No timeout error 1h - Timeout error |
0 | WB_PEND | R | 0h | Delayed write-back pending status. 0h - An ECC data correction write-back is not pending 1h - An ECC data correction write-back is pending Note: NOTE: Not used in inject only mode. Always read as 0h. |
ECC_CBASS_REV is shown in Figure 12-2648 and described in Table 12-5096.
Return to Summary Table.
Interconnect ECC Component Revision Register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-Xh | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | Xh | TI internal data. |
ECC_CBASS_CTRL is shown in Figure 12-2649 and described in Table 12-5097.
Return to Summary Table.
Interconnect ECC Component Control Register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ECC_PATTERN | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FORCE_N_BIT | FORCE_DE | FORCE_SE | RESERVED | ECC_CHECK | RESERVED | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-1h | R-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | ECC_PATTERN | R/W | 0h | Data pattern to be used for injection. 0h = 0s 1h = Fs 2h = As 3h = 5s |
7-6 | RESERVED | R | 0h | Reserved |
5 | FORCE_N_BIT | R/W | 0h | Update injection fields after the injection to setup for the next incremental injection. 0h = Keep current settings after injection 1h = Increment to next bit or group after injection |
4 | FORCE_DE | R/W | 0h | Inject a double bit error when set. Automatically cleared when injection completes. |
3 | FORCE_SE | R/W | 0h | Inject a single bit error when set. Automatically cleared when injection completes. |
2 | RESERVED | R | 0h | Reserved |
1 | ECC_CHECK | R/W | 1h | Enable checkers. 0h = Disabled 1h = Enabled |
0 | RESERVED | R | 0h | Reserved |
ECC_CBASS_ERR_CTRL1 is shown in Figure 12-2650 and described in Table 12-5098.
Return to Summary Table.
Interconnect ECC Component Error Control 1 Register.
This register allows setting the injection data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ECC_BIT1 | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECC_BIT1 | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ECC_GRP | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_GRP | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24-16 | ECC_BIT1 | R/W | 0h | First bit to inject an error. |
15-0 | ECC_GRP | R/W | 0h | Group of checker to inject. |
ECC_CBASS_ERR_CTRL2 is shown in Figure 12-2651 and described in Table 12-5099.
Return to Summary Table.
Interconnect ECC Component Error Control 2 Register.
This register allows setting the injection data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_BIT2 | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8-0 | ECC_BIT2 | R/W | 0h | Second bit to inject an error. Only valid if ECC_CBASS_CTRL[4] FORCE_DE is set. |
ECC_CBASS_ERR_STAT1 is shown in Figure 12-2652 and described in Table 12-5100.
Return to Summary Table.
Interconnect ECC Component Error Status 1 Register.
This register allows reading the captured error data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ERR_GRP | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ERR_GRP | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INJ_UNC_PEND_CLR | INJ_COR_PEND_CLR | UNC_PEND_CLR | COR_PEND_CLR | ||||
R/WD-0h | R/WD-0h | R/WD-0h | R/WD-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INJ_UNC_PEND | INJ_COR_PEND | UNC_PEND | COR_PEND | ||||
R/WI-0h | R/WI-0h | R/WI-0h | R/WI-0h | ||||
LEGEND: R = Read Only; R/WD = Read/Write to Decrement Field; R/WI = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ERR_GRP | R | 0h | Specific checker that reported the error. |
15-14 | INJ_UNC_PEND_CLR | R/WD | 0h | Number of injected uncorrected pending interrupts (same value as UNC_PEND). Writing decrements INJ_UNC_PEND by that value. |
13-12 | INJ_COR_PEND_CLR | R/WD | 0h | Number of injected corrected pending interrupts (same value as COR_PEND). Writing decrements INJ_COR_PEND by that value. |
11-10 | UNC_PEND_CLR | R/WD | 0h | Number of uncorrected pending interrupts (same value as UNC_PEND). Writing decrements UNC_PEND by that value. |
9-8 | COR_PEND_CLR | R/WD | 0h | Number of corrected pending interrupts (same value as COR_PEND). Writing decrements COR_PEND by that value. |
7-6 | INJ_UNC_PEND | R/WI | 0h | Number of injected uncorrected pending interrupts. Writing increments by that value. |
5-4 | INJ_COR_PEND | R/WI | 0h | Number of injected corrected pending interrupts. Writing increments by that value. |
3-2 | UNC_PEND | R/WI | 0h | Number of uncorrected pending interrupts. Writing increments by that value. |
1-0 | COR_PEND | R/WI | 0h | Number of corrected pending interrupts. Writing increments by that value. |
ECC_CBASS_ERR_STAT2 is shown in Figure 12-2653 and described in Table 12-5101.
Return to Summary Table.
Interconnect ECC Component Error Status 2 Register.
This register allows reading the captured error data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR_TYPE | ERR_BIT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ERR_TYPE | R | 0h | This field is not supported and can read any value and be ignored. |
15-0 | ERR_BIT | R | 0h | Bit that caused the error. Always valid for EDC single bit corrected errors or redundant errors. Identifies parity segment number (but not the exact bit) with a parity error. This field is not valid for EDC double bit errors. |
ECC_SEC_EOI_REG is shown in Figure 12-2654 and described in Table 12-5102.
Return to Summary Table.
SEC EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0 | Reserved |
0 | EOI_WR | R/W1S | 0h | Write of 1h to this register indicates that software has serviced the correctable interrupt and next interrupt can be sent to the host. This bit is self clearing and read returns a zero. |
ECC_SEC_STATUS_REG0 is shown in Figure 12-2655 and described in Table 12-5103.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM31_PEND | RAM30_PEND | RAM29_PEND | RAM28_PEND | RAM27_PEND | RAM26_PEND | RAM25_PEND | RAM24_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM23_PEND | RAM22_PEND | RAM21_PEND | RAM20_PEND | RAM19_PEND | RAM18_PEND | RAM17_PEND | RAM16_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM15_PEND | RAM14_PEND | RAM13_PEND | RAM12_PEND | RAM11_PEND | RAM10_PEND | RAM9_PEND | RAM8_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM7_PEND | RAM6_PEND | RAM5_PEND | RAM4_PEND | RAM3_PEND | RAM2_PEND | RAM1_PEND | RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM31_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 31. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM30_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 30. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM29_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 29. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM28_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 28. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM27_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 27. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM26_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 26. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM25_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 25. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM24_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 24. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM23_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 23. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM22_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 22. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM21_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 21. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM20_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 20. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM19_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 19. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM18_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 18. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM17_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 17. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM16_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 16. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM15_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 15. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM14_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 14. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM13_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 13. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM12_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 12. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM11_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 11. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM10_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 10. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM9_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 9. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM8_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 8. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM7_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 7. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM6_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 6. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM5_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 5. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM4_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 4. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM3_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 3. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM2_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 2. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM1_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 1. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM0_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 0. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG1 is shown in Figure 12-2656 and described in Table 12-5104.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM63_PEND | RAM62_PEND | RAM61_PEND | RAM60_PEND | RAM59_PEND | RAM58_PEND | RAM57_PEND | RAM56_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM55_PEND | RAM54_PEND | RAM53_PEND | RAM52_PEND | RAM51_PEND | RAM50_PEND | RAM49_PEND | RAM48_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM47_PEND | RAM46_PEND | RAM45_PEND | RAM44_PEND | RAM43_PEND | RAM42_PEND | RAM41_PEND | RAM40_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM39_PEND | RAM38_PEND | RAM37_PEND | RAM36_PEND | RAM35_PEND | RAM34_PEND | RAM33_PEND | RAM32_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM63_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 63. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM62_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 62. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM61_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 61. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM60_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 60. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM59_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 59. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM58_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 58. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM57_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 57. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM56_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 56. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM55_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 55. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM54_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 54. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM53_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 53. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM52_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 52. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM51_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 51. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM50_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 50. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM49_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 49. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM48_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 48. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM47_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 47. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM46_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 46. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM45_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 45. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM44_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 44. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM43_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 43. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM42_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 42. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM41_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 41. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM40_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 40. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM39_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 39. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM38_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 38. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM37_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 37. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM36_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 36. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM35_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 35. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM34_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 34. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM33_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 33. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM32_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 32. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG2 is shown in Figure 12-2657 and described in Table 12-5105.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM95_PEND | RAM94_PEND | RAM93_PEND | RAM92_PEND | RAM91_PEND | RAM90_PEND | RAM89_PEND | RAM88_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM87_PEND | RAM86_PEND | RAM85_PEND | RAM84_PEND | RAM83_PEND | RAM82_PEND | RAM81_PEND | RAM80_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM79_PEND | RAM78_PEND | RAM77_PEND | RAM76_PEND | RAM75_PEND | RAM74_PEND | RAM73_PEND | RAM72_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM71_PEND | RAM70_PEND | RAM69_PEND | RAM68_PEND | RAM67_PEND | RAM66_PEND | RAM65_PEND | RAM64_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM95_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 95. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM94_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 94. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM93_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 93. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM92_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 92. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM91_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 91. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM90_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 90. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM89_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 89. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM88_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 88. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM87_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 87. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM86_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 86. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM85_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 85. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM84_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 84. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM83_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 83. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM82_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 82. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM81_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 81. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM80_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 80. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM79_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 79. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM78_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 78. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM77_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 77. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM76_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 76. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM75_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 75. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM74_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 74. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM73_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 73. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM72_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 72. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM71_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 71. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM70_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 70. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM69_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 69. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM68_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 68. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM67_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 67. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM66_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 66. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM65_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 65. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM64_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 64. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG3 is shown in Figure 12-2658 and described in Table 12-5106.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM127_PEND | RAM126_PEND | RAM125_PEND | RAM124_PEND | RAM123_PEND | RAM122_PEND | RAM121_PEND | RAM120_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM119_PEND | RAM118_PEND | RAM117_PEND | RAM116_PEND | RAM115_PEND | RAM114_PEND | RAM113_PEND | RAM112_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM111_PEND | RAM110_PEND | RAM109_PEND | RAM108_PEND | RAM107_PEND | RAM106_PEND | RAM105_PEND | RAM104_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM103_PEND | RAM102_PEND | RAM101_PEND | RAM100_PEND | RAM99_PEND | RAM98_PEND | RAM97_PEND | RAM96_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM127_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 127. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM126_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 126. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM125_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 125. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM124_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 124. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM123_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 123. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM122_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 122. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM121_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 121. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM120_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 120. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM119_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 119. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM118_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 118. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM117_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 117. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM116_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 116. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM115_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 115. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM114_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 114. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM113_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 113. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM112_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 112. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM111_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 111. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM110_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 110. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM109_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 109. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM108_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 108. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM107_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 107. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM106_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 106. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM105_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 105. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM104_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 104. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM103_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 103. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM102_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 102. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM101_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 101. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM100_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 100. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM99_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 99. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM98_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 98. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM97_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 97. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM96_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 96. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG4 is shown in Figure 12-2659 and described in Table 12-5107.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM159_PEND | RAM158_PEND | RAM157_PEND | RAM156_PEND | RAM155_PEND | RAM154_PEND | RAM153_PEND | RAM152_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM151_PEND | RAM150_PEND | RAM149_PEND | RAM148_PEND | RAM147_PEND | RAM146_PEND | RAM145_PEND | RAM144_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM143_PEND | RAM142_PEND | RAM141_PEND | RAM140_PEND | RAM139_PEND | RAM138_PEND | RAM137_PEND | RAM136_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM135_PEND | RAM134_PEND | RAM133_PEND | RAM132_PEND | RAM131_PEND | RAM130_PEND | RAM129_PEND | RAM128_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM159_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 159. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM158_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 158. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM157_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 157. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM156_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 156. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM155_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 155. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM154_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 154. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM153_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 153. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM152_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 152. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM151_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 151. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM150_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 150. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM149_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 149. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM148_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 148. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM147_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 147. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM146_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 146. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM145_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 145. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM144_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 144. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM143_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 143. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM142_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 142. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM141_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 141. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM140_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 140. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM139_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 139. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM138_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 138. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM137_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 137. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM136_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 136. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM135_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 135. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM134_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 134. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM133_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 133. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM132_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 132. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM131_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 131. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM130_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 130. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM129_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 129. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM128_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 128. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG5 is shown in Figure 12-2660 and described in Table 12-5108.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM191_PEND | RAM190_PEND | RAM189_PEND | RAM188_PEND | RAM187_PEND | RAM186_PEND | RAM185_PEND | RAM184_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM183_PEND | RAM182_PEND | RAM181_PEND | RAM180_PEND | RAM179_PEND | RAM178_PEND | RAM177_PEND | RAM176_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM175_PEND | RAM174_PEND | RAM173_PEND | RAM172_PEND | RAM171_PEND | RAM170_PEND | RAM169_PEND | RAM168_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM167_PEND | RAM166_PEND | RAM165_PEND | RAM164_PEND | RAM163_PEND | RAM162_PEND | RAM161_PEND | RAM160_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM191_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 191. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM190_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 190. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM189_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 189. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM188_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 188. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM187_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 187. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM186_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 186. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM185_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 185. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM184_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 184. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM183_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 183. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM182_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 182. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM181_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 181. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM180_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 180. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM179_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 179. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM178_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 178. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM177_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 177. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM176_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 176. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM175_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 175. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM174_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 174. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM173_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 173. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM172_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 172. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM171_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 171. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM170_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 170. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM169_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 169. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM168_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 168. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM167_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 167. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM166_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 166. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM165_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 165. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM164_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 164. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM163_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 163. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM162_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 162. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM161_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 161. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM160_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 160. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG6 is shown in Figure 12-2661 and described in Table 12-5109.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM223_PEND | RAM222_PEND | RAM221_PEND | RAM220_PEND | RAM219_PEND | RAM218_PEND | RAM217_PEND | RAM216_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM215_PEND | RAM214_PEND | RAM213_PEND | RAM212_PEND | RAM211_PEND | RAM210_PEND | RAM209_PEND | RAM208_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM207_PEND | RAM206_PEND | RAM205_PEND | RAM204_PEND | RAM203_PEND | RAM202_PEND | RAM201_PEND | RAM200_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM199_PEND | RAM198_PEND | RAM197_PEND | RAM196_PEND | RAM195_PEND | RAM194_PEND | RAM193_PEND | RAM192_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM223_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 223. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM222_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 222. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM221_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 221. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM220_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 220. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM219_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 219. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM218_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 218. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM217_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 217. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM216_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 216. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM215_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 215. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM214_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 214. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM213_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 213. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM212_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 212. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM211_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 211. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM210_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 210. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM209_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 209. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM208_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 208. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM207_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 207. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM206_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 206. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM205_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 205. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM204_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 204. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM203_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 203. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM202_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 202. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM201_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 201. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM200_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 200. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM199_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 199. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM198_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 198. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM197_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 197. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM196_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 196. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM195_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 195. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM194_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 194. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM193_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 193. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM192_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 192. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_STATUS_REG7 is shown in Figure 12-2662 and described in Table 12-5110.
Return to Summary Table.
Interrupt status register for correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM255_PEND | RAM254_PEND | RAM253_PEND | RAM252_PEND | RAM251_PEND | RAM250_PEND | RAM249_PEND | RAM248_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM247_PEND | RAM246_PEND | RAM245_PEND | RAM244_PEND | RAM243_PEND | RAM242_PEND | RAM241_PEND | RAM240_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM239_PEND | RAM238_PEND | RAM237_PEND | RAM236_PEND | RAM235_PEND | RAM234_PEND | RAM233_PEND | RAM232_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM231_PEND | RAM230_PEND | RAM229_PEND | RAM228_PEND | RAM227_PEND | RAM226_PEND | RAM225_PEND | RAM224_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM255_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 255. 0h - Correctable error not occurred 1h - Correctable error occurred |
30 | RAM254_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 254. 0h - Correctable error not occurred 1h - Correctable error occurred |
29 | RAM253_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 253. 0h - Correctable error not occurred 1h - Correctable error occurred |
28 | RAM252_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 252. 0h - Correctable error not occurred 1h - Correctable error occurred |
27 | RAM251_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 251. 0h - Correctable error not occurred 1h - Correctable error occurred |
26 | RAM250_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 250. 0h - Correctable error not occurred 1h - Correctable error occurred |
25 | RAM249_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 249. 0h - Correctable error not occurred 1h - Correctable error occurred |
24 | RAM248_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 248. 0h - Correctable error not occurred 1h - Correctable error occurred |
23 | RAM247_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 247. 0h - Correctable error not occurred 1h - Correctable error occurred |
22 | RAM246_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 246. 0h - Correctable error not occurred 1h - Correctable error occurred |
21 | RAM245_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 245. 0h - Correctable error not occurred 1h - Correctable error occurred |
20 | RAM244_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 244. 0h - Correctable error not occurred 1h - Correctable error occurred |
19 | RAM243_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 243. 0h - Correctable error not occurred 1h - Correctable error occurred |
18 | RAM242_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 242. 0h - Correctable error not occurred 1h - Correctable error occurred |
17 | RAM241_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 241. 0h - Correctable error not occurred 1h - Correctable error occurred |
16 | RAM240_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 240. 0h - Correctable error not occurred 1h - Correctable error occurred |
15 | RAM239_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 239. 0h - Correctable error not occurred 1h - Correctable error occurred |
14 | RAM238_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 238. 0h - Correctable error not occurred 1h - Correctable error occurred |
13 | RAM237_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 237. 0h - Correctable error not occurred 1h - Correctable error occurred |
12 | RAM236_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 236. 0h - Correctable error not occurred 1h - Correctable error occurred |
11 | RAM235_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 235. 0h - Correctable error not occurred 1h - Correctable error occurred |
10 | RAM234_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 234. 0h - Correctable error not occurred 1h - Correctable error occurred |
9 | RAM233_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 233. 0h - Correctable error not occurred 1h - Correctable error occurred |
8 | RAM232_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 232. 0h - Correctable error not occurred 1h - Correctable error occurred |
7 | RAM231_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 231. 0h - Correctable error not occurred 1h - Correctable error occurred |
6 | RAM230_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 230. 0h - Correctable error not occurred 1h - Correctable error occurred |
5 | RAM229_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 229. 0h - Correctable error not occurred 1h - Correctable error occurred |
4 | RAM228_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 228. 0h - Correctable error not occurred 1h - Correctable error occurred |
3 | RAM227_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 227. 0h - Correctable error not occurred 1h - Correctable error occurred |
2 | RAM226_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 226. 0h - Correctable error not occurred 1h - Correctable error occurred |
1 | RAM225_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 225. 0h - Correctable error not occurred 1h - Correctable error occurred |
0 | RAM224_PEND | R/W1S | 0h | Correctable error interrupt status for ECC endpoint with ID = 224. 0h - Correctable error not occurred 1h - Correctable error occurred |
ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2663 and described in Table 12-5111.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM31_ENABLE_SET | RAM30_ENABLE_SET | RAM29_ENABLE_SET | RAM28_ENABLE_SET | RAM27_ENABLE_SET | RAM26_ENABLE_SET | RAM25_ENABLE_SET | RAM24_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM23_ENABLE_SET | RAM22_ENABLE_SET | RAM21_ENABLE_SET | RAM20_ENABLE_SET | RAM19_ENABLE_SET | RAM18_ENABLE_SET | RAM17_ENABLE_SET | RAM16_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM15_ENABLE_SET | RAM14_ENABLE_SET | RAM13_ENABLE_SET | RAM12_ENABLE_SET | RAM11_ENABLE_SET | RAM10_ENABLE_SET | RAM9_ENABLE_SET | RAM8_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM7_ENABLE_SET | RAM6_ENABLE_SET | RAM5_ENABLE_SET | RAM4_ENABLE_SET | RAM3_ENABLE_SET | RAM2_ENABLE_SET | RAM1_ENABLE_SET | RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM31_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 31. Write 1h to enable the interrupt |
30 | RAM30_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 30. Write 1h to enable the interrupt |
29 | RAM29_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 29. Write 1h to enable the interrupt |
28 | RAM28_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 28. Write 1h to enable the interrupt |
27 | RAM27_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 27. Write 1h to enable the interrupt |
26 | RAM26_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 26. Write 1h to enable the interrupt |
25 | RAM25_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 25. Write 1h to enable the interrupt |
24 | RAM24_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 24. Write 1h to enable the interrupt |
23 | RAM23_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 23. Write 1h to enable the interrupt |
22 | RAM22_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 22. Write 1h to enable the interrupt |
21 | RAM21_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 21. Write 1h to enable the interrupt |
20 | RAM20_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 20. Write 1h to enable the interrupt |
19 | RAM19_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 19. Write 1h to enable the interrupt |
18 | RAM18_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 18. Write 1h to enable the interrupt |
17 | RAM17_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 17. Write 1h to enable the interrupt |
16 | RAM16_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 16. Write 1h to enable the interrupt |
15 | RAM15_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 15. Write 1h to enable the interrupt |
14 | RAM14_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 14. Write 1h to enable the interrupt |
13 | RAM13_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 13. Write 1h to enable the interrupt |
12 | RAM12_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 12. Write 1h to enable the interrupt |
11 | RAM11_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 11. Write 1h to enable the interrupt |
10 | RAM10_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 10. Write 1h to enable the interrupt |
9 | RAM9_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 9. Write 1h to enable the interrupt |
8 | RAM8_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 8. Write 1h to enable the interrupt |
7 | RAM7_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 7. Write 1h to enable the interrupt |
6 | RAM6_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 6. Write 1h to enable the interrupt |
5 | RAM5_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 5. Write 1h to enable the interrupt |
4 | RAM4_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 4. Write 1h to enable the interrupt |
3 | RAM3_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 3. Write 1h to enable the interrupt |
2 | RAM2_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 2. Write 1h to enable the interrupt |
1 | RAM1_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 1. Write 1h to enable the interrupt |
0 | RAM0_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 0. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG1 is shown in Figure 12-2664 and described in Table 12-5112.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM63_ENABLE_SET | RAM62_ENABLE_SET | RAM61_ENABLE_SET | RAM60_ENABLE_SET | RAM59_ENABLE_SET | RAM58_ENABLE_SET | RAM57_ENABLE_SET | RAM56_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM55_ENABLE_SET | RAM54_ENABLE_SET | RAM53_ENABLE_SET | RAM52_ENABLE_SET | RAM51_ENABLE_SET | RAM50_ENABLE_SET | RAM49_ENABLE_SET | RAM48_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM47_ENABLE_SET | RAM46_ENABLE_SET | RAM45_ENABLE_SET | RAM44_ENABLE_SET | RAM43_ENABLE_SET | RAM42_ENABLE_SET | RAM41_ENABLE_SET | RAM40_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM39_ENABLE_SET | RAM38_ENABLE_SET | RAM37_ENABLE_SET | RAM36_ENABLE_SET | RAM35_ENABLE_SET | RAM34_ENABLE_SET | RAM33_ENABLE_SET | RAM32_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM63_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 63. Write 1h to enable the interrupt |
30 | RAM62_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 62. Write 1h to enable the interrupt |
29 | RAM61_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 61. Write 1h to enable the interrupt |
28 | RAM60_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 60. Write 1h to enable the interrupt |
27 | RAM59_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 59. Write 1h to enable the interrupt |
26 | RAM58_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 58. Write 1h to enable the interrupt |
25 | RAM57_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 57. Write 1h to enable the interrupt |
24 | RAM56_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 56. Write 1h to enable the interrupt |
23 | RAM55_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 55. Write 1h to enable the interrupt |
22 | RAM54_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 54. Write 1h to enable the interrupt |
21 | RAM53_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 53. Write 1h to enable the interrupt |
20 | RAM52_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 52. Write 1h to enable the interrupt |
19 | RAM51_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 51. Write 1h to enable the interrupt |
18 | RAM50_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 50. Write 1h to enable the interrupt |
17 | RAM49_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 49. Write 1h to enable the interrupt |
16 | RAM48_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 48. Write 1h to enable the interrupt |
15 | RAM47_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 47. Write 1h to enable the interrupt |
14 | RAM46_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 46. Write 1h to enable the interrupt |
13 | RAM45_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 45. Write 1h to enable the interrupt |
12 | RAM44_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 44. Write 1h to enable the interrupt |
11 | RAM43_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 43. Write 1h to enable the interrupt |
10 | RAM42_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 42. Write 1h to enable the interrupt |
9 | RAM41_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 41. Write 1h to enable the interrupt |
8 | RAM40_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 40. Write 1h to enable the interrupt |
7 | RAM39_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 39. Write 1h to enable the interrupt |
6 | RAM38_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 38. Write 1h to enable the interrupt |
5 | RAM37_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 37. Write 1h to enable the interrupt |
4 | RAM36_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 36. Write 1h to enable the interrupt |
3 | RAM35_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 35. Write 1h to enable the interrupt |
2 | RAM34_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 34. Write 1h to enable the interrupt |
1 | RAM33_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 33. Write 1h to enable the interrupt |
0 | RAM32_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 32. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG2 is shown in Figure 12-2665 and described in Table 12-5113.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM95_ENABLE_SET | RAM94_ENABLE_SET | RAM93_ENABLE_SET | RAM92_ENABLE_SET | RAM91_ENABLE_SET | RAM90_ENABLE_SET | RAM89_ENABLE_SET | RAM88_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM87_ENABLE_SET | RAM86_ENABLE_SET | RAM85_ENABLE_SET | RAM84_ENABLE_SET | RAM83_ENABLE_SET | RAM82_ENABLE_SET | RAM81_ENABLE_SET | RAM80_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM79_ENABLE_SET | RAM78_ENABLE_SET | RAM77_ENABLE_SET | RAM76_ENABLE_SET | RAM75_ENABLE_SET | RAM74_ENABLE_SET | RAM73_ENABLE_SET | RAM72_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM71_ENABLE_SET | RAM70_ENABLE_SET | RAM69_ENABLE_SET | RAM68_ENABLE_SET | RAM67_ENABLE_SET | RAM66_ENABLE_SET | RAM65_ENABLE_SET | RAM64_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM95_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 95. Write 1h to enable the interrupt |
30 | RAM94_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 94. Write 1h to enable the interrupt |
29 | RAM93_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 93. Write 1h to enable the interrupt |
28 | RAM92_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 92. Write 1h to enable the interrupt |
27 | RAM91_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 91. Write 1h to enable the interrupt |
26 | RAM90_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 90. Write 1h to enable the interrupt |
25 | RAM89_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 89. Write 1h to enable the interrupt |
24 | RAM88_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 88. Write 1h to enable the interrupt |
23 | RAM87_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 87. Write 1h to enable the interrupt |
22 | RAM86_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 86. Write 1h to enable the interrupt |
21 | RAM85_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 85. Write 1h to enable the interrupt |
20 | RAM84_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 84. Write 1h to enable the interrupt |
19 | RAM83_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 83. Write 1h to enable the interrupt |
18 | RAM82_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 82. Write 1h to enable the interrupt |
17 | RAM81_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 81. Write 1h to enable the interrupt |
16 | RAM80_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 80. Write 1h to enable the interrupt |
15 | RAM79_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 79. Write 1h to enable the interrupt |
14 | RAM78_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 78. Write 1h to enable the interrupt |
13 | RAM77_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 77. Write 1h to enable the interrupt |
12 | RAM76_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 76. Write 1h to enable the interrupt |
11 | RAM75_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 75. Write 1h to enable the interrupt |
10 | RAM74_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 74. Write 1h to enable the interrupt |
9 | RAM73_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 73. Write 1h to enable the interrupt |
8 | RAM72_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 72. Write 1h to enable the interrupt |
7 | RAM71_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 71. Write 1h to enable the interrupt |
6 | RAM70_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 70. Write 1h to enable the interrupt |
5 | RAM69_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 69. Write 1h to enable the interrupt |
4 | RAM68_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 68. Write 1h to enable the interrupt |
3 | RAM67_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 67. Write 1h to enable the interrupt |
2 | RAM66_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 66. Write 1h to enable the interrupt |
1 | RAM65_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 65. Write 1h to enable the interrupt |
0 | RAM64_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 64. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG3 is shown in Figure 12-2666 and described in Table 12-5114.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM127_ENABLE_SET | RAM126_ENABLE_SET | RAM125_ENABLE_SET | RAM124_ENABLE_SET | RAM123_ENABLE_SET | RAM122_ENABLE_SET | RAM121_ENABLE_SET | RAM120_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM119_ENABLE_SET | RAM118_ENABLE_SET | RAM117_ENABLE_SET | RAM116_ENABLE_SET | RAM115_ENABLE_SET | RAM114_ENABLE_SET | RAM113_ENABLE_SET | RAM112_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM111_ENABLE_SET | RAM110_ENABLE_SET | RAM109_ENABLE_SET | RAM108_ENABLE_SET | RAM107_ENABLE_SET | RAM106_ENABLE_SET | RAM105_ENABLE_SET | RAM104_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM103_ENABLE_SET | RAM102_ENABLE_SET | RAM101_ENABLE_SET | RAM100_ENABLE_SET | RAM99_ENABLE_SET | RAM98_ENABLE_SET | RAM97_ENABLE_SET | RAM96_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM127_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 127. Write 1h to enable the interrupt |
30 | RAM126_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 126. Write 1h to enable the interrupt |
29 | RAM125_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 125. Write 1h to enable the interrupt |
28 | RAM124_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 124. Write 1h to enable the interrupt |
27 | RAM123_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 123. Write 1h to enable the interrupt |
26 | RAM122_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 122. Write 1h to enable the interrupt |
25 | RAM121_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 121. Write 1h to enable the interrupt |
24 | RAM120_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 120. Write 1h to enable the interrupt |
23 | RAM119_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 119. Write 1h to enable the interrupt |
22 | RAM118_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 118. Write 1h to enable the interrupt |
21 | RAM117_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 117. Write 1h to enable the interrupt |
20 | RAM116_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 116. Write 1h to enable the interrupt |
19 | RAM115_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 115. Write 1h to enable the interrupt |
18 | RAM114_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 114. Write 1h to enable the interrupt |
17 | RAM113_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 113. Write 1h to enable the interrupt |
16 | RAM112_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 112. Write 1h to enable the interrupt |
15 | RAM111_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 111. Write 1h to enable the interrupt |
14 | RAM110_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 110. Write 1h to enable the interrupt |
13 | RAM109_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 109. Write 1h to enable the interrupt |
12 | RAM108_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 108. Write 1h to enable the interrupt |
11 | RAM107_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 107. Write 1h to enable the interrupt |
10 | RAM106_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 106. Write 1h to enable the interrupt |
9 | RAM105_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 105. Write 1h to enable the interrupt |
8 | RAM104_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 104. Write 1h to enable the interrupt |
7 | RAM103_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 103. Write 1h to enable the interrupt |
6 | RAM102_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 102. Write 1h to enable the interrupt |
5 | RAM101_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 101. Write 1h to enable the interrupt |
4 | RAM100_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 100. Write 1h to enable the interrupt |
3 | RAM99_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 99. Write 1h to enable the interrupt |
2 | RAM98_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 98. Write 1h to enable the interrupt |
1 | RAM97_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 97. Write 1h to enable the interrupt |
0 | RAM96_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 96. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG4 is shown in Figure 12-2667 and described in Table 12-5115.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM159_ENABLE_SET | RAM158_ENABLE_SET | RAM157_ENABLE_SET | RAM156_ENABLE_SET | RAM155_ENABLE_SET | RAM154_ENABLE_SET | RAM153_ENABLE_SET | RAM152_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM151_ENABLE_SET | RAM150_ENABLE_SET | RAM149_ENABLE_SET | RAM148_ENABLE_SET | RAM147_ENABLE_SET | RAM146_ENABLE_SET | RAM145_ENABLE_SET | RAM144_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM143_ENABLE_SET | RAM142_ENABLE_SET | RAM141_ENABLE_SET | RAM140_ENABLE_SET | RAM139_ENABLE_SET | RAM138_ENABLE_SET | RAM137_ENABLE_SET | RAM136_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM135_ENABLE_SET | RAM134_ENABLE_SET | RAM133_ENABLE_SET | RAM132_ENABLE_SET | RAM131_ENABLE_SET | RAM130_ENABLE_SET | RAM129_ENABLE_SET | RAM128_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM159_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 159. Write 1h to enable the interrupt |
30 | RAM158_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 158. Write 1h to enable the interrupt |
29 | RAM157_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 157. Write 1h to enable the interrupt |
28 | RAM156_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 156. Write 1h to enable the interrupt |
27 | RAM155_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 155. Write 1h to enable the interrupt |
26 | RAM154_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 154. Write 1h to enable the interrupt |
25 | RAM153_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 153. Write 1h to enable the interrupt |
24 | RAM152_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 152. Write 1h to enable the interrupt |
23 | RAM151_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 151. Write 1h to enable the interrupt |
22 | RAM150_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 150. Write 1h to enable the interrupt |
21 | RAM149_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 149. Write 1h to enable the interrupt |
20 | RAM148_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 148. Write 1h to enable the interrupt |
19 | RAM147_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 147. Write 1h to enable the interrupt |
18 | RAM146_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 146. Write 1h to enable the interrupt |
17 | RAM145_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 145. Write 1h to enable the interrupt |
16 | RAM144_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 144. Write 1h to enable the interrupt |
15 | RAM143_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 143. Write 1h to enable the interrupt |
14 | RAM142_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 142. Write 1h to enable the interrupt |
13 | RAM141_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 141. Write 1h to enable the interrupt |
12 | RAM140_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 140. Write 1h to enable the interrupt |
11 | RAM139_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 139. Write 1h to enable the interrupt |
10 | RAM138_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 138. Write 1h to enable the interrupt |
9 | RAM137_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 137. Write 1h to enable the interrupt |
8 | RAM136_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 136. Write 1h to enable the interrupt |
7 | RAM135_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 135. Write 1h to enable the interrupt |
6 | RAM134_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 134. Write 1h to enable the interrupt |
5 | RAM133_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 133. Write 1h to enable the interrupt |
4 | RAM132_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 132. Write 1h to enable the interrupt |
3 | RAM131_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 131. Write 1h to enable the interrupt |
2 | RAM130_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 130. Write 1h to enable the interrupt |
1 | RAM129_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 129. Write 1h to enable the interrupt |
0 | RAM128_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 128. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG5 is shown in Figure 12-2668 and described in Table 12-5116.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM191_ENABLE_SET | RAM190_ENABLE_SET | RAM189_ENABLE_SET | RAM188_ENABLE_SET | RAM187_ENABLE_SET | RAM186_ENABLE_SET | RAM185_ENABLE_SET | RAM184_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM183_ENABLE_SET | RAM182_ENABLE_SET | RAM181_ENABLE_SET | RAM180_ENABLE_SET | RAM179_ENABLE_SET | RAM178_ENABLE_SET | RAM177_ENABLE_SET | RAM176_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM175_ENABLE_SET | RAM174_ENABLE_SET | RAM173_ENABLE_SET | RAM172_ENABLE_SET | RAM171_ENABLE_SET | RAM170_ENABLE_SET | RAM169_ENABLE_SET | RAM168_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM167_ENABLE_SET | RAM166_ENABLE_SET | RAM165_ENABLE_SET | RAM164_ENABLE_SET | RAM163_ENABLE_SET | RAM162_ENABLE_SET | RAM161_ENABLE_SET | RAM160_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM191_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 191. Write 1h to enable the interrupt |
30 | RAM190_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 190. Write 1h to enable the interrupt |
29 | RAM189_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 189. Write 1h to enable the interrupt |
28 | RAM188_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 188. Write 1h to enable the interrupt |
27 | RAM187_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 187. Write 1h to enable the interrupt |
26 | RAM186_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 186. Write 1h to enable the interrupt |
25 | RAM185_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 185. Write 1h to enable the interrupt |
24 | RAM184_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 184. Write 1h to enable the interrupt |
23 | RAM183_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 183. Write 1h to enable the interrupt |
22 | RAM182_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 182. Write 1h to enable the interrupt |
21 | RAM181_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 181. Write 1h to enable the interrupt |
20 | RAM180_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 180. Write 1h to enable the interrupt |
19 | RAM179_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 179. Write 1h to enable the interrupt |
18 | RAM178_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 178. Write 1h to enable the interrupt |
17 | RAM177_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 177. Write 1h to enable the interrupt |
16 | RAM176_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 176. Write 1h to enable the interrupt |
15 | RAM175_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 175. Write 1h to enable the interrupt |
14 | RAM174_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 174. Write 1h to enable the interrupt |
13 | RAM173_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 173. Write 1h to enable the interrupt |
12 | RAM172_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 172. Write 1h to enable the interrupt |
11 | RAM171_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 171. Write 1h to enable the interrupt |
10 | RAM170_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 170. Write 1h to enable the interrupt |
9 | RAM169_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 169. Write 1h to enable the interrupt |
8 | RAM168_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 168. Write 1h to enable the interrupt |
7 | RAM167_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 167. Write 1h to enable the interrupt |
6 | RAM166_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 166. Write 1h to enable the interrupt |
5 | RAM165_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 165. Write 1h to enable the interrupt |
4 | RAM164_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 164. Write 1h to enable the interrupt |
3 | RAM163_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 163. Write 1h to enable the interrupt |
2 | RAM162_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 162. Write 1h to enable the interrupt |
1 | RAM161_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 161. Write 1h to enable the interrupt |
0 | RAM160_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 160. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG6 is shown in Figure 12-2669 and described in Table 12-5117.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM223_ENABLE_SET | RAM222_ENABLE_SET | RAM221_ENABLE_SET | RAM220_ENABLE_SET | RAM219_ENABLE_SET | RAM218_ENABLE_SET | RAM217_ENABLE_SET | RAM216_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM215_ENABLE_SET | RAM214_ENABLE_SET | RAM213_ENABLE_SET | RAM212_ENABLE_SET | RAM211_ENABLE_SET | RAM210_ENABLE_SET | RAM209_ENABLE_SET | RAM208_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM207_ENABLE_SET | RAM206_ENABLE_SET | RAM205_ENABLE_SET | RAM204_ENABLE_SET | RAM203_ENABLE_SET | RAM202_ENABLE_SET | RAM201_ENABLE_SET | RAM200_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM199_ENABLE_SET | RAM198_ENABLE_SET | RAM197_ENABLE_SET | RAM196_ENABLE_SET | RAM195_ENABLE_SET | RAM194_ENABLE_SET | RAM193_ENABLE_SET | RAM192_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM223_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 223. Write 1h to enable the interrupt |
30 | RAM222_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 222. Write 1h to enable the interrupt |
29 | RAM221_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 221. Write 1h to enable the interrupt |
28 | RAM220_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 220. Write 1h to enable the interrupt |
27 | RAM219_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 219. Write 1h to enable the interrupt |
26 | RAM218_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 218. Write 1h to enable the interrupt |
25 | RAM217_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 217. Write 1h to enable the interrupt |
24 | RAM216_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 216. Write 1h to enable the interrupt |
23 | RAM215_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 215. Write 1h to enable the interrupt |
22 | RAM214_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 214. Write 1h to enable the interrupt |
21 | RAM213_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 213. Write 1h to enable the interrupt |
20 | RAM212_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 212. Write 1h to enable the interrupt |
19 | RAM211_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 211. Write 1h to enable the interrupt |
18 | RAM210_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 210. Write 1h to enable the interrupt |
17 | RAM209_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 209. Write 1h to enable the interrupt |
16 | RAM208_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 208. Write 1h to enable the interrupt |
15 | RAM207_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 207. Write 1h to enable the interrupt |
14 | RAM206_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 206. Write 1h to enable the interrupt |
13 | RAM205_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 205. Write 1h to enable the interrupt |
12 | RAM204_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 204. Write 1h to enable the interrupt |
11 | RAM203_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 203. Write 1h to enable the interrupt |
10 | RAM202_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 202. Write 1h to enable the interrupt |
9 | RAM201_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 201. Write 1h to enable the interrupt |
8 | RAM200_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 200. Write 1h to enable the interrupt |
7 | RAM199_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 199. Write 1h to enable the interrupt |
6 | RAM198_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 198. Write 1h to enable the interrupt |
5 | RAM197_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 197. Write 1h to enable the interrupt |
4 | RAM196_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 196. Write 1h to enable the interrupt |
3 | RAM195_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 195. Write 1h to enable the interrupt |
2 | RAM194_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 194. Write 1h to enable the interrupt |
1 | RAM193_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 193. Write 1h to enable the interrupt |
0 | RAM192_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 192. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_SET_REG7 is shown in Figure 12-2670 and described in Table 12-5118.
Return to Summary Table.
Interrupt enable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM255_ENABLE_SET | RAM254_ENABLE_SET | RAM253_ENABLE_SET | RAM252_ENABLE_SET | RAM251_ENABLE_SET | RAM250_ENABLE_SET | RAM249_ENABLE_SET | RAM248_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM247_ENABLE_SET | RAM246_ENABLE_SET | RAM245_ENABLE_SET | RAM244_ENABLE_SET | RAM243_ENABLE_SET | RAM242_ENABLE_SET | RAM241_ENABLE_SET | RAM240_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM239_ENABLE_SET | RAM238_ENABLE_SET | RAM237_ENABLE_SET | RAM236_ENABLE_SET | RAM235_ENABLE_SET | RAM234_ENABLE_SET | RAM233_ENABLE_SET | RAM232_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM231_ENABLE_SET | RAM230_ENABLE_SET | RAM229_ENABLE_SET | RAM228_ENABLE_SET | RAM227_ENABLE_SET | RAM226_ENABLE_SET | RAM225_ENABLE_SET | RAM224_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM255_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 255. Write 1h to enable the interrupt |
30 | RAM254_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 254. Write 1h to enable the interrupt |
29 | RAM253_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 253. Write 1h to enable the interrupt |
28 | RAM252_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 252. Write 1h to enable the interrupt |
27 | RAM251_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 251. Write 1h to enable the interrupt |
26 | RAM250_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 250. Write 1h to enable the interrupt |
25 | RAM249_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 249. Write 1h to enable the interrupt |
24 | RAM248_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 248. Write 1h to enable the interrupt |
23 | RAM247_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 247. Write 1h to enable the interrupt |
22 | RAM246_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 246. Write 1h to enable the interrupt |
21 | RAM245_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 245. Write 1h to enable the interrupt |
20 | RAM244_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 244. Write 1h to enable the interrupt |
19 | RAM243_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 243. Write 1h to enable the interrupt |
18 | RAM242_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 242. Write 1h to enable the interrupt |
17 | RAM241_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 241. Write 1h to enable the interrupt |
16 | RAM240_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 240. Write 1h to enable the interrupt |
15 | RAM239_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 239. Write 1h to enable the interrupt |
14 | RAM238_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 238. Write 1h to enable the interrupt |
13 | RAM237_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 237. Write 1h to enable the interrupt |
12 | RAM236_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 236. Write 1h to enable the interrupt |
11 | RAM235_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 235. Write 1h to enable the interrupt |
10 | RAM234_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 234. Write 1h to enable the interrupt |
9 | RAM233_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 233. Write 1h to enable the interrupt |
8 | RAM232_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 232. Write 1h to enable the interrupt |
7 | RAM231_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 231. Write 1h to enable the interrupt |
6 | RAM230_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 230. Write 1h to enable the interrupt |
5 | RAM229_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 229. Write 1h to enable the interrupt |
4 | RAM228_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 228. Write 1h to enable the interrupt |
3 | RAM227_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 227. Write 1h to enable the interrupt |
2 | RAM226_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 226. Write 1h to enable the interrupt |
1 | RAM225_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 225. Write 1h to enable the interrupt |
0 | RAM224_ENABLE_SET | R/W1S | 0h | Correctable error interrupt enable for ECC endpoint with ID = 224. Write 1h to enable the interrupt |
ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2671 and described in Table 12-5119.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM31_ENABLE_CLR | RAM30_ENABLE_CLR | RAM29_ENABLE_CLR | RAM28_ENABLE_CLR | RAM27_ENABLE_CLR | RAM26_ENABLE_CLR | RAM25_ENABLE_CLR | RAM24_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM23_ENABLE_CLR | RAM22_ENABLE_CLR | RAM21_ENABLE_CLR | RAM20_ENABLE_CLR | RAM19_ENABLE_CLR | RAM18_ENABLE_CLR | RAM17_ENABLE_CLR | RAM16_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM15_ENABLE_CLR | RAM14_ENABLE_CLR | RAM13_ENABLE_CLR | RAM12_ENABLE_CLR | RAM11_ENABLE_CLR | RAM10_ENABLE_CLR | RAM9_ENABLE_CLR | RAM8_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM7_ENABLE_CLR | RAM6_ENABLE_CLR | RAM5_ENABLE_CLR | RAM4_ENABLE_CLR | RAM3_ENABLE_CLR | RAM2_ENABLE_CLR | RAM1_ENABLE_CLR | RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM31_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 31. Write 1h to disable the interrupt |
30 | RAM30_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 30. Write 1h to disable the interrupt |
29 | RAM29_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 29. Write 1h to disable the interrupt |
28 | RAM28_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 28. Write 1h to disable the interrupt |
27 | RAM27_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 27. Write 1h to disable the interrupt |
26 | RAM26_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 26. Write 1h to disable the interrupt |
25 | RAM25_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 25. Write 1h to disable the interrupt |
24 | RAM24_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 24. Write 1h to disable the interrupt |
23 | RAM23_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 23. Write 1h to disable the interrupt |
22 | RAM22_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 22. Write 1h to disable the interrupt |
21 | RAM21_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 21. Write 1h to disable the interrupt |
20 | RAM20_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 20. Write 1h to disable the interrupt |
19 | RAM19_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 19. Write 1h to disable the interrupt |
18 | RAM18_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 18. Write 1h to disable the interrupt |
17 | RAM17_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 17. Write 1h to disable the interrupt |
16 | RAM16_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 16. Write 1h to disable the interrupt |
15 | RAM15_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 15. Write 1h to disable the interrupt |
14 | RAM14_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 14. Write 1h to disable the interrupt |
13 | RAM13_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 13. Write 1h to disable the interrupt |
12 | RAM12_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 12. Write 1h to disable the interrupt |
11 | RAM11_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 11. Write 1h to disable the interrupt |
10 | RAM10_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 10. Write 1h to disable the interrupt |
9 | RAM9_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 9. Write 1h to disable the interrupt |
8 | RAM8_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 8. Write 1h to disable the interrupt |
7 | RAM7_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 7. Write 1h to disable the interrupt |
6 | RAM6_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 6. Write 1h to disable the interrupt |
5 | RAM5_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 5. Write 1h to disable the interrupt |
4 | RAM4_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 4. Write 1h to disable the interrupt |
3 | RAM3_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 3. Write 1h to disable the interrupt |
2 | RAM2_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 2. Write 1h to disable the interrupt |
1 | RAM1_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 1. Write 1h to disable the interrupt |
0 | RAM0_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 0. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG1 is shown in Figure 12-2672 and described in Table 12-5120.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM63_ENABLE_CLR | RAM62_ENABLE_CLR | RAM61_ENABLE_CLR | RAM60_ENABLE_CLR | RAM59_ENABLE_CLR | RAM58_ENABLE_CLR | RAM57_ENABLE_CLR | RAM56_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM55_ENABLE_CLR | RAM54_ENABLE_CLR | RAM53_ENABLE_CLR | RAM52_ENABLE_CLR | RAM51_ENABLE_CLR | RAM50_ENABLE_CLR | RAM49_ENABLE_CLR | RAM48_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM47_ENABLE_CLR | RAM46_ENABLE_CLR | RAM45_ENABLE_CLR | RAM44_ENABLE_CLR | RAM43_ENABLE_CLR | RAM42_ENABLE_CLR | RAM41_ENABLE_CLR | RAM40_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM39_ENABLE_CLR | RAM38_ENABLE_CLR | RAM37_ENABLE_CLR | RAM36_ENABLE_CLR | RAM35_ENABLE_CLR | RAM34_ENABLE_CLR | RAM33_ENABLE_CLR | RAM32_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM63_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 63. Write 1h to disable the interrupt |
30 | RAM62_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 62. Write 1h to disable the interrupt |
29 | RAM61_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 61. Write 1h to disable the interrupt |
28 | RAM60_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 60. Write 1h to disable the interrupt |
27 | RAM59_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 59. Write 1h to disable the interrupt |
26 | RAM58_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 58. Write 1h to disable the interrupt |
25 | RAM57_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 57. Write 1h to disable the interrupt |
24 | RAM56_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 56. Write 1h to disable the interrupt |
23 | RAM55_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 55. Write 1h to disable the interrupt |
22 | RAM54_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 54. Write 1h to disable the interrupt |
21 | RAM53_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 53. Write 1h to disable the interrupt |
20 | RAM52_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 52. Write 1h to disable the interrupt |
19 | RAM51_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 51. Write 1h to disable the interrupt |
18 | RAM50_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 50. Write 1h to disable the interrupt |
17 | RAM49_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 49. Write 1h to disable the interrupt |
16 | RAM48_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 48. Write 1h to disable the interrupt |
15 | RAM47_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 47. Write 1h to disable the interrupt |
14 | RAM46_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 46. Write 1h to disable the interrupt |
13 | RAM45_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 45. Write 1h to disable the interrupt |
12 | RAM44_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 44. Write 1h to disable the interrupt |
11 | RAM43_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 43. Write 1h to disable the interrupt |
10 | RAM42_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 42. Write 1h to disable the interrupt |
9 | RAM41_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 41. Write 1h to disable the interrupt |
8 | RAM40_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 40. Write 1h to disable the interrupt |
7 | RAM39_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 39. Write 1h to disable the interrupt |
6 | RAM38_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 38. Write 1h to disable the interrupt |
5 | RAM37_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 37. Write 1h to disable the interrupt |
4 | RAM36_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 36. Write 1h to disable the interrupt |
3 | RAM35_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 35. Write 1h to disable the interrupt |
2 | RAM34_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 34. Write 1h to disable the interrupt |
1 | RAM33_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 33. Write 1h to disable the interrupt |
0 | RAM32_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 32. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG2 is shown in Figure 12-2673 and described in Table 12-5121.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM95_ENABLE_CLR | RAM94_ENABLE_CLR | RAM93_ENABLE_CLR | RAM92_ENABLE_CLR | RAM91_ENABLE_CLR | RAM90_ENABLE_CLR | RAM89_ENABLE_CLR | RAM88_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM87_ENABLE_CLR | RAM86_ENABLE_CLR | RAM85_ENABLE_CLR | RAM84_ENABLE_CLR | RAM83_ENABLE_CLR | RAM82_ENABLE_CLR | RAM81_ENABLE_CLR | RAM80_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM79_ENABLE_CLR | RAM78_ENABLE_CLR | RAM77_ENABLE_CLR | RAM76_ENABLE_CLR | RAM75_ENABLE_CLR | RAM74_ENABLE_CLR | RAM73_ENABLE_CLR | RAM72_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM71_ENABLE_CLR | RAM70_ENABLE_CLR | RAM69_ENABLE_CLR | RAM68_ENABLE_CLR | RAM67_ENABLE_CLR | RAM66_ENABLE_CLR | RAM65_ENABLE_CLR | RAM64_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM95_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 95. Write 1h to disable the interrupt |
30 | RAM94_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 94. Write 1h to disable the interrupt |
29 | RAM93_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 93. Write 1h to disable the interrupt |
28 | RAM92_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 92. Write 1h to disable the interrupt |
27 | RAM91_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 91. Write 1h to disable the interrupt |
26 | RAM90_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 90. Write 1h to disable the interrupt |
25 | RAM89_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 89. Write 1h to disable the interrupt |
24 | RAM88_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 88. Write 1h to disable the interrupt |
23 | RAM87_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 87. Write 1h to disable the interrupt |
22 | RAM86_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 86. Write 1h to disable the interrupt |
21 | RAM85_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 85. Write 1h to disable the interrupt |
20 | RAM84_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 84. Write 1h to disable the interrupt |
19 | RAM83_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 83. Write 1h to disable the interrupt |
18 | RAM82_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 82. Write 1h to disable the interrupt |
17 | RAM81_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 81. Write 1h to disable the interrupt |
16 | RAM80_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 80. Write 1h to disable the interrupt |
15 | RAM79_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 79. Write 1h to disable the interrupt |
14 | RAM78_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 78. Write 1h to disable the interrupt |
13 | RAM77_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 77. Write 1h to disable the interrupt |
12 | RAM76_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 76. Write 1h to disable the interrupt |
11 | RAM75_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 75. Write 1h to disable the interrupt |
10 | RAM74_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 74. Write 1h to disable the interrupt |
9 | RAM73_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 73. Write 1h to disable the interrupt |
8 | RAM72_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 72. Write 1h to disable the interrupt |
7 | RAM71_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 71. Write 1h to disable the interrupt |
6 | RAM70_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 70. Write 1h to disable the interrupt |
5 | RAM69_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 69. Write 1h to disable the interrupt |
4 | RAM68_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 68. Write 1h to disable the interrupt |
3 | RAM67_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 67. Write 1h to disable the interrupt |
2 | RAM66_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 66. Write 1h to disable the interrupt |
1 | RAM65_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 65. Write 1h to disable the interrupt |
0 | RAM64_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 64. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG3 is shown in Figure 12-2674 and described in Table 12-5122.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM127_ENABLE_CLR | RAM126_ENABLE_CLR | RAM125_ENABLE_CLR | RAM124_ENABLE_CLR | RAM123_ENABLE_CLR | RAM122_ENABLE_CLR | RAM121_ENABLE_CLR | RAM120_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM119_ENABLE_CLR | RAM118_ENABLE_CLR | RAM117_ENABLE_CLR | RAM116_ENABLE_CLR | RAM115_ENABLE_CLR | RAM114_ENABLE_CLR | RAM113_ENABLE_CLR | RAM112_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM111_ENABLE_CLR | RAM110_ENABLE_CLR | RAM109_ENABLE_CLR | RAM108_ENABLE_CLR | RAM107_ENABLE_CLR | RAM106_ENABLE_CLR | RAM105_ENABLE_CLR | RAM104_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM103_ENABLE_CLR | RAM102_ENABLE_CLR | RAM101_ENABLE_CLR | RAM100_ENABLE_CLR | RAM99_ENABLE_CLR | RAM98_ENABLE_CLR | RAM97_ENABLE_CLR | RAM96_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM127_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 127. Write 1h to disable the interrupt |
30 | RAM126_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 126. Write 1h to disable the interrupt |
29 | RAM125_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 125. Write 1h to disable the interrupt |
28 | RAM124_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 124. Write 1h to disable the interrupt |
27 | RAM123_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 123. Write 1h to disable the interrupt |
26 | RAM122_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 122. Write 1h to disable the interrupt |
25 | RAM121_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 121. Write 1h to disable the interrupt |
24 | RAM120_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 120. Write 1h to disable the interrupt |
23 | RAM119_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 119. Write 1h to disable the interrupt |
22 | RAM118_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 118. Write 1h to disable the interrupt |
21 | RAM117_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 117. Write 1h to disable the interrupt |
20 | RAM116_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 116. Write 1h to disable the interrupt |
19 | RAM115_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 115. Write 1h to disable the interrupt |
18 | RAM114_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 114. Write 1h to disable the interrupt |
17 | RAM113_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 113. Write 1h to disable the interrupt |
16 | RAM112_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 112. Write 1h to disable the interrupt |
15 | RAM111_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 111. Write 1h to disable the interrupt |
14 | RAM110_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 110. Write 1h to disable the interrupt |
13 | RAM109_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 109. Write 1h to disable the interrupt |
12 | RAM108_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 108. Write 1h to disable the interrupt |
11 | RAM107_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 107. Write 1h to disable the interrupt |
10 | RAM106_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 106. Write 1h to disable the interrupt |
9 | RAM105_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 105. Write 1h to disable the interrupt |
8 | RAM104_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 104. Write 1h to disable the interrupt |
7 | RAM103_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 103. Write 1h to disable the interrupt |
6 | RAM102_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 102. Write 1h to disable the interrupt |
5 | RAM101_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 101. Write 1h to disable the interrupt |
4 | RAM100_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 100. Write 1h to disable the interrupt |
3 | RAM99_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 99. Write 1h to disable the interrupt |
2 | RAM98_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 98. Write 1h to disable the interrupt |
1 | RAM97_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 97. Write 1h to disable the interrupt |
0 | RAM96_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 96. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG4 is shown in Figure 12-2675 and described in Table 12-5123.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM159_ENABLE_CLR | RAM158_ENABLE_CLR | RAM157_ENABLE_CLR | RAM156_ENABLE_CLR | RAM155_ENABLE_CLR | RAM154_ENABLE_CLR | RAM153_ENABLE_CLR | RAM152_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM151_ENABLE_CLR | RAM150_ENABLE_CLR | RAM149_ENABLE_CLR | RAM148_ENABLE_CLR | RAM147_ENABLE_CLR | RAM146_ENABLE_CLR | RAM145_ENABLE_CLR | RAM144_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM143_ENABLE_CLR | RAM142_ENABLE_CLR | RAM141_ENABLE_CLR | RAM140_ENABLE_CLR | RAM139_ENABLE_CLR | RAM138_ENABLE_CLR | RAM137_ENABLE_CLR | RAM136_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM135_ENABLE_CLR | RAM134_ENABLE_CLR | RAM133_ENABLE_CLR | RAM132_ENABLE_CLR | RAM131_ENABLE_CLR | RAM130_ENABLE_CLR | RAM129_ENABLE_CLR | RAM128_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM159_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 159. Write 1h to disable the interrupt |
30 | RAM158_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 158. Write 1h to disable the interrupt |
29 | RAM157_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 157. Write 1h to disable the interrupt |
28 | RAM156_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 156. Write 1h to disable the interrupt |
27 | RAM155_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 155. Write 1h to disable the interrupt |
26 | RAM154_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 154. Write 1h to disable the interrupt |
25 | RAM153_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 153. Write 1h to disable the interrupt |
24 | RAM152_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 152. Write 1h to disable the interrupt |
23 | RAM151_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 151. Write 1h to disable the interrupt |
22 | RAM150_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 150. Write 1h to disable the interrupt |
21 | RAM149_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 149. Write 1h to disable the interrupt |
20 | RAM148_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 148. Write 1h to disable the interrupt |
19 | RAM147_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 147. Write 1h to disable the interrupt |
18 | RAM146_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 146. Write 1h to disable the interrupt |
17 | RAM145_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 145. Write 1h to disable the interrupt |
16 | RAM144_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 144. Write 1h to disable the interrupt |
15 | RAM143_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 143. Write 1h to disable the interrupt |
14 | RAM142_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 142. Write 1h to disable the interrupt |
13 | RAM141_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 141. Write 1h to disable the interrupt |
12 | RAM140_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 140. Write 1h to disable the interrupt |
11 | RAM139_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 139. Write 1h to disable the interrupt |
10 | RAM138_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 138. Write 1h to disable the interrupt |
9 | RAM137_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 137. Write 1h to disable the interrupt |
8 | RAM136_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 136. Write 1h to disable the interrupt |
7 | RAM135_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 135. Write 1h to disable the interrupt |
6 | RAM134_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 134. Write 1h to disable the interrupt |
5 | RAM133_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 133. Write 1h to disable the interrupt |
4 | RAM132_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 132. Write 1h to disable the interrupt |
3 | RAM131_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 131. Write 1h to disable the interrupt |
2 | RAM130_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 130. Write 1h to disable the interrupt |
1 | RAM129_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 129. Write 1h to disable the interrupt |
0 | RAM128_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 128. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG5 is shown in Figure 12-2676 and described in Table 12-5124.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM191_ENABLE_CLR | RAM190_ENABLE_CLR | RAM189_ENABLE_CLR | RAM188_ENABLE_CLR | RAM187_ENABLE_CLR | RAM186_ENABLE_CLR | RAM185_ENABLE_CLR | RAM184_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM183_ENABLE_CLR | RAM182_ENABLE_CLR | RAM181_ENABLE_CLR | RAM180_ENABLE_CLR | RAM179_ENABLE_CLR | RAM178_ENABLE_CLR | RAM177_ENABLE_CLR | RAM176_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM175_ENABLE_CLR | RAM174_ENABLE_CLR | RAM173_ENABLE_CLR | RAM172_ENABLE_CLR | RAM171_ENABLE_CLR | RAM170_ENABLE_CLR | RAM169_ENABLE_CLR | RAM168_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM167_ENABLE_CLR | RAM166_ENABLE_CLR | RAM165_ENABLE_CLR | RAM164_ENABLE_CLR | RAM163_ENABLE_CLR | RAM162_ENABLE_CLR | RAM161_ENABLE_CLR | RAM160_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM191_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 191. Write 1h to disable the interrupt |
30 | RAM190_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 190. Write 1h to disable the interrupt |
29 | RAM189_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 189. Write 1h to disable the interrupt |
28 | RAM188_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 188. Write 1h to disable the interrupt |
27 | RAM187_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 187. Write 1h to disable the interrupt |
26 | RAM186_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 186. Write 1h to disable the interrupt |
25 | RAM185_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 185. Write 1h to disable the interrupt |
24 | RAM184_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 184. Write 1h to disable the interrupt |
23 | RAM183_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 183. Write 1h to disable the interrupt |
22 | RAM182_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 182. Write 1h to disable the interrupt |
21 | RAM181_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 181. Write 1h to disable the interrupt |
20 | RAM180_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 180. Write 1h to disable the interrupt |
19 | RAM179_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 179. Write 1h to disable the interrupt |
18 | RAM178_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 178. Write 1h to disable the interrupt |
17 | RAM177_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 177. Write 1h to disable the interrupt |
16 | RAM176_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 176. Write 1h to disable the interrupt |
15 | RAM175_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 175. Write 1h to disable the interrupt |
14 | RAM174_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 174. Write 1h to disable the interrupt |
13 | RAM173_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 173. Write 1h to disable the interrupt |
12 | RAM172_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 172. Write 1h to disable the interrupt |
11 | RAM171_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 171. Write 1h to disable the interrupt |
10 | RAM170_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 170. Write 1h to disable the interrupt |
9 | RAM169_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 169. Write 1h to disable the interrupt |
8 | RAM168_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 168. Write 1h to disable the interrupt |
7 | RAM167_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 167. Write 1h to disable the interrupt |
6 | RAM166_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 166. Write 1h to disable the interrupt |
5 | RAM165_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 165. Write 1h to disable the interrupt |
4 | RAM164_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 164. Write 1h to disable the interrupt |
3 | RAM163_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 163. Write 1h to disable the interrupt |
2 | RAM162_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 162. Write 1h to disable the interrupt |
1 | RAM161_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 161. Write 1h to disable the interrupt |
0 | RAM160_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 160. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG6 is shown in Figure 12-2677 and described in Table 12-5125.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM223_ENABLE_CLR | RAM222_ENABLE_CLR | RAM221_ENABLE_CLR | RAM220_ENABLE_CLR | RAM219_ENABLE_CLR | RAM218_ENABLE_CLR | RAM217_ENABLE_CLR | RAM216_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM215_ENABLE_CLR | RAM214_ENABLE_CLR | RAM213_ENABLE_CLR | RAM212_ENABLE_CLR | RAM211_ENABLE_CLR | RAM210_ENABLE_CLR | RAM209_ENABLE_CLR | RAM208_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM207_ENABLE_CLR | RAM206_ENABLE_CLR | RAM205_ENABLE_CLR | RAM204_ENABLE_CLR | RAM203_ENABLE_CLR | RAM202_ENABLE_CLR | RAM201_ENABLE_CLR | RAM200_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM199_ENABLE_CLR | RAM198_ENABLE_CLR | RAM197_ENABLE_CLR | RAM196_ENABLE_CLR | RAM195_ENABLE_CLR | RAM194_ENABLE_CLR | RAM193_ENABLE_CLR | RAM192_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM223_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 223. Write 1h to disable the interrupt |
30 | RAM222_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 222. Write 1h to disable the interrupt |
29 | RAM221_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 221. Write 1h to disable the interrupt |
28 | RAM220_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 220. Write 1h to disable the interrupt |
27 | RAM219_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 219. Write 1h to disable the interrupt |
26 | RAM218_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 218. Write 1h to disable the interrupt |
25 | RAM217_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 217. Write 1h to disable the interrupt |
24 | RAM216_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 216. Write 1h to disable the interrupt |
23 | RAM215_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 215. Write 1h to disable the interrupt |
22 | RAM214_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 214. Write 1h to disable the interrupt |
21 | RAM213_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 213. Write 1h to disable the interrupt |
20 | RAM212_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 212. Write 1h to disable the interrupt |
19 | RAM211_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 211. Write 1h to disable the interrupt |
18 | RAM210_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 210. Write 1h to disable the interrupt |
17 | RAM209_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 209. Write 1h to disable the interrupt |
16 | RAM208_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 208. Write 1h to disable the interrupt |
15 | RAM207_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 207. Write 1h to disable the interrupt |
14 | RAM206_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 206. Write 1h to disable the interrupt |
13 | RAM205_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 205. Write 1h to disable the interrupt |
12 | RAM204_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 204. Write 1h to disable the interrupt |
11 | RAM203_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 203. Write 1h to disable the interrupt |
10 | RAM202_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 202. Write 1h to disable the interrupt |
9 | RAM201_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 201. Write 1h to disable the interrupt |
8 | RAM200_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 200. Write 1h to disable the interrupt |
7 | RAM199_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 199. Write 1h to disable the interrupt |
6 | RAM198_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 198. Write 1h to disable the interrupt |
5 | RAM197_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 197. Write 1h to disable the interrupt |
4 | RAM196_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 196. Write 1h to disable the interrupt |
3 | RAM195_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 195. Write 1h to disable the interrupt |
2 | RAM194_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 194. Write 1h to disable the interrupt |
1 | RAM193_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 193. Write 1h to disable the interrupt |
0 | RAM192_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 192. Write 1h to disable the interrupt |
ECC_SEC_ENABLE_CLR_REG7 is shown in Figure 12-2678 and described in Table 12-5126.
Return to Summary Table.
Interrupt disable register for correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM255_ENABLE_CLR | RAM254_ENABLE_CLR | RAM253_ENABLE_CLR | RAM252_ENABLE_CLR | RAM251_ENABLE_CLR | RAM250_ENABLE_CLR | RAM249_ENABLE_CLR | RAM248_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM247_ENABLE_CLR | RAM246_ENABLE_CLR | RAM245_ENABLE_CLR | RAM244_ENABLE_CLR | RAM243_ENABLE_CLR | RAM242_ENABLE_CLR | RAM241_ENABLE_CLR | RAM240_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM239_ENABLE_CLR | RAM238_ENABLE_CLR | RAM237_ENABLE_CLR | RAM236_ENABLE_CLR | RAM235_ENABLE_CLR | RAM234_ENABLE_CLR | RAM233_ENABLE_CLR | RAM232_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM231_ENABLE_CLR | RAM230_ENABLE_CLR | RAM229_ENABLE_CLR | RAM228_ENABLE_CLR | RAM227_ENABLE_CLR | RAM226_ENABLE_CLR | RAM225_ENABLE_CLR | RAM224_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM255_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 255. Write 1h to disable the interrupt |
30 | RAM254_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 254. Write 1h to disable the interrupt |
29 | RAM253_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 253. Write 1h to disable the interrupt |
28 | RAM252_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 252. Write 1h to disable the interrupt |
27 | RAM251_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 251. Write 1h to disable the interrupt |
26 | RAM250_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 250. Write 1h to disable the interrupt |
25 | RAM249_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 249. Write 1h to disable the interrupt |
24 | RAM248_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 248. Write 1h to disable the interrupt |
23 | RAM247_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 247. Write 1h to disable the interrupt |
22 | RAM246_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 246. Write 1h to disable the interrupt |
21 | RAM245_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 245. Write 1h to disable the interrupt |
20 | RAM244_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 244. Write 1h to disable the interrupt |
19 | RAM243_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 243. Write 1h to disable the interrupt |
18 | RAM242_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 242. Write 1h to disable the interrupt |
17 | RAM241_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 241. Write 1h to disable the interrupt |
16 | RAM240_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 240. Write 1h to disable the interrupt |
15 | RAM239_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 239. Write 1h to disable the interrupt |
14 | RAM238_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 238. Write 1h to disable the interrupt |
13 | RAM237_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 237. Write 1h to disable the interrupt |
12 | RAM236_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 236. Write 1h to disable the interrupt |
11 | RAM235_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 235. Write 1h to disable the interrupt |
10 | RAM234_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 234. Write 1h to disable the interrupt |
9 | RAM233_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 233. Write 1h to disable the interrupt |
8 | RAM232_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 232. Write 1h to disable the interrupt |
7 | RAM231_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 231. Write 1h to disable the interrupt |
6 | RAM230_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 230. Write 1h to disable the interrupt |
5 | RAM229_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 229. Write 1h to disable the interrupt |
4 | RAM228_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 228. Write 1h to disable the interrupt |
3 | RAM227_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 227. Write 1h to disable the interrupt |
2 | RAM226_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 226. Write 1h to disable the interrupt |
1 | RAM225_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 225. Write 1h to disable the interrupt |
0 | RAM224_ENABLE_CLR | R/W1C | 0h | Correctable error interrupt disable for ECC endpoint with ID = 224. Write 1h to disable the interrupt |
ECC_DED_EOI_REG is shown in Figure 12-2679 and described in Table 12-5127.
Return to Summary Table.
DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0 | Reserved |
0 | EOI_WR | R/W1S | 0h | Write of 1h to this register indicates that software has serviced the non-correctable interrupt and next interrupt can be sent to the host. This bit is self clearing and read returns a zero. |
ECC_DED_STATUS_REG0 is shown in Figure 12-2680 and described in Table 12-5128.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM31_PEND | RAM30_PEND | RAM29_PEND | RAM28_PEND | RAM27_PEND | RAM26_PEND | RAM25_PEND | RAM24_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM23_PEND | RAM22_PEND | RAM21_PEND | RAM20_PEND | RAM19_PEND | RAM18_PEND | RAM17_PEND | RAM16_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM15_PEND | RAM14_PEND | RAM13_PEND | RAM12_PEND | RAM11_PEND | RAM10_PEND | RAM9_PEND | RAM8_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM7_PEND | RAM6_PEND | RAM5_PEND | RAM4_PEND | RAM3_PEND | RAM2_PEND | RAM1_PEND | RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM31_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 31. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM30_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 30. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM29_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 29. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM28_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 28. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM27_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 27. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM26_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 26. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM25_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 25. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM24_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 24. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM23_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 23. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM22_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 22. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM21_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 21. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM20_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 20. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM19_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 19. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM18_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 18. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM17_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 17. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM16_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 16. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM15_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 15. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM14_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 14. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM13_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 13. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM12_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 12. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM11_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 11. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM10_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 10. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM9_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 9. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM8_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 8. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM7_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 7. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM6_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 6. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM5_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 5. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM4_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 4. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM3_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 3. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM2_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 2. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM1_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 1. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM0_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 0. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG1 is shown in Figure 12-2681 and described in Table 12-5129.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM63_PEND | RAM62_PEND | RAM61_PEND | RAM60_PEND | RAM59_PEND | RAM58_PEND | RAM57_PEND | RAM56_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM55_PEND | RAM54_PEND | RAM53_PEND | RAM52_PEND | RAM51_PEND | RAM50_PEND | RAM49_PEND | RAM48_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM47_PEND | RAM46_PEND | RAM45_PEND | RAM44_PEND | RAM43_PEND | RAM42_PEND | RAM41_PEND | RAM40_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM39_PEND | RAM38_PEND | RAM37_PEND | RAM36_PEND | RAM35_PEND | RAM34_PEND | RAM33_PEND | RAM32_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM63_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 63. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM62_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 62. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM61_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 61. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM60_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 60. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM59_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 59. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM58_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 58. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM57_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 57. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM56_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 56. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM55_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 55. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM54_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 54. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM53_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 53. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM52_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 52. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM51_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 51. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM50_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 50. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM49_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 49. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM48_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 48. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM47_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 47. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM46_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 46. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM45_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 45. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM44_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 44. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM43_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 43. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM42_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 42. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM41_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 41. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM40_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 40. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM39_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 39. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM38_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 38. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM37_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 37. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM36_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 36. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM35_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 35. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM34_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 34. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM33_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 33. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM32_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 32. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG2 is shown in Figure 12-2682 and described in Table 12-5130.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM95_PEND | RAM94_PEND | RAM93_PEND | RAM92_PEND | RAM91_PEND | RAM90_PEND | RAM89_PEND | RAM88_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM87_PEND | RAM86_PEND | RAM85_PEND | RAM84_PEND | RAM83_PEND | RAM82_PEND | RAM81_PEND | RAM80_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM79_PEND | RAM78_PEND | RAM77_PEND | RAM76_PEND | RAM75_PEND | RAM74_PEND | RAM73_PEND | RAM72_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM71_PEND | RAM70_PEND | RAM69_PEND | RAM68_PEND | RAM67_PEND | RAM66_PEND | RAM65_PEND | RAM64_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM95_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 95. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM94_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 94. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM93_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 93. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM92_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 92. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM91_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 91. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM90_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 90. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM89_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 89. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM88_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 88. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM87_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 87. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM86_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 86. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM85_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 85. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM84_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 84. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM83_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 83. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM82_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 82. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM81_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 81. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM80_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 80. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM79_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 79. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM78_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 78. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM77_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 77. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM76_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 76. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM75_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 75. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM74_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 74. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM73_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 73. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM72_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 72. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM71_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 71. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM70_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 70. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM69_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 69. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM68_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 68. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM67_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 67. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM66_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 66. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM65_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 65. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM64_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 64. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG3 is shown in Figure 12-2683 and described in Table 12-5131.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM127_PEND | RAM126_PEND | RAM125_PEND | RAM124_PEND | RAM123_PEND | RAM122_PEND | RAM121_PEND | RAM120_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM119_PEND | RAM118_PEND | RAM117_PEND | RAM116_PEND | RAM115_PEND | RAM114_PEND | RAM113_PEND | RAM112_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM111_PEND | RAM110_PEND | RAM109_PEND | RAM108_PEND | RAM107_PEND | RAM106_PEND | RAM105_PEND | RAM104_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM103_PEND | RAM102_PEND | RAM101_PEND | RAM100_PEND | RAM99_PEND | RAM98_PEND | RAM97_PEND | RAM96_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM127_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 127. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM126_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 126. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM125_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 125. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM124_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 124. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM123_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 123. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM122_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 122. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM121_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 121. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM120_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 120. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM119_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 119. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM118_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 118. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM117_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 117. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM116_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 116. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM115_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 115. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM114_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 114. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM113_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 113. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM112_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 112. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM111_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 111. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM110_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 110. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM109_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 109. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM108_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 108. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM107_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 107. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM106_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 106. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM105_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 105. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM104_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 104. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM103_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 103. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM102_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 102. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM101_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 101. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM100_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 100. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM99_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 99. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM98_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 98. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM97_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 97. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM96_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 96. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG4 is shown in Figure 12-2684 and described in Table 12-5132.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM159_PEND | RAM158_PEND | RAM157_PEND | RAM156_PEND | RAM155_PEND | RAM154_PEND | RAM153_PEND | RAM152_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM151_PEND | RAM150_PEND | RAM149_PEND | RAM148_PEND | RAM147_PEND | RAM146_PEND | RAM145_PEND | RAM144_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM143_PEND | RAM142_PEND | RAM141_PEND | RAM140_PEND | RAM139_PEND | RAM138_PEND | RAM137_PEND | RAM136_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM135_PEND | RAM134_PEND | RAM133_PEND | RAM132_PEND | RAM131_PEND | RAM130_PEND | RAM129_PEND | RAM128_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM159_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 159. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM158_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 158. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM157_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 157. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM156_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 156. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM155_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 155. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM154_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 154. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM153_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 153. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM152_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 152. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM151_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 151. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM150_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 150. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM149_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 149. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM148_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 148. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM147_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 147. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM146_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 146. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM145_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 145. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM144_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 144. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM143_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 143. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM142_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 142. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM141_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 141. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM140_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 140. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM139_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 139. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM138_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 138. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM137_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 137. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM136_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 136. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM135_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 135. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM134_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 134. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM133_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 133. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM132_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 132. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM131_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 131. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM130_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 130. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM129_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 129. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM128_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 128. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG5 is shown in Figure 12-2685 and described in Table 12-5133.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM191_PEND | RAM190_PEND | RAM189_PEND | RAM188_PEND | RAM187_PEND | RAM186_PEND | RAM185_PEND | RAM184_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM183_PEND | RAM182_PEND | RAM181_PEND | RAM180_PEND | RAM179_PEND | RAM178_PEND | RAM177_PEND | RAM176_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM175_PEND | RAM174_PEND | RAM173_PEND | RAM172_PEND | RAM171_PEND | RAM170_PEND | RAM169_PEND | RAM168_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM167_PEND | RAM166_PEND | RAM165_PEND | RAM164_PEND | RAM163_PEND | RAM162_PEND | RAM161_PEND | RAM160_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM191_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 191. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM190_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 190. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM189_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 189. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM188_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 188. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM187_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 187. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM186_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 186. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM185_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 185. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM184_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 184. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM183_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 183. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM182_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 182. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM181_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 181. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM180_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 180. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM179_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 179. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM178_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 178. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM177_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 177. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM176_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 176. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM175_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 175. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM174_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 174. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM173_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 173. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM172_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 172. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM171_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 171. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM170_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 170. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM169_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 169. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM168_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 168. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM167_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 167. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM166_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 166. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM165_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 165. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM164_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 164. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM163_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 163. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM162_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 162. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM161_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 161. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM160_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 160. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG6 is shown in Figure 12-2686 and described in Table 12-5134.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM223_PEND | RAM222_PEND | RAM221_PEND | RAM220_PEND | RAM219_PEND | RAM218_PEND | RAM217_PEND | RAM216_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM215_PEND | RAM214_PEND | RAM213_PEND | RAM212_PEND | RAM211_PEND | RAM210_PEND | RAM209_PEND | RAM208_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM207_PEND | RAM206_PEND | RAM205_PEND | RAM204_PEND | RAM203_PEND | RAM202_PEND | RAM201_PEND | RAM200_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM199_PEND | RAM198_PEND | RAM197_PEND | RAM196_PEND | RAM195_PEND | RAM194_PEND | RAM193_PEND | RAM192_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM223_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 223. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM222_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 222. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM221_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 221. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM220_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 220. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM219_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 219. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM218_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 218. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM217_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 217. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM216_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 216. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM215_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 215. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM214_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 214. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM213_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 213. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM212_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 212. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM211_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 211. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM210_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 210. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM209_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 209. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM208_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 208. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM207_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 207. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM206_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 206. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM205_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 205. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM204_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 204. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM203_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 203. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM202_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 202. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM201_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 201. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM200_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 200. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM199_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 199. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM198_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 198. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM197_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 197. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM196_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 196. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM195_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 195. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM194_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 194. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM193_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 193. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM192_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 192. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_STATUS_REG7 is shown in Figure 12-2687 and described in Table 12-5135.
Return to Summary Table.
Interrupt status register for non-correctable error. Each bit corresponds to the status from an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM255_PEND | RAM254_PEND | RAM253_PEND | RAM252_PEND | RAM251_PEND | RAM250_PEND | RAM249_PEND | RAM248_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM247_PEND | RAM246_PEND | RAM245_PEND | RAM244_PEND | RAM243_PEND | RAM242_PEND | RAM241_PEND | RAM240_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM239_PEND | RAM238_PEND | RAM237_PEND | RAM236_PEND | RAM235_PEND | RAM234_PEND | RAM233_PEND | RAM232_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM231_PEND | RAM230_PEND | RAM229_PEND | RAM228_PEND | RAM227_PEND | RAM226_PEND | RAM225_PEND | RAM224_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM255_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 255. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
30 | RAM254_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 254. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
29 | RAM253_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 253. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
28 | RAM252_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 252. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
27 | RAM251_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 251. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
26 | RAM250_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 250. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
25 | RAM249_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 249. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
24 | RAM248_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 248. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
23 | RAM247_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 247. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
22 | RAM246_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 246. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
21 | RAM245_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 245. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
20 | RAM244_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 244. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
19 | RAM243_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 243. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
18 | RAM242_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 242. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
17 | RAM241_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 241. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
16 | RAM240_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 240. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
15 | RAM239_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 239. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
14 | RAM238_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 238. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
13 | RAM237_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 237. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
12 | RAM236_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 236. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
11 | RAM235_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 235. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
10 | RAM234_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 234. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
9 | RAM233_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 233. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
8 | RAM232_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 232. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
7 | RAM231_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 231. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
6 | RAM230_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 230. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
5 | RAM229_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 229. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
4 | RAM228_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 228. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
3 | RAM227_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 227. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
2 | RAM226_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 226. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
1 | RAM225_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 225. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
0 | RAM224_PEND | R/W1S | 0h | Non-correctable error interrupt status for ECC endpoint with ID = 224. 0h - Non-correctable error not occurred 1h - Non-correctable error occurred |
ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2688 and described in Table 12-5136.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM31_ENABLE_SET | RAM30_ENABLE_SET | RAM29_ENABLE_SET | RAM28_ENABLE_SET | RAM27_ENABLE_SET | RAM26_ENABLE_SET | RAM25_ENABLE_SET | RAM24_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM23_ENABLE_SET | RAM22_ENABLE_SET | RAM21_ENABLE_SET | RAM20_ENABLE_SET | RAM19_ENABLE_SET | RAM18_ENABLE_SET | RAM17_ENABLE_SET | RAM16_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM15_ENABLE_SET | RAM14_ENABLE_SET | RAM13_ENABLE_SET | RAM12_ENABLE_SET | RAM11_ENABLE_SET | RAM10_ENABLE_SET | RAM9_ENABLE_SET | RAM8_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM7_ENABLE_SET | RAM6_ENABLE_SET | RAM5_ENABLE_SET | RAM4_ENABLE_SET | RAM3_ENABLE_SET | RAM2_ENABLE_SET | RAM1_ENABLE_SET | RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM31_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 31. Write 1h to enable the interrupt |
30 | RAM30_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 30. Write 1h to enable the interrupt |
29 | RAM29_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 29. Write 1h to enable the interrupt |
28 | RAM28_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 28. Write 1h to enable the interrupt |
27 | RAM27_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 27. Write 1h to enable the interrupt |
26 | RAM26_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 26. Write 1h to enable the interrupt |
25 | RAM25_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 25. Write 1h to enable the interrupt |
24 | RAM24_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 24. Write 1h to enable the interrupt |
23 | RAM23_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 23. Write 1h to enable the interrupt |
22 | RAM22_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 22. Write 1h to enable the interrupt |
21 | RAM21_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 21. Write 1h to enable the interrupt |
20 | RAM20_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 20. Write 1h to enable the interrupt |
19 | RAM19_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 19. Write 1h to enable the interrupt |
18 | RAM18_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 18. Write 1h to enable the interrupt |
17 | RAM17_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 17. Write 1h to enable the interrupt |
16 | RAM16_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 16. Write 1h to enable the interrupt |
15 | RAM15_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 15. Write 1h to enable the interrupt |
14 | RAM14_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 14. Write 1h to enable the interrupt |
13 | RAM13_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 13. Write 1h to enable the interrupt |
12 | RAM12_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 12. Write 1h to enable the interrupt |
11 | RAM11_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 11. Write 1h to enable the interrupt |
10 | RAM10_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 10. Write 1h to enable the interrupt |
9 | RAM9_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 9. Write 1h to enable the interrupt |
8 | RAM8_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 8. Write 1h to enable the interrupt |
7 | RAM7_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 7. Write 1h to enable the interrupt |
6 | RAM6_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 6. Write 1h to enable the interrupt |
5 | RAM5_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 5. Write 1h to enable the interrupt |
4 | RAM4_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 4. Write 1h to enable the interrupt |
3 | RAM3_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 3. Write 1h to enable the interrupt |
2 | RAM2_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 2. Write 1h to enable the interrupt |
1 | RAM1_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 1. Write 1h to enable the interrupt |
0 | RAM0_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 0. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG1 is shown in Figure 12-2689 and described in Table 12-5137.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM63_ENABLE_SET | RAM62_ENABLE_SET | RAM61_ENABLE_SET | RAM60_ENABLE_SET | RAM59_ENABLE_SET | RAM58_ENABLE_SET | RAM57_ENABLE_SET | RAM56_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM55_ENABLE_SET | RAM54_ENABLE_SET | RAM53_ENABLE_SET | RAM52_ENABLE_SET | RAM51_ENABLE_SET | RAM50_ENABLE_SET | RAM49_ENABLE_SET | RAM48_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM47_ENABLE_SET | RAM46_ENABLE_SET | RAM45_ENABLE_SET | RAM44_ENABLE_SET | RAM43_ENABLE_SET | RAM42_ENABLE_SET | RAM41_ENABLE_SET | RAM40_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM39_ENABLE_SET | RAM38_ENABLE_SET | RAM37_ENABLE_SET | RAM36_ENABLE_SET | RAM35_ENABLE_SET | RAM34_ENABLE_SET | RAM33_ENABLE_SET | RAM32_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM63_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 63. Write 1h to enable the interrupt |
30 | RAM62_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 62. Write 1h to enable the interrupt |
29 | RAM61_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 61. Write 1h to enable the interrupt |
28 | RAM60_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 60. Write 1h to enable the interrupt |
27 | RAM59_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 59. Write 1h to enable the interrupt |
26 | RAM58_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 58. Write 1h to enable the interrupt |
25 | RAM57_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 57. Write 1h to enable the interrupt |
24 | RAM56_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 56. Write 1h to enable the interrupt |
23 | RAM55_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 55. Write 1h to enable the interrupt |
22 | RAM54_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 54. Write 1h to enable the interrupt |
21 | RAM53_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 53. Write 1h to enable the interrupt |
20 | RAM52_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 52. Write 1h to enable the interrupt |
19 | RAM51_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 51. Write 1h to enable the interrupt |
18 | RAM50_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 50. Write 1h to enable the interrupt |
17 | RAM49_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 49. Write 1h to enable the interrupt |
16 | RAM48_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 48. Write 1h to enable the interrupt |
15 | RAM47_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 47. Write 1h to enable the interrupt |
14 | RAM46_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 46. Write 1h to enable the interrupt |
13 | RAM45_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 45. Write 1h to enable the interrupt |
12 | RAM44_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 44. Write 1h to enable the interrupt |
11 | RAM43_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 43. Write 1h to enable the interrupt |
10 | RAM42_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 42. Write 1h to enable the interrupt |
9 | RAM41_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 41. Write 1h to enable the interrupt |
8 | RAM40_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 40. Write 1h to enable the interrupt |
7 | RAM39_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 39. Write 1h to enable the interrupt |
6 | RAM38_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 38. Write 1h to enable the interrupt |
5 | RAM37_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 37. Write 1h to enable the interrupt |
4 | RAM36_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 36. Write 1h to enable the interrupt |
3 | RAM35_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 35. Write 1h to enable the interrupt |
2 | RAM34_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 34. Write 1h to enable the interrupt |
1 | RAM33_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 33. Write 1h to enable the interrupt |
0 | RAM32_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 32. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG2 is shown in Figure 12-2690 and described in Table 12-5138.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM95_ENABLE_SET | RAM94_ENABLE_SET | RAM93_ENABLE_SET | RAM92_ENABLE_SET | RAM91_ENABLE_SET | RAM90_ENABLE_SET | RAM89_ENABLE_SET | RAM88_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM87_ENABLE_SET | RAM86_ENABLE_SET | RAM85_ENABLE_SET | RAM84_ENABLE_SET | RAM83_ENABLE_SET | RAM82_ENABLE_SET | RAM81_ENABLE_SET | RAM80_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM79_ENABLE_SET | RAM78_ENABLE_SET | RAM77_ENABLE_SET | RAM76_ENABLE_SET | RAM75_ENABLE_SET | RAM74_ENABLE_SET | RAM73_ENABLE_SET | RAM72_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM71_ENABLE_SET | RAM70_ENABLE_SET | RAM69_ENABLE_SET | RAM68_ENABLE_SET | RAM67_ENABLE_SET | RAM66_ENABLE_SET | RAM65_ENABLE_SET | RAM64_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM95_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 95. Write 1h to enable the interrupt |
30 | RAM94_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 94. Write 1h to enable the interrupt |
29 | RAM93_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 93. Write 1h to enable the interrupt |
28 | RAM92_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 92. Write 1h to enable the interrupt |
27 | RAM91_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 91. Write 1h to enable the interrupt |
26 | RAM90_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 90. Write 1h to enable the interrupt |
25 | RAM89_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 89. Write 1h to enable the interrupt |
24 | RAM88_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 88. Write 1h to enable the interrupt |
23 | RAM87_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 87. Write 1h to enable the interrupt |
22 | RAM86_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 86. Write 1h to enable the interrupt |
21 | RAM85_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 85. Write 1h to enable the interrupt |
20 | RAM84_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 84. Write 1h to enable the interrupt |
19 | RAM83_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 83. Write 1h to enable the interrupt |
18 | RAM82_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 82. Write 1h to enable the interrupt |
17 | RAM81_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 81. Write 1h to enable the interrupt |
16 | RAM80_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 80. Write 1h to enable the interrupt |
15 | RAM79_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 79. Write 1h to enable the interrupt |
14 | RAM78_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 78. Write 1h to enable the interrupt |
13 | RAM77_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 77. Write 1h to enable the interrupt |
12 | RAM76_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 76. Write 1h to enable the interrupt |
11 | RAM75_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 75. Write 1h to enable the interrupt |
10 | RAM74_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 74. Write 1h to enable the interrupt |
9 | RAM73_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 73. Write 1h to enable the interrupt |
8 | RAM72_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 72. Write 1h to enable the interrupt |
7 | RAM71_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 71. Write 1h to enable the interrupt |
6 | RAM70_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 70. Write 1h to enable the interrupt |
5 | RAM69_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 69. Write 1h to enable the interrupt |
4 | RAM68_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 68. Write 1h to enable the interrupt |
3 | RAM67_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 67. Write 1h to enable the interrupt |
2 | RAM66_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 66. Write 1h to enable the interrupt |
1 | RAM65_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 65. Write 1h to enable the interrupt |
0 | RAM64_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 64. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG3 is shown in Figure 12-2691 and described in Table 12-5139.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM127_ENABLE_SET | RAM126_ENABLE_SET | RAM125_ENABLE_SET | RAM124_ENABLE_SET | RAM123_ENABLE_SET | RAM122_ENABLE_SET | RAM121_ENABLE_SET | RAM120_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM119_ENABLE_SET | RAM118_ENABLE_SET | RAM117_ENABLE_SET | RAM116_ENABLE_SET | RAM115_ENABLE_SET | RAM114_ENABLE_SET | RAM113_ENABLE_SET | RAM112_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM111_ENABLE_SET | RAM110_ENABLE_SET | RAM109_ENABLE_SET | RAM108_ENABLE_SET | RAM107_ENABLE_SET | RAM106_ENABLE_SET | RAM105_ENABLE_SET | RAM104_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM103_ENABLE_SET | RAM102_ENABLE_SET | RAM101_ENABLE_SET | RAM100_ENABLE_SET | RAM99_ENABLE_SET | RAM98_ENABLE_SET | RAM97_ENABLE_SET | RAM96_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM127_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 127. Write 1h to enable the interrupt |
30 | RAM126_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 126. Write 1h to enable the interrupt |
29 | RAM125_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 125. Write 1h to enable the interrupt |
28 | RAM124_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 124. Write 1h to enable the interrupt |
27 | RAM123_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 123. Write 1h to enable the interrupt |
26 | RAM122_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 122. Write 1h to enable the interrupt |
25 | RAM121_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 121. Write 1h to enable the interrupt |
24 | RAM120_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 120. Write 1h to enable the interrupt |
23 | RAM119_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 119. Write 1h to enable the interrupt |
22 | RAM118_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 118. Write 1h to enable the interrupt |
21 | RAM117_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 117. Write 1h to enable the interrupt |
20 | RAM116_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 116. Write 1h to enable the interrupt |
19 | RAM115_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 115. Write 1h to enable the interrupt |
18 | RAM114_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 114. Write 1h to enable the interrupt |
17 | RAM113_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 113. Write 1h to enable the interrupt |
16 | RAM112_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 112. Write 1h to enable the interrupt |
15 | RAM111_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 111. Write 1h to enable the interrupt |
14 | RAM110_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 110. Write 1h to enable the interrupt |
13 | RAM109_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 109. Write 1h to enable the interrupt |
12 | RAM108_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 108. Write 1h to enable the interrupt |
11 | RAM107_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 107. Write 1h to enable the interrupt |
10 | RAM106_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 106. Write 1h to enable the interrupt |
9 | RAM105_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 105. Write 1h to enable the interrupt |
8 | RAM104_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 104. Write 1h to enable the interrupt |
7 | RAM103_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 103. Write 1h to enable the interrupt |
6 | RAM102_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 102. Write 1h to enable the interrupt |
5 | RAM101_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 101. Write 1h to enable the interrupt |
4 | RAM100_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 100. Write 1h to enable the interrupt |
3 | RAM99_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 99. Write 1h to enable the interrupt |
2 | RAM98_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 98. Write 1h to enable the interrupt |
1 | RAM97_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 97. Write 1h to enable the interrupt |
0 | RAM96_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 96. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG4 is shown in Figure 12-2692 and described in Table 12-5140.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM159_ENABLE_SET | RAM158_ENABLE_SET | RAM157_ENABLE_SET | RAM156_ENABLE_SET | RAM155_ENABLE_SET | RAM154_ENABLE_SET | RAM153_ENABLE_SET | RAM152_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM151_ENABLE_SET | RAM150_ENABLE_SET | RAM149_ENABLE_SET | RAM148_ENABLE_SET | RAM147_ENABLE_SET | RAM146_ENABLE_SET | RAM145_ENABLE_SET | RAM144_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM143_ENABLE_SET | RAM142_ENABLE_SET | RAM141_ENABLE_SET | RAM140_ENABLE_SET | RAM139_ENABLE_SET | RAM138_ENABLE_SET | RAM137_ENABLE_SET | RAM136_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM135_ENABLE_SET | RAM134_ENABLE_SET | RAM133_ENABLE_SET | RAM132_ENABLE_SET | RAM131_ENABLE_SET | RAM130_ENABLE_SET | RAM129_ENABLE_SET | RAM128_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM159_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 159. Write 1h to enable the interrupt |
30 | RAM158_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 158. Write 1h to enable the interrupt |
29 | RAM157_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 157. Write 1h to enable the interrupt |
28 | RAM156_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 156. Write 1h to enable the interrupt |
27 | RAM155_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 155. Write 1h to enable the interrupt |
26 | RAM154_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 154. Write 1h to enable the interrupt |
25 | RAM153_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 153. Write 1h to enable the interrupt |
24 | RAM152_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 152. Write 1h to enable the interrupt |
23 | RAM151_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 151. Write 1h to enable the interrupt |
22 | RAM150_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 150. Write 1h to enable the interrupt |
21 | RAM149_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 149. Write 1h to enable the interrupt |
20 | RAM148_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 148. Write 1h to enable the interrupt |
19 | RAM147_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 147. Write 1h to enable the interrupt |
18 | RAM146_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 146. Write 1h to enable the interrupt |
17 | RAM145_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 145. Write 1h to enable the interrupt |
16 | RAM144_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 144. Write 1h to enable the interrupt |
15 | RAM143_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 143. Write 1h to enable the interrupt |
14 | RAM142_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 142. Write 1h to enable the interrupt |
13 | RAM141_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 141. Write 1h to enable the interrupt |
12 | RAM140_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 140. Write 1h to enable the interrupt |
11 | RAM139_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 139. Write 1h to enable the interrupt |
10 | RAM138_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 138. Write 1h to enable the interrupt |
9 | RAM137_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 137. Write 1h to enable the interrupt |
8 | RAM136_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 136. Write 1h to enable the interrupt |
7 | RAM135_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 135. Write 1h to enable the interrupt |
6 | RAM134_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 134. Write 1h to enable the interrupt |
5 | RAM133_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 133. Write 1h to enable the interrupt |
4 | RAM132_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 132. Write 1h to enable the interrupt |
3 | RAM131_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 131. Write 1h to enable the interrupt |
2 | RAM130_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 130. Write 1h to enable the interrupt |
1 | RAM129_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 129. Write 1h to enable the interrupt |
0 | RAM128_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 128. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG5 is shown in Figure 12-2693 and described in Table 12-5141.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM191_ENABLE_SET | RAM190_ENABLE_SET | RAM189_ENABLE_SET | RAM188_ENABLE_SET | RAM187_ENABLE_SET | RAM186_ENABLE_SET | RAM185_ENABLE_SET | RAM184_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM183_ENABLE_SET | RAM182_ENABLE_SET | RAM181_ENABLE_SET | RAM180_ENABLE_SET | RAM179_ENABLE_SET | RAM178_ENABLE_SET | RAM177_ENABLE_SET | RAM176_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM175_ENABLE_SET | RAM174_ENABLE_SET | RAM173_ENABLE_SET | RAM172_ENABLE_SET | RAM171_ENABLE_SET | RAM170_ENABLE_SET | RAM169_ENABLE_SET | RAM168_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM167_ENABLE_SET | RAM166_ENABLE_SET | RAM165_ENABLE_SET | RAM164_ENABLE_SET | RAM163_ENABLE_SET | RAM162_ENABLE_SET | RAM161_ENABLE_SET | RAM160_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM191_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 191. Write 1h to enable the interrupt |
30 | RAM190_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 190. Write 1h to enable the interrupt |
29 | RAM189_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 189. Write 1h to enable the interrupt |
28 | RAM188_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 188. Write 1h to enable the interrupt |
27 | RAM187_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 187. Write 1h to enable the interrupt |
26 | RAM186_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 186. Write 1h to enable the interrupt |
25 | RAM185_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 185. Write 1h to enable the interrupt |
24 | RAM184_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 184. Write 1h to enable the interrupt |
23 | RAM183_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 183. Write 1h to enable the interrupt |
22 | RAM182_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 182. Write 1h to enable the interrupt |
21 | RAM181_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 181. Write 1h to enable the interrupt |
20 | RAM180_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 180. Write 1h to enable the interrupt |
19 | RAM179_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 179. Write 1h to enable the interrupt |
18 | RAM178_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 178. Write 1h to enable the interrupt |
17 | RAM177_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 177. Write 1h to enable the interrupt |
16 | RAM176_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 176. Write 1h to enable the interrupt |
15 | RAM175_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 175. Write 1h to enable the interrupt |
14 | RAM174_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 174. Write 1h to enable the interrupt |
13 | RAM173_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 173. Write 1h to enable the interrupt |
12 | RAM172_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 172. Write 1h to enable the interrupt |
11 | RAM171_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 171. Write 1h to enable the interrupt |
10 | RAM170_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 170. Write 1h to enable the interrupt |
9 | RAM169_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 169. Write 1h to enable the interrupt |
8 | RAM168_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 168. Write 1h to enable the interrupt |
7 | RAM167_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 167. Write 1h to enable the interrupt |
6 | RAM166_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 166. Write 1h to enable the interrupt |
5 | RAM165_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 165. Write 1h to enable the interrupt |
4 | RAM164_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 164. Write 1h to enable the interrupt |
3 | RAM163_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 163. Write 1h to enable the interrupt |
2 | RAM162_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 162. Write 1h to enable the interrupt |
1 | RAM161_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 161. Write 1h to enable the interrupt |
0 | RAM160_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 160. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG6 is shown in Figure 12-2694 and described in Table 12-5142.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM223_ENABLE_SET | RAM222_ENABLE_SET | RAM221_ENABLE_SET | RAM220_ENABLE_SET | RAM219_ENABLE_SET | RAM218_ENABLE_SET | RAM217_ENABLE_SET | RAM216_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM215_ENABLE_SET | RAM214_ENABLE_SET | RAM213_ENABLE_SET | RAM212_ENABLE_SET | RAM211_ENABLE_SET | RAM210_ENABLE_SET | RAM209_ENABLE_SET | RAM208_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM207_ENABLE_SET | RAM206_ENABLE_SET | RAM205_ENABLE_SET | RAM204_ENABLE_SET | RAM203_ENABLE_SET | RAM202_ENABLE_SET | RAM201_ENABLE_SET | RAM200_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM199_ENABLE_SET | RAM198_ENABLE_SET | RAM197_ENABLE_SET | RAM196_ENABLE_SET | RAM195_ENABLE_SET | RAM194_ENABLE_SET | RAM193_ENABLE_SET | RAM192_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM223_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 223. Write 1h to enable the interrupt |
30 | RAM222_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 222. Write 1h to enable the interrupt |
29 | RAM221_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 221. Write 1h to enable the interrupt |
28 | RAM220_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 220. Write 1h to enable the interrupt |
27 | RAM219_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 219. Write 1h to enable the interrupt |
26 | RAM218_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 218. Write 1h to enable the interrupt |
25 | RAM217_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 217. Write 1h to enable the interrupt |
24 | RAM216_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 216. Write 1h to enable the interrupt |
23 | RAM215_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 215. Write 1h to enable the interrupt |
22 | RAM214_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 214. Write 1h to enable the interrupt |
21 | RAM213_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 213. Write 1h to enable the interrupt |
20 | RAM212_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 212. Write 1h to enable the interrupt |
19 | RAM211_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 211. Write 1h to enable the interrupt |
18 | RAM210_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 210. Write 1h to enable the interrupt |
17 | RAM209_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 209. Write 1h to enable the interrupt |
16 | RAM208_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 208. Write 1h to enable the interrupt |
15 | RAM207_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 207. Write 1h to enable the interrupt |
14 | RAM206_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 206. Write 1h to enable the interrupt |
13 | RAM205_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 205. Write 1h to enable the interrupt |
12 | RAM204_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 204. Write 1h to enable the interrupt |
11 | RAM203_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 203. Write 1h to enable the interrupt |
10 | RAM202_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 202. Write 1h to enable the interrupt |
9 | RAM201_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 201. Write 1h to enable the interrupt |
8 | RAM200_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 200. Write 1h to enable the interrupt |
7 | RAM199_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 199. Write 1h to enable the interrupt |
6 | RAM198_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 198. Write 1h to enable the interrupt |
5 | RAM197_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 197. Write 1h to enable the interrupt |
4 | RAM196_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 196. Write 1h to enable the interrupt |
3 | RAM195_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 195. Write 1h to enable the interrupt |
2 | RAM194_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 194. Write 1h to enable the interrupt |
1 | RAM193_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 193. Write 1h to enable the interrupt |
0 | RAM192_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 192. Write 1h to enable the interrupt |
ECC_DED_ENABLE_SET_REG7 is shown in Figure 12-2695 and described in Table 12-5143.
Return to Summary Table.
Interrupt enable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM255_ENABLE_SET | RAM254_ENABLE_SET | RAM253_ENABLE_SET | RAM252_ENABLE_SET | RAM251_ENABLE_SET | RAM250_ENABLE_SET | RAM249_ENABLE_SET | RAM248_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM247_ENABLE_SET | RAM246_ENABLE_SET | RAM245_ENABLE_SET | RAM244_ENABLE_SET | RAM243_ENABLE_SET | RAM242_ENABLE_SET | RAM241_ENABLE_SET | RAM240_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM239_ENABLE_SET | RAM238_ENABLE_SET | RAM237_ENABLE_SET | RAM236_ENABLE_SET | RAM235_ENABLE_SET | RAM234_ENABLE_SET | RAM233_ENABLE_SET | RAM232_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM231_ENABLE_SET | RAM230_ENABLE_SET | RAM229_ENABLE_SET | RAM228_ENABLE_SET | RAM227_ENABLE_SET | RAM226_ENABLE_SET | RAM225_ENABLE_SET | RAM224_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM255_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 255. Write 1h to enable the interrupt |
30 | RAM254_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 254. Write 1h to enable the interrupt |
29 | RAM253_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 253. Write 1h to enable the interrupt |
28 | RAM252_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 252. Write 1h to enable the interrupt |
27 | RAM251_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 251. Write 1h to enable the interrupt |
26 | RAM250_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 250. Write 1h to enable the interrupt |
25 | RAM249_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 249. Write 1h to enable the interrupt |
24 | RAM248_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 248. Write 1h to enable the interrupt |
23 | RAM247_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 247. Write 1h to enable the interrupt |
22 | RAM246_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 246. Write 1h to enable the interrupt |
21 | RAM245_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 245. Write 1h to enable the interrupt |
20 | RAM244_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 244. Write 1h to enable the interrupt |
19 | RAM243_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 243. Write 1h to enable the interrupt |
18 | RAM242_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 242. Write 1h to enable the interrupt |
17 | RAM241_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 241. Write 1h to enable the interrupt |
16 | RAM240_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 240. Write 1h to enable the interrupt |
15 | RAM239_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 239. Write 1h to enable the interrupt |
14 | RAM238_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 238. Write 1h to enable the interrupt |
13 | RAM237_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 237. Write 1h to enable the interrupt |
12 | RAM236_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 236. Write 1h to enable the interrupt |
11 | RAM235_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 235. Write 1h to enable the interrupt |
10 | RAM234_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 234. Write 1h to enable the interrupt |
9 | RAM233_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 233. Write 1h to enable the interrupt |
8 | RAM232_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 232. Write 1h to enable the interrupt |
7 | RAM231_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 231. Write 1h to enable the interrupt |
6 | RAM230_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 230. Write 1h to enable the interrupt |
5 | RAM229_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 229. Write 1h to enable the interrupt |
4 | RAM228_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 228. Write 1h to enable the interrupt |
3 | RAM227_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 227. Write 1h to enable the interrupt |
2 | RAM226_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 226. Write 1h to enable the interrupt |
1 | RAM225_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 225. Write 1h to enable the interrupt |
0 | RAM224_ENABLE_SET | R/W1S | 0h | Non-correctable error interrupt enable for ECC endpoint with ID = 224. Write 1h to enable the interrupt |
ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2696 and described in Table 12-5144.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM31_ENABLE_CLR | RAM30_ENABLE_CLR | RAM29_ENABLE_CLR | RAM28_ENABLE_CLR | RAM27_ENABLE_CLR | RAM26_ENABLE_CLR | RAM25_ENABLE_CLR | RAM24_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM23_ENABLE_CLR | RAM22_ENABLE_CLR | RAM21_ENABLE_CLR | RAM20_ENABLE_CLR | RAM19_ENABLE_CLR | RAM18_ENABLE_CLR | RAM17_ENABLE_CLR | RAM16_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM15_ENABLE_CLR | RAM14_ENABLE_CLR | RAM13_ENABLE_CLR | RAM12_ENABLE_CLR | RAM11_ENABLE_CLR | RAM10_ENABLE_CLR | RAM9_ENABLE_CLR | RAM8_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM7_ENABLE_CLR | RAM6_ENABLE_CLR | RAM5_ENABLE_CLR | RAM4_ENABLE_CLR | RAM3_ENABLE_CLR | RAM2_ENABLE_CLR | RAM1_ENABLE_CLR | RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM31_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 31. Write 1h to disable the interrupt |
30 | RAM30_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 30. Write 1h to disable the interrupt |
29 | RAM29_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 29. Write 1h to disable the interrupt |
28 | RAM28_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 28. Write 1h to disable the interrupt |
27 | RAM27_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 27. Write 1h to disable the interrupt |
26 | RAM26_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 26. Write 1h to disable the interrupt |
25 | RAM25_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 25. Write 1h to disable the interrupt |
24 | RAM24_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 24. Write 1h to disable the interrupt |
23 | RAM23_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 23. Write 1h to disable the interrupt |
22 | RAM22_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 22. Write 1h to disable the interrupt |
21 | RAM21_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 21. Write 1h to disable the interrupt |
20 | RAM20_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 20. Write 1h to disable the interrupt |
19 | RAM19_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 19. Write 1h to disable the interrupt |
18 | RAM18_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 18. Write 1h to disable the interrupt |
17 | RAM17_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 17. Write 1h to disable the interrupt |
16 | RAM16_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 16. Write 1h to disable the interrupt |
15 | RAM15_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 15. Write 1h to disable the interrupt |
14 | RAM14_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 14. Write 1h to disable the interrupt |
13 | RAM13_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 13. Write 1h to disable the interrupt |
12 | RAM12_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 12. Write 1h to disable the interrupt |
11 | RAM11_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 11. Write 1h to disable the interrupt |
10 | RAM10_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 10. Write 1h to disable the interrupt |
9 | RAM9_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 9. Write 1h to disable the interrupt |
8 | RAM8_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 8. Write 1h to disable the interrupt |
7 | RAM7_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 7. Write 1h to disable the interrupt |
6 | RAM6_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 6. Write 1h to disable the interrupt |
5 | RAM5_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 5. Write 1h to disable the interrupt |
4 | RAM4_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 4. Write 1h to disable the interrupt |
3 | RAM3_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 3. Write 1h to disable the interrupt |
2 | RAM2_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 2. Write 1h to disable the interrupt |
1 | RAM1_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 1. Write 1h to disable the interrupt |
0 | RAM0_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 0. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG1 is shown in Figure 12-2697 and described in Table 12-5145.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM63_ENABLE_CLR | RAM62_ENABLE_CLR | RAM61_ENABLE_CLR | RAM60_ENABLE_CLR | RAM59_ENABLE_CLR | RAM58_ENABLE_CLR | RAM57_ENABLE_CLR | RAM56_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM55_ENABLE_CLR | RAM54_ENABLE_CLR | RAM53_ENABLE_CLR | RAM52_ENABLE_CLR | RAM51_ENABLE_CLR | RAM50_ENABLE_CLR | RAM49_ENABLE_CLR | RAM48_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM47_ENABLE_CLR | RAM46_ENABLE_CLR | RAM45_ENABLE_CLR | RAM44_ENABLE_CLR | RAM43_ENABLE_CLR | RAM42_ENABLE_CLR | RAM41_ENABLE_CLR | RAM40_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM39_ENABLE_CLR | RAM38_ENABLE_CLR | RAM37_ENABLE_CLR | RAM36_ENABLE_CLR | RAM35_ENABLE_CLR | RAM34_ENABLE_CLR | RAM33_ENABLE_CLR | RAM32_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM63_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 63. Write 1h to disable the interrupt |
30 | RAM62_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 62. Write 1h to disable the interrupt |
29 | RAM61_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 61. Write 1h to disable the interrupt |
28 | RAM60_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 60. Write 1h to disable the interrupt |
27 | RAM59_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 59. Write 1h to disable the interrupt |
26 | RAM58_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 58. Write 1h to disable the interrupt |
25 | RAM57_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 57. Write 1h to disable the interrupt |
24 | RAM56_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 56. Write 1h to disable the interrupt |
23 | RAM55_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 55. Write 1h to disable the interrupt |
22 | RAM54_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 54. Write 1h to disable the interrupt |
21 | RAM53_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 53. Write 1h to disable the interrupt |
20 | RAM52_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 52. Write 1h to disable the interrupt |
19 | RAM51_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 51. Write 1h to disable the interrupt |
18 | RAM50_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 50. Write 1h to disable the interrupt |
17 | RAM49_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 49. Write 1h to disable the interrupt |
16 | RAM48_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 48. Write 1h to disable the interrupt |
15 | RAM47_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 47. Write 1h to disable the interrupt |
14 | RAM46_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 46. Write 1h to disable the interrupt |
13 | RAM45_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 45. Write 1h to disable the interrupt |
12 | RAM44_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 44. Write 1h to disable the interrupt |
11 | RAM43_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 43. Write 1h to disable the interrupt |
10 | RAM42_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 42. Write 1h to disable the interrupt |
9 | RAM41_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 41. Write 1h to disable the interrupt |
8 | RAM40_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 40. Write 1h to disable the interrupt |
7 | RAM39_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 39. Write 1h to disable the interrupt |
6 | RAM38_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 38. Write 1h to disable the interrupt |
5 | RAM37_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 37. Write 1h to disable the interrupt |
4 | RAM36_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 36. Write 1h to disable the interrupt |
3 | RAM35_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 35. Write 1h to disable the interrupt |
2 | RAM34_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 34. Write 1h to disable the interrupt |
1 | RAM33_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 33. Write 1h to disable the interrupt |
0 | RAM32_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 32. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG2 is shown in Figure 12-2698 and described in Table 12-5146.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM95_ENABLE_CLR | RAM94_ENABLE_CLR | RAM93_ENABLE_CLR | RAM92_ENABLE_CLR | RAM91_ENABLE_CLR | RAM90_ENABLE_CLR | RAM89_ENABLE_CLR | RAM88_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM87_ENABLE_CLR | RAM86_ENABLE_CLR | RAM85_ENABLE_CLR | RAM84_ENABLE_CLR | RAM83_ENABLE_CLR | RAM82_ENABLE_CLR | RAM81_ENABLE_CLR | RAM80_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM79_ENABLE_CLR | RAM78_ENABLE_CLR | RAM77_ENABLE_CLR | RAM76_ENABLE_CLR | RAM75_ENABLE_CLR | RAM74_ENABLE_CLR | RAM73_ENABLE_CLR | RAM72_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM71_ENABLE_CLR | RAM70_ENABLE_CLR | RAM69_ENABLE_CLR | RAM68_ENABLE_CLR | RAM67_ENABLE_CLR | RAM66_ENABLE_CLR | RAM65_ENABLE_CLR | RAM64_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM95_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 95. Write 1h to disable the interrupt |
30 | RAM94_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 94. Write 1h to disable the interrupt |
29 | RAM93_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 93. Write 1h to disable the interrupt |
28 | RAM92_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 92. Write 1h to disable the interrupt |
27 | RAM91_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 91. Write 1h to disable the interrupt |
26 | RAM90_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 90. Write 1h to disable the interrupt |
25 | RAM89_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 89. Write 1h to disable the interrupt |
24 | RAM88_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 88. Write 1h to disable the interrupt |
23 | RAM87_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 87. Write 1h to disable the interrupt |
22 | RAM86_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 86. Write 1h to disable the interrupt |
21 | RAM85_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 85. Write 1h to disable the interrupt |
20 | RAM84_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 84. Write 1h to disable the interrupt |
19 | RAM83_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 83. Write 1h to disable the interrupt |
18 | RAM82_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 82. Write 1h to disable the interrupt |
17 | RAM81_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 81. Write 1h to disable the interrupt |
16 | RAM80_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 80. Write 1h to disable the interrupt |
15 | RAM79_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 79. Write 1h to disable the interrupt |
14 | RAM78_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 78. Write 1h to disable the interrupt |
13 | RAM77_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 77. Write 1h to disable the interrupt |
12 | RAM76_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 76. Write 1h to disable the interrupt |
11 | RAM75_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 75. Write 1h to disable the interrupt |
10 | RAM74_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 74. Write 1h to disable the interrupt |
9 | RAM73_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 73. Write 1h to disable the interrupt |
8 | RAM72_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 72. Write 1h to disable the interrupt |
7 | RAM71_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 71. Write 1h to disable the interrupt |
6 | RAM70_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 70. Write 1h to disable the interrupt |
5 | RAM69_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 69. Write 1h to disable the interrupt |
4 | RAM68_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 68. Write 1h to disable the interrupt |
3 | RAM67_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 67. Write 1h to disable the interrupt |
2 | RAM66_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 66. Write 1h to disable the interrupt |
1 | RAM65_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 65. Write 1h to disable the interrupt |
0 | RAM64_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 64. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG3 is shown in Figure 12-2699 and described in Table 12-5147.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM127_ENABLE_CLR | RAM126_ENABLE_CLR | RAM125_ENABLE_CLR | RAM124_ENABLE_CLR | RAM123_ENABLE_CLR | RAM122_ENABLE_CLR | RAM121_ENABLE_CLR | RAM120_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM119_ENABLE_CLR | RAM118_ENABLE_CLR | RAM117_ENABLE_CLR | RAM116_ENABLE_CLR | RAM115_ENABLE_CLR | RAM114_ENABLE_CLR | RAM113_ENABLE_CLR | RAM112_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM111_ENABLE_CLR | RAM110_ENABLE_CLR | RAM109_ENABLE_CLR | RAM108_ENABLE_CLR | RAM107_ENABLE_CLR | RAM106_ENABLE_CLR | RAM105_ENABLE_CLR | RAM104_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM103_ENABLE_CLR | RAM102_ENABLE_CLR | RAM101_ENABLE_CLR | RAM100_ENABLE_CLR | RAM99_ENABLE_CLR | RAM98_ENABLE_CLR | RAM97_ENABLE_CLR | RAM96_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM127_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 127. Write 1h to disable the interrupt |
30 | RAM126_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 126. Write 1h to disable the interrupt |
29 | RAM125_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 125. Write 1h to disable the interrupt |
28 | RAM124_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 124. Write 1h to disable the interrupt |
27 | RAM123_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 123. Write 1h to disable the interrupt |
26 | RAM122_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 122. Write 1h to disable the interrupt |
25 | RAM121_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 121. Write 1h to disable the interrupt |
24 | RAM120_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 120. Write 1h to disable the interrupt |
23 | RAM119_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 119. Write 1h to disable the interrupt |
22 | RAM118_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 118. Write 1h to disable the interrupt |
21 | RAM117_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 117. Write 1h to disable the interrupt |
20 | RAM116_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 116. Write 1h to disable the interrupt |
19 | RAM115_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 115. Write 1h to disable the interrupt |
18 | RAM114_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 114. Write 1h to disable the interrupt |
17 | RAM113_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 113. Write 1h to disable the interrupt |
16 | RAM112_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 112. Write 1h to disable the interrupt |
15 | RAM111_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 111. Write 1h to disable the interrupt |
14 | RAM110_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 110. Write 1h to disable the interrupt |
13 | RAM109_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 109. Write 1h to disable the interrupt |
12 | RAM108_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 108. Write 1h to disable the interrupt |
11 | RAM107_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 107. Write 1h to disable the interrupt |
10 | RAM106_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 106. Write 1h to disable the interrupt |
9 | RAM105_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 105. Write 1h to disable the interrupt |
8 | RAM104_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 104. Write 1h to disable the interrupt |
7 | RAM103_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 103. Write 1h to disable the interrupt |
6 | RAM102_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 102. Write 1h to disable the interrupt |
5 | RAM101_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 101. Write 1h to disable the interrupt |
4 | RAM100_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 100. Write 1h to disable the interrupt |
3 | RAM99_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 99. Write 1h to disable the interrupt |
2 | RAM98_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 98. Write 1h to disable the interrupt |
1 | RAM97_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 97. Write 1h to disable the interrupt |
0 | RAM96_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 96. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG4 is shown in Figure 12-2700 and described in Table 12-5148.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM159_ENABLE_CLR | RAM158_ENABLE_CLR | RAM157_ENABLE_CLR | RAM156_ENABLE_CLR | RAM155_ENABLE_CLR | RAM154_ENABLE_CLR | RAM153_ENABLE_CLR | RAM152_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM151_ENABLE_CLR | RAM150_ENABLE_CLR | RAM149_ENABLE_CLR | RAM148_ENABLE_CLR | RAM147_ENABLE_CLR | RAM146_ENABLE_CLR | RAM145_ENABLE_CLR | RAM144_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM143_ENABLE_CLR | RAM142_ENABLE_CLR | RAM141_ENABLE_CLR | RAM140_ENABLE_CLR | RAM139_ENABLE_CLR | RAM138_ENABLE_CLR | RAM137_ENABLE_CLR | RAM136_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM135_ENABLE_CLR | RAM134_ENABLE_CLR | RAM133_ENABLE_CLR | RAM132_ENABLE_CLR | RAM131_ENABLE_CLR | RAM130_ENABLE_CLR | RAM129_ENABLE_CLR | RAM128_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM159_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 159. Write 1h to disable the interrupt |
30 | RAM158_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 158. Write 1h to disable the interrupt |
29 | RAM157_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 157. Write 1h to disable the interrupt |
28 | RAM156_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 156. Write 1h to disable the interrupt |
27 | RAM155_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 155. Write 1h to disable the interrupt |
26 | RAM154_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 154. Write 1h to disable the interrupt |
25 | RAM153_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 153. Write 1h to disable the interrupt |
24 | RAM152_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 152. Write 1h to disable the interrupt |
23 | RAM151_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 151. Write 1h to disable the interrupt |
22 | RAM150_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 150. Write 1h to disable the interrupt |
21 | RAM149_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 149. Write 1h to disable the interrupt |
20 | RAM148_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 148. Write 1h to disable the interrupt |
19 | RAM147_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 147. Write 1h to disable the interrupt |
18 | RAM146_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 146. Write 1h to disable the interrupt |
17 | RAM145_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 145. Write 1h to disable the interrupt |
16 | RAM144_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 144. Write 1h to disable the interrupt |
15 | RAM143_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 143. Write 1h to disable the interrupt |
14 | RAM142_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 142. Write 1h to disable the interrupt |
13 | RAM141_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 141. Write 1h to disable the interrupt |
12 | RAM140_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 140. Write 1h to disable the interrupt |
11 | RAM139_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 139. Write 1h to disable the interrupt |
10 | RAM138_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 138. Write 1h to disable the interrupt |
9 | RAM137_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 137. Write 1h to disable the interrupt |
8 | RAM136_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 136. Write 1h to disable the interrupt |
7 | RAM135_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 135. Write 1h to disable the interrupt |
6 | RAM134_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 134. Write 1h to disable the interrupt |
5 | RAM133_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 133. Write 1h to disable the interrupt |
4 | RAM132_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 132. Write 1h to disable the interrupt |
3 | RAM131_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 131. Write 1h to disable the interrupt |
2 | RAM130_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 130. Write 1h to disable the interrupt |
1 | RAM129_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 129. Write 1h to disable the interrupt |
0 | RAM128_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 128. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG5 is shown in Figure 12-2701 and described in Table 12-5149.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM191_ENABLE_CLR | RAM190_ENABLE_CLR | RAM189_ENABLE_CLR | RAM188_ENABLE_CLR | RAM187_ENABLE_CLR | RAM186_ENABLE_CLR | RAM185_ENABLE_CLR | RAM184_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM183_ENABLE_CLR | RAM182_ENABLE_CLR | RAM181_ENABLE_CLR | RAM180_ENABLE_CLR | RAM179_ENABLE_CLR | RAM178_ENABLE_CLR | RAM177_ENABLE_CLR | RAM176_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM175_ENABLE_CLR | RAM174_ENABLE_CLR | RAM173_ENABLE_CLR | RAM172_ENABLE_CLR | RAM171_ENABLE_CLR | RAM170_ENABLE_CLR | RAM169_ENABLE_CLR | RAM168_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM167_ENABLE_CLR | RAM166_ENABLE_CLR | RAM165_ENABLE_CLR | RAM164_ENABLE_CLR | RAM163_ENABLE_CLR | RAM162_ENABLE_CLR | RAM161_ENABLE_CLR | RAM160_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM191_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 191. Write 1h to disable the interrupt |
30 | RAM190_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 190. Write 1h to disable the interrupt |
29 | RAM189_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 189. Write 1h to disable the interrupt |
28 | RAM188_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 188. Write 1h to disable the interrupt |
27 | RAM187_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 187. Write 1h to disable the interrupt |
26 | RAM186_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 186. Write 1h to disable the interrupt |
25 | RAM185_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 185. Write 1h to disable the interrupt |
24 | RAM184_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 184. Write 1h to disable the interrupt |
23 | RAM183_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 183. Write 1h to disable the interrupt |
22 | RAM182_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 182. Write 1h to disable the interrupt |
21 | RAM181_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 181. Write 1h to disable the interrupt |
20 | RAM180_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 180. Write 1h to disable the interrupt |
19 | RAM179_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 179. Write 1h to disable the interrupt |
18 | RAM178_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 178. Write 1h to disable the interrupt |
17 | RAM177_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 177. Write 1h to disable the interrupt |
16 | RAM176_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 176. Write 1h to disable the interrupt |
15 | RAM175_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 175. Write 1h to disable the interrupt |
14 | RAM174_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 174. Write 1h to disable the interrupt |
13 | RAM173_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 173. Write 1h to disable the interrupt |
12 | RAM172_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 172. Write 1h to disable the interrupt |
11 | RAM171_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 171. Write 1h to disable the interrupt |
10 | RAM170_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 170. Write 1h to disable the interrupt |
9 | RAM169_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 169. Write 1h to disable the interrupt |
8 | RAM168_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 168. Write 1h to disable the interrupt |
7 | RAM167_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 167. Write 1h to disable the interrupt |
6 | RAM166_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 166. Write 1h to disable the interrupt |
5 | RAM165_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 165. Write 1h to disable the interrupt |
4 | RAM164_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 164. Write 1h to disable the interrupt |
3 | RAM163_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 163. Write 1h to disable the interrupt |
2 | RAM162_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 162. Write 1h to disable the interrupt |
1 | RAM161_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 161. Write 1h to disable the interrupt |
0 | RAM160_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 160. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG6 is shown in Figure 12-2702 and described in Table 12-5150.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM223_ENABLE_CLR | RAM222_ENABLE_CLR | RAM221_ENABLE_CLR | RAM220_ENABLE_CLR | RAM219_ENABLE_CLR | RAM218_ENABLE_CLR | RAM217_ENABLE_CLR | RAM216_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM215_ENABLE_CLR | RAM214_ENABLE_CLR | RAM213_ENABLE_CLR | RAM212_ENABLE_CLR | RAM211_ENABLE_CLR | RAM210_ENABLE_CLR | RAM209_ENABLE_CLR | RAM208_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM207_ENABLE_CLR | RAM206_ENABLE_CLR | RAM205_ENABLE_CLR | RAM204_ENABLE_CLR | RAM203_ENABLE_CLR | RAM202_ENABLE_CLR | RAM201_ENABLE_CLR | RAM200_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM199_ENABLE_CLR | RAM198_ENABLE_CLR | RAM197_ENABLE_CLR | RAM196_ENABLE_CLR | RAM195_ENABLE_CLR | RAM194_ENABLE_CLR | RAM193_ENABLE_CLR | RAM192_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM223_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 223. Write 1h to disable the interrupt |
30 | RAM222_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 222. Write 1h to disable the interrupt |
29 | RAM221_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 221. Write 1h to disable the interrupt |
28 | RAM220_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 220. Write 1h to disable the interrupt |
27 | RAM219_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 219. Write 1h to disable the interrupt |
26 | RAM218_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 218. Write 1h to disable the interrupt |
25 | RAM217_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 217. Write 1h to disable the interrupt |
24 | RAM216_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 216. Write 1h to disable the interrupt |
23 | RAM215_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 215. Write 1h to disable the interrupt |
22 | RAM214_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 214. Write 1h to disable the interrupt |
21 | RAM213_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 213. Write 1h to disable the interrupt |
20 | RAM212_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 212. Write 1h to disable the interrupt |
19 | RAM211_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 211. Write 1h to disable the interrupt |
18 | RAM210_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 210. Write 1h to disable the interrupt |
17 | RAM209_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 209. Write 1h to disable the interrupt |
16 | RAM208_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 208. Write 1h to disable the interrupt |
15 | RAM207_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 207. Write 1h to disable the interrupt |
14 | RAM206_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 206. Write 1h to disable the interrupt |
13 | RAM205_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 205. Write 1h to disable the interrupt |
12 | RAM204_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 204. Write 1h to disable the interrupt |
11 | RAM203_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 203. Write 1h to disable the interrupt |
10 | RAM202_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 202. Write 1h to disable the interrupt |
9 | RAM201_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 201. Write 1h to disable the interrupt |
8 | RAM200_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 200. Write 1h to disable the interrupt |
7 | RAM199_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 199. Write 1h to disable the interrupt |
6 | RAM198_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 198. Write 1h to disable the interrupt |
5 | RAM197_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 197. Write 1h to disable the interrupt |
4 | RAM196_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 196. Write 1h to disable the interrupt |
3 | RAM195_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 195. Write 1h to disable the interrupt |
2 | RAM194_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 194. Write 1h to disable the interrupt |
1 | RAM193_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 193. Write 1h to disable the interrupt |
0 | RAM192_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 192. Write 1h to disable the interrupt |
ECC_DED_ENABLE_CLR_REG7 is shown in Figure 12-2703 and described in Table 12-5151.
Return to Summary Table.
Interrupt disable register for non-correctable error. Each bit corresponds to an ECC endpoint. Depending on the number of ECC endpoints associated with a module or subsystem some of the bits may not be used.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RAM255_ENABLE_CLR | RAM254_ENABLE_CLR | RAM253_ENABLE_CLR | RAM252_ENABLE_CLR | RAM251_ENABLE_CLR | RAM250_ENABLE_CLR | RAM249_ENABLE_CLR | RAM248_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RAM247_ENABLE_CLR | RAM246_ENABLE_CLR | RAM245_ENABLE_CLR | RAM244_ENABLE_CLR | RAM243_ENABLE_CLR | RAM242_ENABLE_CLR | RAM241_ENABLE_CLR | RAM240_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAM239_ENABLE_CLR | RAM238_ENABLE_CLR | RAM237_ENABLE_CLR | RAM236_ENABLE_CLR | RAM235_ENABLE_CLR | RAM234_ENABLE_CLR | RAM233_ENABLE_CLR | RAM232_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAM231_ENABLE_CLR | RAM230_ENABLE_CLR | RAM229_ENABLE_CLR | RAM228_ENABLE_CLR | RAM227_ENABLE_CLR | RAM226_ENABLE_CLR | RAM225_ENABLE_CLR | RAM224_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RAM255_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 255. Write 1h to disable the interrupt |
30 | RAM254_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 254. Write 1h to disable the interrupt |
29 | RAM253_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 253. Write 1h to disable the interrupt |
28 | RAM252_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 252. Write 1h to disable the interrupt |
27 | RAM251_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 251. Write 1h to disable the interrupt |
26 | RAM250_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 250. Write 1h to disable the interrupt |
25 | RAM249_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 249. Write 1h to disable the interrupt |
24 | RAM248_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 248. Write 1h to disable the interrupt |
23 | RAM247_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 247. Write 1h to disable the interrupt |
22 | RAM246_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 246. Write 1h to disable the interrupt |
21 | RAM245_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 245. Write 1h to disable the interrupt |
20 | RAM244_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 244. Write 1h to disable the interrupt |
19 | RAM243_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 243. Write 1h to disable the interrupt |
18 | RAM242_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 242. Write 1h to disable the interrupt |
17 | RAM241_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 241. Write 1h to disable the interrupt |
16 | RAM240_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 240. Write 1h to disable the interrupt |
15 | RAM239_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 239. Write 1h to disable the interrupt |
14 | RAM238_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 238. Write 1h to disable the interrupt |
13 | RAM237_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 237. Write 1h to disable the interrupt |
12 | RAM236_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 236. Write 1h to disable the interrupt |
11 | RAM235_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 235. Write 1h to disable the interrupt |
10 | RAM234_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 234. Write 1h to disable the interrupt |
9 | RAM233_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 233. Write 1h to disable the interrupt |
8 | RAM232_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 232. Write 1h to disable the interrupt |
7 | RAM231_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 231. Write 1h to disable the interrupt |
6 | RAM230_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 230. Write 1h to disable the interrupt |
5 | RAM229_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 229. Write 1h to disable the interrupt |
4 | RAM228_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 228. Write 1h to disable the interrupt |
3 | RAM227_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 227. Write 1h to disable the interrupt |
2 | RAM226_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 226. Write 1h to disable the interrupt |
1 | RAM225_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 225. Write 1h to disable the interrupt |
0 | RAM224_ENABLE_CLR | R/W1C | 0h | Non-correctable error interrupt disable for ECC endpoint with ID = 224. Write 1h to disable the interrupt |
ECC_AGGR_ENABLE_SET is shown in Figure 12-2704 and described in Table 12-5152.
Return to Summary Table.
Aggregator Interrupt Enable Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for ECC serial interface timeout errors. Write 1h to enable timeout errors. |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors. Write 1h to enable parity errors. |
ECC_AGGR_ENABLE_CLR is shown in Figure 12-2705 and described in Table 12-5153.
Return to Summary Table.
Aggregator Interrupt Enable Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0 | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt disable for ECC serial interface timeout errors. Write 1h to disable timeout errors. |
0 | PARITY | R/W1C | 0h | Interrupt disable for parity errors. Write 1h to disable parity errors. |
ECC_AGGR_STATUS_SET is shown in Figure 12-2706 and described in Table 12-5154.
Return to Summary Table.
Aggregator Interrupt Status Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0 | Reserved |
3-2 | TIMEOUT | R/W | 0h | 2-bit saturating counter for the number of timeout errors that have occurred since last cleared. A write of a non-zero value to this register incrments that many from the timeout fields. If the value written is less than the current value of the counter, then the pending level interrupt stays asserted. If this field goes from 0h to non-zero value a level interrupt is asserted. If the value is non-zero then the interrupt remains asserted. 0h - No timeout errors have occurred 1h - 1 timeout error has occurred 2h - 2 timeout errors have occurred 3h - 3 or more timeout error have occurred |
1-0 | PARITY | R/W | 0h | 2-bit saturating counter for the number of parity errors that have occurred since last cleared. A write of a non-zero value to this field increments that many from the parity fields. If the value written is less than the current value of the counter, then the pending level interrupt stays asserted. If this field goes from 0h to non-zero value a level interrupt is asserted. If the value is non-zero then the interrupt remains asserted. 0h - No parity errors have occurred 1h - 1 parity error has occurred 2h - 2 parity errors have occurred 3h - 3 or more parity errors have occurred |
ECC_AGGR_STATUS_CLR is shown in Figure 12-2707 and described in Table 12-5155.
Return to Summary Table.
Aggregator Interrupt Status Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0 | Reserved |
3-2 | TIMEOUT | R/W | 0h | Interrupt status clear for ECC serial interface timeout errors. A write of a non-zero value to this register decrements that many from the timeout fields. If the resulting value is not zero, then the pending level interrupt stays asserted. If the value written is more than the counter value, then the result is zero. 0h - No timeout errors have occurred 1h - 1 timeout error has occurred 2h - 2 timeout errors have occurred 3h - 3 or more timeout error have occurred |
1-0 | PARITY | R/W | 0h | Interrupt status clear for parity errors. A write of a non-zero value to this register decrements that many from the parity fields. If the resulting value is not zero, then the pending level interrupt stays asserted. If the value written is more than the counter value, then the result is zero. 0h - No parity errors have occurred 1h - 1 parity error has occurred 2h - 2 parity errors have occurred 3h - 3 or more parity errors have occurred |