SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This reset is a MAIN domain warm reset that is executed from the DMSC-L.
This is an asynchronous reset type (takes effect immediately).
This reset behavior is same as MAIN_RESETz_REQ reset signal (RESET_REQz HW Pin).
Entire MCU domain is reset isolated.
MCU IOs are not effected.
This is a MAIN domain reset request. First, the reset isolation sequence is applied and then the reset is propagated.
All modules in MAIN domain are reset except for modules and MAIN domain CTRLMMR register bits which are reset only on MAIN_PORz.
IOs are not effected.
All processor cores are reset (A53SS, DMSC-L, and R5FSS).
Reason for this reset is captured in CTRLMMR reset source status register CTRLMMR_RST_SRC. After reset is de-asserted, device will boot-up. During device boot-up, R5FSS (secondary boot loader) will read the reset status and MCU ACTIVE MAGIC WORD registers and reconfigure the MCU domain/M4FSS processor accordingly.