SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-1754 lists the PRU_ICSSG_PA_STAT registers. All register offset addresses not listed in Table 6-1754 should be considered as reserved locations and the register contents should not be modified.
Control registers
Instance | Base Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C000h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C000h |
Offset | Acronym | Register Name | PRU_ICSSG0_PA_STAT_WRAP_PA_SLV Physical Address |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV Physical Address |
---|---|---|---|---|
0h | ICSSG_PA_STAT_REVID | Revision Register | 3003 C000h | 300B C000h |
4h | ICSSG_PA_STAT_SRESET | Soft Reset Register | 3003 C004h | 300B C004h |
8h | ICSSG_PA_STAT_EAC | Enable and Allocation Control Register | 3003 C008h | 300B C008h |
10h | ICSSG_PA_STAT_TCTL | Timer Control Register | 3003 C010h | 300B C010h |
14h | ICSSG_PA_STAT_TLD | Timer Load Register | 3003 C014h | 300B C014h |
18h | ICSSG_PA_STAT_TVL | Timer Value Register | 3003 C018h | 300B C018h |
ICSSG_PA_STAT_REVID is shown in Figure 6-881 and described in Table 6-1756.
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The Revision Register contains the ID and revision information.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C000h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVID | |||||||||||||||||||||||||||||||
R-0EF50100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVID | R | 0EF50100h | Module ID and revision information. |
ICSSG_PA_STAT_SRESET is shown in Figure 6-882 and described in Table 6-1758.
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The Soft Reset Register is written in order to clear the contents of all statistics.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C004h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGGER | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TRIGGER | W | 0h | Writing anything to this field causes the command FIFOs to be emptied, all statistics to be cleared and all bit masks to be reset to 1. The write to this register will be acknowledged (wready will be asserted) after the reset process is completed. |
ICSSG_PA_STAT_EAC is shown in Figure 6-883 and described in Table 6-1760.
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The register contains the enable for the engine and controls the allocation of 64-bit counters in the memory. It is possible to configure the engine to only have 32-bit counters by setting the 64-bit cnt field to zero.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C008h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CNT | ||||||
R/W-X | R/W-200h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT | |||||||
R/W-200h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | Enables stat engine. If the module is not in enabled state, no stats increment is processed and both input and output streaming interfaces are disabled. |
30-14 | RESERVED | R/W | X | Always read as 0. Writes have no effect. |
13-0 | CNT | R/W | 200h | Defines the number of 64-bit counters in the memory (must be even number). If this number multiplied by 8-byte is less than 4 KB (stats memory space), then the remaining space is allocated for 32-bit counters. |
ICSSG_PA_STAT_TCTL is shown in Figure 6-884 and described in Table 6-1762.
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The Control Timer Register controls a 16-bit timer.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C010h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLK_EN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRE_VAL | RESERVED | |||||
R/W-X | R/W-0h | R/W-X | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | Always read as 0. Writes have no effect. |
15 | CLK_EN | R/W | 0h | 0 = Disable prescaler 1 = Enable prescaler |
14-6 | RESERVED | R/W | X | Always read as 0. Writes have no effect. |
5-2 | PRE_VAL | R/W | 0h | 0000 Divide by 2 0001 Divide by 4 0010 Divide by 8 0011 Divide by 16 0100 Divide by 32 0101 Divide by 64 0110 Divide by 128 0111 Divide by 256 1000 Divide by 512 1001 Divide by 1024 1010 Divide by 2048 1011 Divide by 1024 1100 Divide by 8192 1101 Disable timer 1110 Disable timer 1111 Disable timer |
1-0 | RESERVED | R/W | X | Always read as 0. Writes have no effect. |
ICSSG_PA_STAT_TLD is shown in Figure 6-885 and described in Table 6-1764.
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The Load Timer Register contains the starting count down value for the 16-bit timer. This register should be written with some value before the timer is started by write on the timer control register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C014h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOAD_VAL | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | Always read as 0. Writes have no effect. |
15-0 | LOAD_VAL | R/W | 0h | 16-bit timer value. |
ICSSG_PA_STAT_TVL is shown in Figure 6-886 and described in Table 6-1766.
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The Timer Value Register contains the current value of the timer.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV | 3003 C018h |
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV | 300B C018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CUR_VAL | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | Always read as 0. Writes have no effect. |
15-0 | CUR_VAL | R | 0h | Current value of the 16-bit timer. |