SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 11-703 lists the PDMA PSI-L TX configuration registers (PDMA_PSILCFG_TX). These registers are not memory mapped and are accessed indirectly via CFG_PROXY modules in DMSS.
Instance | Base Address |
---|---|
PDMA_PSILCFG_TX | N/A |
Offset | Acronym | Register Name | PDMA_PSILCFG_TX Physical Address |
---|---|---|---|
2h | PDMA_PSILCFG_TX_ENABLE | TX enable register | N/A |
40h | PDMA_PSILCFG_TX_CAPABILITIES | TX local capabilities register | N/A |
400h | PDMA_PSILCFG_TX_STATIC_TR | TX static transfer request (X, Y) register | N/A |
402h | PDMA_PSILCFG_TX_DEBUG_1 | TX debug/state register 1 | N/A |
403h | PDMA_PSILCFG_TX_DEBUG_2 | TX debug/state register 2 | N/A |
404h | PDMA_PSILCFG_TX_BYTE_COUNT | TX byte count register | N/A |
PDMA_PSILCFG_TX_ENABLE is shown in Figure 11-299 and described in Table 11-705.
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Enable Register. This register contains enable control for the thread.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | When set, the TX channel is enabled. When cleared, the TX channel is disabled. When disabled, the channel discards all ingress data. A one-to-zero transition on this bit fully resets the channel. |
30-0 | RESERVED | R | 0h | Reserved |
PDMA_PSILCFG_TX_CAPABILITIES is shown in Figure 11-300 and described in Table 11-707.
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Local Capabilities Register. This register provides the width and count of the credits for which buffering is available in the local thread. This register can be read by the system configuration software to determine what values to place in the following registers of the source paired thread:
This register is only implemented for destination threads.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | LOCAL_THREAD_WIDTH | ||||||
R-0h | R-2h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCAL_CREDIT_CNT | |||||||
R-8h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | Reserved |
28-24 | LOCAL_THREAD_WIDTH | R | 2h | Read-only element width for the local thread used for pairing purposes. 0h = 4 bytes 1h = 8 bytes 2h = 16 bytes 3h to 1Fh = Reserved |
23-8 | RESERVED | R | 0h | Reserved |
7-0 | LOCAL_CREDIT_CNT | R | 7h | Read-only local thread free entry count used for pairing purposes. This field is encoded as follows: 0h to 80h = Available count in elements 81h to FFh = Reserved |
PDMA_PSILCFG_TX_STATIC_TR is shown in Figure 11-301 and described in Table 11-709.
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Static Transfer Request (X, Y) Register. This register is used to define the 'X' and 'Y' parameters in a static TR.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BURST | ACC32 | RESERVED | X | ||||
R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | Y | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Y | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BURST | R/W | 0h | X-Y FIFO mode static TR: When set, enables VBUSP burst mode on this channel. See the XY burst description for more information. |
MCAN mode static TR: When set, enables VBUSP burst mode on this channel. See the MCAN burst description for more information. | ||||
AASRC mode static TR: Not used. | ||||
30 | ACC32 | R/W | 0h | X-Y FIFO mode static TR: When set, enables 32-bit access mode. On a 32-bit PDMA, all accesses will have XCNT=4 to support legacy IP that is not fully VBUSP compliant. This bit is ignored if the PDMA VBUSP port is not 32 bits wide. |
MCAN mode static TR: Not used. | ||||
AASRC mode static TR: When set, enables 32-bit access mode. On a 32-bit PDMA, all accesses will have XCNT=4 to support legacy IP that is not fully VBUSP compliant. This bit is ignored if the PDMA VBUSP port is not 32 bits wide. | ||||
29-27 | RESERVED | R | 0h | Reserved |
26-24 | X | R/W | 0h | X-Y FIFO mode static TR: Element size. This field specifies how much data is transferred in each write which is performed by the DMA. This field is encoded as follows: 0h = 8 bits; 1h =16 bits; 2h = 24 bits; 3h = 32 bits; 4h = 64 bits; 5h-7h = RESERVED. |
MCAN mode static TR: Not used. | ||||
AASRC mode static TR: Element size. This field specifies how much data is transferred in each write which is performed by the DMA. This field is encoded as follows: 0h = 8 bits; 1h =16 bits; 2h = 24 bits; 3h = 32 bits; 4h = 64 bits; 5h-7h = RESERVED. | ||||
23-12 | RESERVED | R | 0h | Reserved |
11-0 | Y | R/W | 0h | X-Y FIFO mode static TR: Element count. This field specifies how many elements to transfer each time a trigger is received on the channel. |
MCAN mode static TR: Buffer Size. This field specifies how many bytes should be written to an MCAN TX buffer. This field includes the 8-byte MCAN header on the initial packet fragment. The PDMA will break up the source packet into fragments of this buffer size, copying the 8-byte MCAN header for the initial fragment, and then skipping it for each additional fragment and thus reusing the header from the first fragment. A buffer size less than 16 is treated as 16, and a buffer size greater than 72 is treated as 72. | ||||
AASRC mode static TR: FIFO element count. In AASRC mode, a channel can service multiple FIFOs using a list supplied in its FIFO configuration. This field specifies how many times to service the FIFO list, hence how many elements to transfer from each FIFO, each time a trigger is received on the channel. Note for each loop specified by the value of Y, the entire list is processed. For example, if the FIFO list is 0, 1, 2, 3, and Y is set to 2 loops, the FIFOs are serviced in the order: 0, 1, 2, 3, 0, 1, 2, 3. |
PDMA_PSILCFG_TX_DEBUG_1 is shown in Figure 11-302 and described in Table 11-711.
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Debug/State Register 1. The debug/state registers give software applications additional information about the PDMA than they would need in regular opteration, but which may be useful in debug situations.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESEREVD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Y | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Y | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | Y | R/W | 0h | This field holds the current Y count. In X-Y FIFO mode, this is the number of X sized samples yet to write to the peripheral for the DMA event being serviced. In MCAN mode, this field holds the next write offset to use when writing to the CAN TX buffer. |
PDMA_PSILCFG_TX_DEBUG_2 is shown in Figure 11-303 and described in Table 11-713.
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Debug/State Register 2. The debug/state registers give software applications additional information about the PDMA than they would need in regular opteration, but which may be useful in debug situations.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INEVENT | FLUSH | PAUSE | DATA | XDATA | RESERVED | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STATE | EVENTCNT | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INEVENT | R/W | 0h | When set, the PDMA is in the middle of processing a FIFO event. |
30 | FLUSH | R/W | 0h | When set, the PDMA is processing in a flushing state, where it runs without waiting for DMA requests and without writing data to the peripheral. It is only operating its internal state machine to allow internal data pipes to drain properly. |
29 | PAUSE | R/W | 0h | When set, the PDMA waiting in a paused state. This bit will clear when data starts flowing again from the paired-DMA. |
28 | DATA | R/W | 0h | When set, there is a non-zero amount of data still waiting to be written to the peripheral. |
27 | XDATA | R/W | 0h | When set, there is enough data still waiting to be written to the peripheral to start servicing a peripheral DMA event. |
26-24 | RESERVED | R | 0h | Reserved |
23-20 | STATE | R/W | 0h | This code reflects the current state of the PDMA channel, and is specific to the current implementation. |
19-16 | EVENTCNT | R/W | 0h | This field holds the number of backlogged DMA events yet to be serviced. |
15-0 | RESERVED | R | 0h | Reserved |
PDMA_PSILCFG_TX_BYTE_COUNT is shown in Figure 11-304 and described in Table 11-715.
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Byte Count Register. This register contains the number of bytes that have been written to the VBUSP mapped peripheral.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYTES | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTES | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BYTES | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYTES | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BYTES | R/W | 0h | This register contains the number of bytes that have been read from the VBUSP mapped peripheral. The register is write-to-decrement, so running counts can be tracked by reading register and then writing back the value that was read. It will wrap on overflow. It will reset to zero on a channel reset. |
PDMA_PSILCFG_TX_RT_ENABLE is shown in Figure 11-305 and described in Figure 11-305.
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Real Time Enable Register. This register allows enabling various channel settings in real time.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_TX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | TDOWN | PAUSE | FLUSH | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERROR | IDLE | FREE | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | When set, the TX channel is enabled. When cleared, the TX channel is disabled. When disabled, it discards all held data. It clears DMA event counts and ignores all future DMA events from the peripheral. It maintains data exchange with the paired-DMA so that credit handshake is not disrupted. A 'hard teardown' can be performed by directly clearing this bit. Note that this bit cannot be changed from 0 to 1 if the global enable bit in the peer enable register is 0. |
30 | TDOWN | R/W | 0h | When set, the channel will commence a TX channel teardown procedure. To perform a TX teardown, the teardown bit should be set in the paired-DMA and it will automatically propagate to this register bit with the normal flow of peripheral data. Once the channel is fully stopped and ready to be reused (including returning all credits), the ENABLE bit is cleared. |
29 | PAUSE | R/W | 0h | When set, the channel is in a paused state. It will stop on the next FIFO boundary. It continues to accept and count DMA events from the peripherals but will not act on them. The PAUSE bit can be cleared and data will resume. |
28 | FLUSH | R/W | 0h | When set, causes all TX channel data to be discarded instead of being written to the peripheral. It essentially allows the TX engine to 'free run' without DMA requests from the peripheral (it will also override 'pause'). This bit should be set only when a channel fails to complete its teardown procedure normally because a peripheral is no longer functioning or because data flow was halted on a boundary that is not compatible with the static TR configuration. |
27-3 | RESERVED | R | 0h | Reserved |
2 | ERROR | R/W | 0h | When set, the channel has encountered a PSI-L protocol violation. The ERROR bit can only be set by hardware and can only be cleared by software. Once this bit is set, the channel should be fully reset and re-initialized via the PSI-L pairing registers. |
1 | IDLE | R | 0h | This is a read-only bit that signifies that the disabled thread is also idle. This bit is read only and can only become set if the ENABLE bit is cleared. |
0 | FREE | R/W | 0h | When cleared, the channel honors the debug suspend signal. When set, the channel will 'free run', regardless of the value of debug suspend. |