SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Host can issue read on specific counter and the read data comes from the active page. This is especially useful for debug purpose, or when the timer is disabled and the host manually reads the stats. The bit mask table has no effect on the counter on manual read. There are two register addresses for every statistics counter. One address is used for query mode (read and not clear), and another is used for collect mode (read and clear). Note that issuing two 32-bit reads through the 32-bit configuration bus for reading a 64-bit stat can be unreliable, because there may be latency between the two reads and a stat bump can occur in between. This may be unavoidable for Arm cores, but for cores that can issue burst read, such as DSPs, the statistics engine will ensure that reads on 64-bit counter value is treated as atomic operation. However, the module does not support read burst on multiple counters using collect (read and clear) mode.
When reading a 64-bit counter in collect mode through the 32-bit configuration bus, each 32-bit portion of the counter is cleared immediately after the read.