SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | VTM0 Physical Address |
---|---|---|---|---|
0h | 32 | VTM0_VTM_PID | 00B0 0000h | |
4h | 32 | VTM0_VTM_DEVINFO_PWR0 | 00B0 0004h | |
100h+ Formula | 32 | VTM0_VTM_VD_DEVINFO_j | 00B0 0100h+ Formula | |
104h+ Formula | 32 | VTM0_VTM_VD_OPPVID_j | 00B0 0104h+ Formula | |
108h+ Formula | 32 | VTM0_VTM_VD_EVT_STAT_j | 00B0 0108h+ Formula | |
10Ch+ Formula | 32 | VTM0_VTM_VD_EVT_SEL_SET_j | 00B0 010Ch+ Formula | |
110h+ Formula | 32 | VTM0_VTM_VD_EVT_SEL_CLR_j | 00B0 0110h+ Formula | |
204h | 32 | VTM0_VTM_GT_TH1_INT_RAW_STAT_SET | 00B0 0204h | |
208h | 32 | VTM0_VTM_GT_TH1_INT_EN_STAT_CLR | 00B0 0208h | |
214h | 32 | VTM0_VTM_GT_TH1_INT_EN_SET | 00B0 0214h | |
218h | 32 | VTM0_VTM_GT_TH1_INT_EN_CLR | 00B0 0218h | |
224h | 32 | VTM0_VTM_GT_TH2_INT_RAW_STAT_SET | 00B0 0224h | |
228h | 32 | VTM0_VTM_GT_TH2_INT_EN_STAT_CLR | 00B0 0228h | |
234h | 32 | VTM0_VTM_GT_TH2_INT_EN_SET | 00B0 0234h | |
238h | 32 | VTM0_VTM_GT_TH2_INT_EN_CLR | 00B0 0238h | |
244h | 32 | VTM0_VTM_LT_TH0_INT_RAW_STAT_SET | 00B0 0244h | |
248h | 32 | VTM0_VTM_LT_TH0_INT_EN_STAT_CLR | 00B0 0248h | |
254h | 32 | VTM0_VTM_LT_TH0_INT_EN_SET | 00B0 0254h | |
258h | 32 | VTM0_VTM_LT_TH0_INT_EN_CLR | 00B0 0258h | |
300h+ Formula | 32 | VTM0_VTM_TMPSENS_CTRL_j | 00B0 0300h+ Formula | |
308h+ Formula | 32 | VTM0_VTM_TMPSENS_STAT_j | 00B0 0308h+ Formula | |
30Ch+ Formula | 32 | VTM0_VTM_TMPSENS_TH_j | 00B0 030Ch+ Formula | |
310h+ Formula | 32 | VTM0_VTM_TMPSENS_TH2_j | 00B0 0310h+ Formula |
Offset | Length | Acronym | Register Name | VTM0 Physical Address |
---|---|---|---|---|
8h | 32 | VTM0_VTM_CLK_CTRL | 00B0 1008h | |
Ch | 32 | VTM0_VTM_MISC_CTRL | 00B0 100Ch | |
10h | 32 | VTM0_VTM_MISC_CTRL2 | 00B0 1010h | |
20h | 32 | VTM0_VTM_SAMPLE_CTRL | 00B0 1020h | |
300h+ Formula | 32 | VTM0_VTM_TMPSENS_CTRL_j | 00B0 1300h+ Formula | |
304h+ Formula | 32 | VTM0_VTM_TMPSENS_TRIM_j | 00B0 1304h+ Formula |
Offset | Length | Acronym | Register Name | VTM0 Physical Address |
---|---|---|---|---|
0h | 32 | VTM0_rev | Aggregator Revision Register | 00B0 2000h |
8h | 32 | VTM0_vector | ECC Vector Register | 00B0 2008h |
Ch | 32 | VTM0_stat | Misc Status | 00B0 200Ch |
10h | 32 | VTM0_reserved_svbus | Reserved Area for Serial VBUS Registers | 00B0 2010h |
3Ch | 32 | VTM0_sec_eoi_reg | EOI Register | 00B0 203Ch |
40h | 32 | VTM0_sec_status_reg0 | Interrupt Status Register 0 | 00B0 2040h |
80h | 32 | VTM0_sec_enable_set_reg0 | Interrupt Enable Set Register 0 | 00B0 2080h |
C0h | 32 | VTM0_sec_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 00B0 20C0h |
13Ch | 32 | VTM0_ded_eoi_reg | EOI Register | 00B0 213Ch |
140h | 32 | VTM0_ded_status_reg0 | Interrupt Status Register 0 | 00B0 2140h |
180h | 32 | VTM0_ded_enable_set_reg0 | Interrupt Enable Set Register 0 | 00B0 2180h |
1C0h | 32 | VTM0_ded_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 00B0 21C0h |
200h | 32 | VTM0_aggr_enable_set | AGGR interrupt enable set Register | 00B0 2200h |
204h | 32 | VTM0_aggr_enable_clr | AGGR interrupt enable clear Register | 00B0 2204h |
208h | 32 | VTM0_aggr_status_set | AGGR interrupt status set Register | 00B0 2208h |
20Ch | 32 | VTM0_aggr_status_clr | AGGR interrupt status clear Register | 00B0 220Ch |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 11000011011 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R_RTL | X_MAJOR | CUSTOM | Y_MINOR | ||||||||||||
R | R | R | R | ||||||||||||
1111 | 1 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | PID follows new scheme |
29 - 28 | BU | R | 2h | Business unit - Processors |
27 - 16 | FUNC | R | 61Bh | Module functional identifier - CTRL MMR |
15 - 11 | R_RTL | R | Fh | RTL revision number - actual value determined by RTL |
10 - 8 | X_MAJOR | R | 1h | Major revision number - actual value determined by RTL |
7 - 6 | CUSTOM | R | 0h | Custom revision number - actual value determined by RTL |
5 - 0 | Y_MINOR | R | 1h | Minor revision number - actual value determined by RTL |
Short Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VTM_VD_MAP | ||||||||||||||
NONE | R | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VD_RTC | RESERVED | TMPSENS_CT | CVD_CT | |||||||||||
NONE | R | NONE | R | R | |||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
19 - 16 | VTM_VD_MAP | R | 0h | Core voltage domain, cVD, global mapping 4-bit code, in the context of this SOC. It shows in which cVD this VTM is instantiated/placed. This field indicates in which core voltage domain, cVD, has been physically placed this VTM. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC, not present is some SOCs, 0x1 = VD_WKUP, 0x2 = VD_MCU, 0x3 = VD_CORE, not present is some SOCs, 0x4-0xE = Mapping varies between SOCs, 0xF = not implemented. Reset value is a VTM tieoff, d_vtm_vd_map. |
RESERVED | NONE | Reserved | ||
12 | VD_RTC | R | 0h | RTC voltage domain presence. 0: There is NO VD_RTC in this SOC. 1: There is a VD_RTC in this SOC. Reset value is a VTM tieoff, d_vd_rtc. |
RESERVED | NONE | Reserved | ||
7 - 4 | TMPSENS_CT | R | 0h | Number of temperature sensors associated with this VTM. Valid values are 4'h0 - 4'h8. 0x0: NO temp-sensor associated to this VTM. 0x8: 8 temp-sensors associated to this VTM. 0x9 to 0xF: invalid values. Reset value is a VTM tieoff, d_vtm_tmpsens_ct. |
3 - 0 | CVD_CT | R | 0h | Number of core voltage domains in device. VD0 is always allocated to VD_RTC, if it exists, and VD1 always to VD_WKUP. The maximum number of cVDs in an SOC is 15, 0xF. Reset value is a VTM tieoff, d_device_cvd_ct. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TS | 0h | Interrupt pending bit set for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the interrupt flag to be set. Used to manually force/drive an interrupt pending event. Reads return the pending stats regardless of the corresponding enable setting. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TC | 0h | Interrupt masked pending bit for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the pending bit to be cleared. Reads return the enabled pending status that includes the corresponding enable setting. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0214h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TS | 0h | Interrupt enable bit for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be set to 1. Reads return the enable settings. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0218h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TC | 0h | Interrupt enable bit for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be cleared. Reads return the enable settings. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0224h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TS | 0h | Interrupt pending bit set for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the interrupt flag to be set. Used to manually force/drive an interrupt pending event. Reads return the pending status regardless of the enable setting. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0228h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TC | 0h | Interrupt enabled pending bit for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the pending bit to be cleared. Reads return the enabled pending status including the corresponding enable setting. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0234h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TS | 0h | Interrupt enable bit for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be set to 1. Reads return the enable settings. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0238h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TC | 0h | Interrupt enable bit for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be cleared. Reads return the enable settings. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0244h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TS | 0h | Interrupt pending bit set for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the interrupt flag to be set. Used to manually force/drive an interrupt pending event. Reads return the raw pending status regardless of the corresponding enable setting. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0248h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TC | 0h | Interrupt enabled pending status bit for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the pending bit to be cleared. Reads return the enabled pending status that factors in the corresponding enable along with the pending status. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0254h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TS | 0h | Interrupt enable bit for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be set to 1. Reads return the enable settings. |
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 0258h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | INT_VD | R/W1TC | 0h | Interrupt enable bit for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be cleared. Reads return the enable settings. |
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Offset = 100h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AVS0_SUP | VD_MAP | RESERVED | ||||||||||||
NONE | R/W | R | NONE | ||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
12 | AVS0_SUP | R/W | 0h | Indicates VD0 AVS class0 support. Indicates if the cVD associated with this VTM's VD MMR supports AVS-Class0: 0: No AVS-Class0. 1: Supports-AVS-Class0. Reset value is from e-fuse at module reset, efuse_vd[a]_avs_sup. |
11 - 8 | VD_MAP | R | 0h | Indicates the core voltage domain mapping of VTM VD. Device specific field. This field indicates to which SOC cVD is this VD of this VTM map to. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC, not present is some SOCs, 0x1 = VD_WKUP, 0x2 = VD_MCU, 0x3 = VD_CORE, not present is some SOCs, 0x4-0xE = Mapping varies between SOCs, 0xF = not implemented. Reset value is a VTM tieoff, d_vd[a]_vd_map_ipcfg. |
RESERVED | NONE | Reserved |
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Offset = 104h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
OPP_3 | OPP_2 | ||||||||||||||
R/W | R/W | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPP_1 | OPP_0 | ||||||||||||||
R/W | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | OPP_3 | R/W | 0h | OPP 3 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[a]_opp_3. |
23 - 16 | OPP_2 | R/W | 0h | OPP 2 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[a]_opp_2. |
15 - 8 | OPP_1 | R/W | 0h | OPP 1 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[a]_opp_1. |
7 - 0 | OPP_0 | R/W | 0h | OPP 0 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[a]_opp_0. |
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Offset = 108h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LT_TH0_ALERT | GT_TH2_ALERT | GT_TH1_ALERT | ||||||||||||
NONE | R | R | R | ||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
2 | LT_TH0_ALERT | R | 0h | This bit reflects the status of the TH0 undertemp alert resulting from the AND of all the similar alerts produced by the temp sensors selected by VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. |
1 | GT_TH2_ALERT | R | 0h | This bit reflects the status of the merged temperature alert resulting from the combination of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. This field shows the actual present level of the resulting OR function of the combined selected signals. |
0 | GT_TH1_ALERT | R | 0h | This bit reflects the status of the merged temperature alert resulting from the OR of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. This field shows the actual present value of the resulting OR function of the combined selected signals. |
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Offset = 10ch + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 010Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TSENS_EVT_SEL | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 - 16 | TSENS_EVT_SEL | R/W1TS | 0h | In this field we select which of the event contributions of the 8-maximum possible temp-monitors controlled by this VTM will contribute to generate the merged event/alerts of this VD. Any combination of them could be selected and varies between SOCs and VDs. Eg: 0x00 : No temp-monitor event contributes to generate the temperature events of this VD. 0x06: Temp-monitors[2,1] contribute to generate the temperature events of this VD. ... 0xFF: All 8 temp-monitors contribute to generate the temperature events of this VD. 0: Writing 0 to this field produces no effect. 1: Writing 1 to any of the bits in this field sets to 1 the corresponding bit in that field. |
RESERVED | NONE | Reserved |
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Offset = 110h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TSENS_EVT_SEL | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 - 16 | TSENS_EVT_SEL | R/W1TC | 0h | In this field we select which of the event contributions of the 8-maximum possible temp-monitors controlled by this VTM will contribute to generate the merged event/alerts of this VD. Any combination of them could be selected and varies between SOCs and VDs. Eg: 0x00 : No temp-monitor event contributes to generate the temperature events of this VD. 0x06: Temp-monitors[2,1] contribute to generate the temperature events of this VD. ... 0xFF: All 8 temp-monitors contribute to generate the temperature events of this VD. 0: Writing 0 to this field produces no effect. 1: Writing 1 to any of the bits in this field clears, = 0, the corresponding bit in that field. |
RESERVED | NONE | Reserved |
Short Description:
Long Description:
Return to Summary Table
Offset = 300h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LT_TH0_EN | GT_TH2_EN | GT_TH1_EN | RESERVED | |||||||||||
NONE | R/W | R/W | R/W | NONE | |||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
10 | LT_TH0_EN | R/W | 0h | Enable under-threshold0 event. Temp event/level control: 0 = Don't generate output level. 1 = Enable generation of event/level high when temperature reading is < value set for threshold point 0. Reset value is POR only. |
9 | GT_TH2_EN | R/W | 0h | Enable over-threshold2 event. Temp event/level control: 0 = Don't generate output level. 1 = Enable generation of event/level high when temperature reading is > value set for threshold point 2. Reset value is POR only. |
8 | GT_TH1_EN | R/W | 0h | Enable over-threshold1 event. Temp event/level control: 0 = Don't generate output level. 1 = Enable generation of event/level high when temperature reading is > value set for threshold point 1. Reset value is POR only. |
RESERVED | NONE | Reserved |
Short Description:
Long Description:
Return to Summary Table
Offset = 308h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0308h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VD_MAP | ||||||||||||||
NONE | R | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXT_OUTRG_ALERT | LT_TH0_ALERT | GT_TH2_ALERT | GT_TH1_ALERT | EOC_FC_UPDATE | DATA_VALID | DATA_OUT | |||||||||
R | R | R | R | R | R | R | |||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
19 - 16 | VD_MAP | R | 0h | Indicates the core voltage domain placement of the temp sensor. Device specific field. This field indicates in which core voltage domain, cVD, has been physically placed the temp-monitor. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC, not present is some SOCs, 0x1 = VD_WKUP, 0x2 = VD_MCU, 0x3 = VD_CORE, not present is some SOCs, 0x4-0xE = Mapping varies between SOCs, 0xF = not implemented. Reset value is a VTM tieoff at POR, d_VTM_TMPSENS[a]_STAT_vd_map_ipcfg. |
15 | MAXT_OUTRG_ALERT | R | 0h | This bit will be driven to a level 1 for a given temperature monitor if it has its corresponding bit maxt_outrg_en = 1, and the temperature reading is reporting to be outside the max temperature supported, temp > programmed value. The level of this signal is a reflection, with some clock delays, of the temperature code reading. This is NOT an sticky bit. Reset value is POR only. |
14 | LT_TH0_ALERT | R | 0h | This field reflects the status of the lt_th0_alert comparator result. The control MMR field lt_th0_en = 1 is required for this field to become 1. Reset value is at POR or clrz. |
13 | GT_TH2_ALERT | R | 0h | This field reflects the status of the gt_th2_alert comparator result. The control MMR field gt_th2_en = 1 is required for this field to become 1. Reset value is at POR or clrz. |
12 | GT_TH1_ALERT | R | 0h | This field reflects the status of the gt_th1_alert comparator result. The control MMR field gt_th1_en = 1 is required for this field to become 1. Reset value is at POR or clrz. |
11 | EOC_FC_UPDATE | R | 0h | First time end of conversion. This field is reset to 0 every time VTM.por_rst_n or VTM_TMPSENS[a]_CTRL.clrz are active, or when continuous mode is deasserted. This bit will be set to 1 after the first time after reset release that data_valid transitions from 0 to 1, and remain at 1 until next time either of por_rst_n or VTM_TMPSENS[a]_CTRL.clrz are active, or when continuous mode is deasserted. Reset value is at POR or VTM_TMPSENS[a]_CTRL.clrz, or continuous mode deassertion. |
10 | DATA_VALID | R | 0h | Data_valid signal value from sensor: ADC End of Conversion. End of conversion indicated by 0 to 1 transition. When high data_out(9:0) out of the temp-monitor is valid. This field doesn't reflect the instantaneous output from the temp-monitor. This field gets latched/updated in this VTM register when the data_valid value from temp-monitor toggles. Reset value is at POR or VTM_TMPSENS[a]_CTRL.clrz. |
9 - 0 | DATA_OUT | R | 0h | Data_out signal value from sensor: Temperature data from the ADC in monitor. Valid after VTM_TMPSENS[a]_STAT.eoc_fc_update = 1. This value will be latched in this VTM register every time monitor output data_valid transitions from 0 to 1. Reset value is POR only. |
Short Description:
Long Description:
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Offset = 30ch + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 030Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TH1_VAL | ||||||||||||||
NONE | R/W | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TH0_VAL | ||||||||||||||
NONE | R/W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
25 - 16 | TH1_VAL | R/W | 0h | Threshold point-1, thpt1, temp-value. Is a 10-bit temperature reference value. This is the 10-bit value that represents a high temperature point, as per sensor spec, with which to compare the present temperature reading, same 10-bit format. If the current temperature reading is > th1_val[9:0] and gt_th1_en=1, that will cause the VTM to set the gt_th1_alert output. Once the current temp reading =< th1_val[9:0] then gt_th1_alert output will go to 0. Reset value is at POR only. |
RESERVED | NONE | Reserved | ||
9 - 0 | TH0_VAL | R/W | 0h | Threshold point-0, thpt0, temp-value. Is a 10-bit temperature reference value. This is the 10-bit value that represents a high temperature point, as per sensor spec, with which to compare the present temperature reading, same 10-bit format. If the current temperature reading is < th0_val[9:0] and lt_th0_en=1, that will cause the VTM to set the lt_th0_alert output. Once the current temp reading => th0_val[9:0] then lt_th0_alert output will go to 0. Reset value is at POR only. |
Short Description:
Long Description:
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Offset = 310h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 0310h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TH2_VAL | ||||||||||||||
NONE | R/W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
9 - 0 | TH2_VAL | R/W | 0h | Threshold point-2, thpt2, temp-value. Is a 10-bit temperature reference value. This is the 10-bit value that represents a high temperature point, as per sensor spec, with which to compare the present temperature reading, same 10-bit format. If the current temperature reading is > th2_val[9:0] and gt_th2_en=1, that will cause the VTM to set the gt_th2_alert output. Once the current temp reading =< th2_val[9:0] then gt_th2_alert output will go to 0. Reset value is at POR only. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 1008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TSENS_CLK_SEL | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TSENS_CLK_DIV | ||||||||||||||
NONE | R/W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TSENS_CLK_SEL | R/W | 0h | Temperature sensor clock source selector. Device specific. 0 = fix_ref_clk as source. 1 = fix_ref2_clk as source. Reset value is at POR only. |
RESERVED | NONE | Reserved | ||
4 - 0 | TSENS_CLK_DIV | R/W | 0h | Temperature sensor clock source divider selector. Device specific. Default set by e-fuse or tie-off. Divider uses select reference clock as source. 0 = 1x divide. 1 = 2x divide. ... 15 = 16x divide. ... 63 = 64x divide. Reset value is from e-fuse at POR, efuse_tsens_clk_src_div. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 100Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ANY_MAXT_OUTRG_ALERT_EN | ||||||||||||||
NONE | R/W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | ANY_MAXT_OUTRG_ALERT_EN | R/W | 0h | This bit when enabled will cause the VTM's output therm_maxtemp_outrange_alert to be driven high, if any of the sources for the maxt_outrg_alert, is set high. Whenever all the maxt_outrg_alert enabled sensor alerts, out of the 8 possible are back to 0 then the output, therm_maxtemp_outrange_alert, will also return to 0. Reset is at POR only. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 1010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MAXT_OUTRG_ALERT_THR0 | ||||||||||||||
NONE | R/W | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAXT_OUTRG_ALERT_THR | ||||||||||||||
NONE | R/W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
25 - 16 | MAXT_OUTRG_ALERT_THR0 | R/W | 0h | This defines the global max temperature out of range safe sample value. If the alert is enabled globally and for the sensor and the sensor reads a value <= this value then the alert is cleared after being triggered. This safe threshold defines at what temp the alert can be cleared. Reset is at POR only. |
RESERVED | NONE | Reserved | ||
9 - 0 | MAXT_OUTRG_ALERT_THR | R/W | 0h | This defines the global max temperature out of range sample value. If the alert is enabled globally and for the sensor and the sensor reads a value >= this value then the alert is triggered. Reset is at POR only. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 1020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SAMPLE_PER_CNT | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | SAMPLE_PER_CNT | R/W | 0h | Temperature sensor sample period count selector. Device specific. Default set by e-fuse or tie-off. This defines the sample period or number of sensor clocks between consecutive samples of the sensor allowed, from the start of the previous sample request to the start of the next sample request. After the sample is received the sensor status MMR fields will not be updated and the sensor will remain disabled. Reset value is from e-fuse at POR, efuse_sample_per_cnt. |
Short Description:
Long Description:
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Offset = 300h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 1300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAXT_OUTRG_EN | RESERVED | CLRZ | SOC | CONT | RESERVED | |||||||||
NONE | R/W | NONE | R/W | R/W | R/W | NONE | |||||||||
0 | 1 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
11 | MAXT_OUTRG_EN | R/W | 0h | Enable out-of-range event. This bit enables generation of the alert in case the given temperature sensors generates a temp code above a programmed max. 0 = Don't generate alert. 1 = Generate alert. Reset value is POR only. |
RESERVED | NONE | Reserved | ||
6 | CLRZ | R/W | 1h | Temp-Monitor control: 0 = Reset all Temp-monitor digital outputs. 1 = Allow operation of sensor. Reset value is POR only. |
5 | SOC | R/W | 0h | Temp-Monitor control: ADC Start of Conversion. A transition from 0 to 1 starts a new ADC conversion cycle. The bit with automatically clear when the conversion has completed. This mode is not valid when already in continuous mode. Reset value is POR only. |
4 | CONT | R/W | 0h | Temp-Monitor control: ADC Continuous mode. Setting this mode enables the VTM to continuously monitor the sensor automatically. Each sample period the sensor will be accessed and the results captured. Reset value is POR only. |
RESERVED | NONE | Reserved |
Short Description:
Long Description:
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Offset = 304h + (j * 20h); where j = 0h to 7h
Instance Name | Base Address |
---|---|
VTM0 | 00B0 1304h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRIMO | RESERVED | TRIMG | ||||||||||||
NONE | R/W | NONE | R/W | ||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
13 - 8 | TRIMO | R/W | 0h | Trim offset bits in the temp sensor. Reset value is from e-fuse at POR, efuse_tmpsens[a]_trimo. |
RESERVED | NONE | Reserved | ||
4 - 0 | TRIMG | R/W | 0h | Trim gain bits in the temp sensor. Reset value is from e-fuse at POR, efuse_tmpsens[a]_trimg. |
Short Description: Aggregator Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 11010100000 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
101 | 10 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | Scheme |
29 - 28 | BU | R | 2h | bu |
27 - 16 | MODULE_ID | R | 6A0h | Module ID |
15 - 11 | REVRTL | R | 5h | RTL version |
10 - 8 | REVMAJ | R | 2h | Major version |
7 - 6 | CUSTOM | R | 0h | Custom version |
5 - 0 | REVMIN | R | 1h | Minor version |
Short Description: ECC Vector Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RD_SVBUS_DONE | RD_SVBUS_ADDRESS | |||||||||||||
NONE | R/W1TC | R/W | |||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||||||||||
R/W1TS | NONE | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
24 | RD_SVBUS_DONE | R/W1TC | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23 - 16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1TS | 0h | Write 1 to trigger a read on the serial VBUS |
RESERVED | NONE | Reserved | ||
10 - 0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
Short Description: Misc Status
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 200Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||
NONE | R | ||||||||||||||
100 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
10 - 0 | NUM_RAMS | R | 4h | Indicates the number of RAMS serviced by the ECC aggregator |
Short Description: Reserved Area for Serial VBUS Registers
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Serial VBUS register data |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 203Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 2040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | ECCAGG_PEND | |||||||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | R/W1TS | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | R/W1TS | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | R/W1TS | 0h | Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_PEND | R/W1TS | 0h | Interrupt Pending Status for eccagg_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 2080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | ECCAGG_ENABLE_SET | |||||||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for eccagg_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
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Instance Name | Base Address |
---|---|
VTM0 | 00B0 20C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | ECCAGG_ENABLE_CLR | |||||||||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for eccagg_pend |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 213Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | ECCAGG_PEND | |||||||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | R/W1TS | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | R/W1TS | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | R/W1TS | 0h | Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_PEND | R/W1TS | 0h | Interrupt Pending Status for eccagg_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | ECCAGG_ENABLE_SET | |||||||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for eccagg_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 21C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | ECCAGG_ENABLE_CLR | |||||||||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for eccagg_pend |
Short Description: AGGR interrupt enable set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TS | R/W1TS | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TS | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1TS | 0h | interrupt enable set for parity errors |
Short Description: AGGR interrupt enable clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TC | R/W1TC | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TC | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1TC | 0h | interrupt enable clear for parity errors |
Short Description: AGGR interrupt status set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 2208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WI | R/WI | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WI | 0h | interrupt status set for svbus timeout errors |
1 - 0 | PARITY | R/WI | 0h | interrupt status set for parity errors |
Short Description: AGGR interrupt status clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
VTM0 | 00B0 220Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WD | R/WD | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WD | 0h | interrupt status clear for svbus timeout errors |
1 - 0 | PARITY | R/WD | 0h | interrupt status clear for parity errors |
Access Type | Code | Description |
---|---|---|
R | R | Read |
R/W1TS | R/W1TS | Read/Write 1 To Set |
R/W1TC | R/W1TC | Read/Write 1 To Clear |
R/W | R/W | Read / Write |
R/WI | R/WI | Read/Write Increment. A write to this bit field increments the specified register bit field by the amount written. |
R/WD | R/WD | Read/Write Decrement. A write to this bit field decrements the specified register bit field by the amount written. |