SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 7-16 lists the memory-mapped registers for the MAILBOX0. All register offset addresses not listed in Table 7-16 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MAILBOX0_REGS0 | 2900 0000h |
MAILBOX0_REGS1 | 2901 0000h |
MAILBOX0_REGS2 | 2902 0000h |
MAILBOX0_REGS3 | 2903 0000h |
MAILBOX0_REGS4 | 2904 0000h |
MAILBOX0_REGS5 | 2905 0000h |
MAILBOX0_REGS6 | 2906 0000h |
MAILBOX0_REGS7 | 2907 0000h |
Offset | Acronym | Register Name | MAILBOX0_REGS0 Physical Address | MAILBOX0_REGS1 Physical Address |
---|---|---|---|---|
0h | MAILBOX_REVISION | Peripheral ID register | 2900 0000h | 2901 0000h |
10h | MAILBOX_SYSCONFIG | Mailbox control register | 2900 0010h | 2901 0010h |
40h + formula | MAILBOX_MESSAGE_y | Message Mailbox y | 2900 0040h + formula | 2901 0040h + formula |
80h + formula | MAILBOX_FIFO_STATUS_y | FIFO status for Mailbox y | 2900 0080h + formula | 2901 0080h + formula |
C0h + formula | MAILBOX_MSG_STATUS_y | Number of messages in Mailbox y | 2900 00C0h + formula | 2901 00C0h + formula |
100h + formula | MAILBOX_IRQ_STATUS_RAW_j | Raw status for each event for user j | 2900 0100h + formula | 2901 0100h + formula |
104h + formula | MAILBOX_IRQ_STATUS_CLR_j | Masked status for each event for user j | 2900 0104h + formula | 2901 0104h + formula |
108h + formula | MAILBOX_IRQ_ENABLE_SET_j | Set interrupt enables user j | 2900 0108h + formula | 2901 0108h + formula |
10Ch + formula | MAILBOX_IRQ_ENABLE_CLR_j | Clear interrupt enables user j | 2900 010Ch + formula | 2901 010Ch + formula |
140h | MAILBOX_IRQ_EOI | End of interrupt register | 2900 0140h | 2901 0140h |
Offset | Acronym | Register Name | MAILBOX0_REGS2 Physical Address | MAILBOX0_REGS3 Physical Address |
---|---|---|---|---|
0h | MAILBOX_REVISION | Peripheral ID register | 2902 0000h | 2903 0000h |
10h | MAILBOX_SYSCONFIG | Mailbox control register | 2902 0010h | 2903 0010h |
40h + formula | MAILBOX_MESSAGE_y | Message Mailbox y | 2902 0040h + formula | 2903 0040h + formula |
80h + formula | MAILBOX_FIFO_STATUS_y | FIFO status for Mailbox y | 2902 0080h + formula | 2903 0080h + formula |
C0h + formula | MAILBOX_MSG_STATUS_y | Number of messages in Mailbox y | 2902 00C0h + formula | 2903 00C0h + formula |
100h + formula | MAILBOX_IRQ_STATUS_RAW_j | Raw status for each event for user j | 2902 0100h + formula | 2903 0100h + formula |
104h + formula | MAILBOX_IRQ_STATUS_CLR_j | Masked status for each event for user j | 2902 0104h + formula | 2903 0104h + formula |
108h + formula | MAILBOX_IRQ_ENABLE_SET_j | Set interrupt enables user j | 2902 0108h + formula | 2903 0108h + formula |
10Ch + formula | MAILBOX_IRQ_ENABLE_CLR_j | Clear interrupt enables user j | 2902 010Ch + formula | 2903 010Ch + formula |
140h | MAILBOX_IRQ_EOI | End of interrupt register | 2902 0140h | 2903 0140h |
Offset | Acronym | Register Name | MAILBOX0_REGS4 Physical Address | MAILBOX0_REGS5 Physical Address |
---|---|---|---|---|
0h | MAILBOX_REVISION | Peripheral ID register | 2904 0000h | 2905 0000h |
10h | MAILBOX_SYSCONFIG | Mailbox control register | 2904 0010h | 2905 0010h |
40h + formula | MAILBOX_MESSAGE_y | Message Mailbox y | 2904 0040h + formula | 2905 0040h + formula |
80h + formula | MAILBOX_FIFO_STATUS_y | FIFO status for Mailbox y | 2904 0080h + formula | 2905 0080h + formula |
C0h + formula | MAILBOX_MSG_STATUS_y | Number of messages in Mailbox y | 2904 00C0h + formula | 2905 00C0h + formula |
100h + formula | MAILBOX_IRQ_STATUS_RAW_j | Raw status for each event for user j | 2904 0100h + formula | 2905 0100h + formula |
104h + formula | MAILBOX_IRQ_STATUS_CLR_j | Masked status for each event for user j | 2904 0104h + formula | 2905 0104h + formula |
108h + formula | MAILBOX_IRQ_ENABLE_SET_j | Set interrupt enables user j | 2904 0108h + formula | 2905 0108h + formula |
10Ch + formula | MAILBOX_IRQ_ENABLE_CLR_j | Clear interrupt enables user j | 2904 010Ch + formula | 2905 010Ch + formula |
140h | MAILBOX_IRQ_EOI | End of interrupt register | 2904 0140h | 2905 0140h |
Offset | Acronym | Register Name | MAILBOX0_REGS6 Physical Address | MAILBOX0_REGS7 Physical Address |
---|---|---|---|---|
0h | MAILBOX_REVISION | Peripheral ID register | 2906 0000h | 2907 0000h |
10h | MAILBOX_SYSCONFIG | Mailbox control register | 2906 0010h | 2907 0010h |
40h + formula | MAILBOX_MESSAGE_y | Message Mailbox y | 2906 0040h + formula | 2907 0040h + formula |
80h + formula | MAILBOX_FIFO_STATUS_y | FIFO status for Mailbox y | 2906 0080h + formula | 2907 0080h + formula |
C0h + formula | MAILBOX_MSG_STATUS_y | Number of messages in Mailbox y | 2906 00C0h + formula | 2907 00C0h + formula |
100h + formula | MAILBOX_IRQ_STATUS_RAW_j | Raw status for each event for user j | 2906 0100h + formula | 2907 0100h + formula |
104h + formula | MAILBOX_IRQ_STATUS_CLR_j | Masked status for each event for user j | 2906 0104h + formula | 2907 0104h + formula |
108h + formula | MAILBOX_IRQ_ENABLE_SET_j | Set interrupt enables user j | 2906 0108h + formula | 2907 0108h + formula |
10Ch + formula | MAILBOX_IRQ_ENABLE_CLR_j | Clear interrupt enables user j | 2906 010Ch + formula | 2907 010Ch + formula |
140h | MAILBOX_IRQ_EOI | End of interrupt register | 2906 0140h | 2907 0140h |
MAILBOX_REVISION is shown in Figure 7-4 and described in Table 7-21.
Return to Summary Table.
This is the standard TI peripheral ID register that exists at address 0 in the peripheral space
Reset = 66FC 8900h
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0000h |
MAILBOX0_REGS1 | 2901 0000h |
MAILBOX0_REGS2 | 2902 0000h |
MAILBOX0_REGS3 | 2903 0000h |
MAILBOX0_REGS4 | 2904 0000h |
MAILBOX0_REGS5 | 2905 0000h |
MAILBOX0_REGS6 | 2906 0000h |
MAILBOX0_REGS7 | 2907 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNCTION | |||||||||||||
R-1h | R-2h | R-6FCh | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_REV | CUSTOM | MINOR_REV | ||||||||||||
R-11h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Used to distinguish which ID numbering scheme is used. |
29-28 | BU | R | 2h | BU identifier |
27-16 | FUNCTION | R | 6FCh | Module family. |
15-11 | RTL_VER | R | 11h | RTL version. R of X.Y.R.Z |
10-8 | MAJOR_REV | R | 1h | Major revision. X of X.Y.R.Z |
7-6 | CUSTOM | R | 0h | Special version number |
5-0 | MINOR_REV | R | 0h | Minor revision. Y of X.Y.R.Z |
MAILBOX_SYSCONFIG is shown in Figure 7-5 and described in Table 7-23.
Return to Summary Table.
This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset.
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0010h |
MAILBOX0_REGS1 | 2901 0010h |
MAILBOX0_REGS2 | 2902 0010h |
MAILBOX0_REGS3 | 2903 0010h |
MAILBOX0_REGS4 | 2904 0010h |
MAILBOX0_REGS5 | 2905 0010h |
MAILBOX0_REGS6 | 2906 0010h |
MAILBOX0_REGS7 | 2907 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT_RESET | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | SOFT_RESET | R/W | 0h | Module Software Reset The bit is automatically reset by the hardware. During reads, it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the mailboxes |
MAILBOX_MESSAGE_y is shown in Figure 7-6 and described in Table 7-25.
Return to Summary Table.
The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue.
Offset = 40h + (y * 4h); where y = 0h to Fh
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0040h + formula |
MAILBOX0_REGS1 | 2901 0040h + formula |
MAILBOX0_REGS2 | 2902 0040h + formula |
MAILBOX0_REGS3 | 2903 0040h + formula |
MAILBOX0_REGS4 | 2904 0040h + formula |
MAILBOX0_REGS5 | 2905 0040h + formula |
MAILBOX0_REGS6 | 2906 0040h + formula |
MAILBOX0_REGS7 | 2907 0040h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VALUE | R/W | 0h | Message in Mailbox y |
MAILBOX_FIFO_STATUS_y is shown in Figure 7-7 and described in Table 7-27.
Return to Summary Table.
The FIFO status register has the status of the Mailbox y FIFO
Offset = 80h + (y * 4h); where y = 0h to Fh
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0080h + formula |
MAILBOX0_REGS1 | 2901 0080h + formula |
MAILBOX0_REGS2 | 2902 0080h + formula |
MAILBOX0_REGS3 | 2903 0080h + formula |
MAILBOX0_REGS4 | 2904 0080h + formula |
MAILBOX0_REGS5 | 2905 0080h + formula |
MAILBOX0_REGS6 | 2906 0080h + formula |
MAILBOX0_REGS7 | 2907 0080h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FULL | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | FULL | R | 0h | Full flag for Mailbox y |
MAILBOX_MSG_STATUS_y is shown in Figure 7-8 and described in Table 7-29.
Return to Summary Table.
The message status register has the status of the messages in Mailbox y
Offset = C0h + (y * 4h); where y = 0h to Fh
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 00C0h + formula |
MAILBOX0_REGS1 | 2901 00C0h + formula |
MAILBOX0_REGS2 | 2902 00C0h + formula |
MAILBOX0_REGS3 | 2903 00C0h + formula |
MAILBOX0_REGS4 | 2904 00C0h + formula |
MAILBOX0_REGS5 | 2905 00C0h + formula |
MAILBOX0_REGS6 | 2906 00C0h + formula |
MAILBOX0_REGS7 | 2907 00C0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_MESSAGES | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | X | |
2-0 | NUM_MESSAGES | R | 0h | Number of messages in Mailbox y |
MAILBOX_IRQ_STATUS_RAW_j is shown in Figure 7-9 and described in Table 7-31.
Return to Summary Table.
The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt generation. It will activate the status bit for two cycles. This may still be masked, however. Write 0 has no effect.
Offset = 100h + (j * 10h); where j = 0h to 3h
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0100h + formula |
MAILBOX0_REGS1 | 2901 0100h + formula |
MAILBOX0_REGS2 | 2902 0100h + formula |
MAILBOX0_REGS3 | 2903 0100h + formula |
MAILBOX0_REGS4 | 2904 0100h + formula |
MAILBOX0_REGS5 | 2905 0100h + formula |
MAILBOX0_REGS6 | 2906 0100h + formula |
MAILBOX0_REGS7 | 2907 0100h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NOTFULLSTATUSMB15 | NEWMSGSTATUSMB15 | NOTFULLSTATUSMB14 | NEWMSGSTATUSMB14 | NOTFULLSTATUSMB13 | NEWMSGSTATUSMB13 | NOTFULLSTATUSMB12 | NEWMSGSTATUSMB12 |
R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NOTFULLSTATUSMB11 | NEWMSGSTATUSMB11 | NOTFULLSTATUSMB10 | NEWMSGSTATUSMB10 | NOTFULLSTATUSMB9 | NEWMSGSTATUSMB9 | NOTFULLSTATUSMB8 | NEWMSGSTATUSMB8 |
R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NOTFULLSTATUSMB7 | NEWMSGSTATUSMB7 | NOTFULLSTATUSMB6 | NEWMSGSTATUSMB6 | NOTFULLSTATUSMB5 | NEWMSGSTATUSMB5 | NOTFULLSTATUSMB4 | NEWMSGSTATUSMB4 |
R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTFULLSTATUSMB3 | NEWMSGSTATUSMB3 | NOTFULLSTATUSMB2 | NEWMSGSTATUSMB2 | NOTFULLSTATUSMB1 | NEWMSGSTATUSMB1 | NOTFULLSTATUSMB0 | NEWMSGSTATUSMB0 |
R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NOTFULLSTATUSMB15 | R/W | 1h | 1 if Mailbox 15 is not full |
30 | NEWMSGSTATUSMB15 | R/W | 0h | 1 if there are messages present in Mailbox 15 |
29 | NOTFULLSTATUSMB14 | R/W | 1h | 1 if Mailbox 14 is not full |
28 | NEWMSGSTATUSMB14 | R/W | 0h | 1 if there are messages present in Mailbox 14 |
27 | NOTFULLSTATUSMB13 | R/W | 1h | 1 if Mailbox 13 is not full |
26 | NEWMSGSTATUSMB13 | R/W | 0h | 1 if there are messages present in Mailbox 13 |
25 | NOTFULLSTATUSMB12 | R/W | 1h | 1 if Mailbox 12 is not full |
24 | NEWMSGSTATUSMB12 | R/W | 0h | 1 if there are messages present in Mailbox 12 |
23 | NOTFULLSTATUSMB11 | R/W | 1h | 1 if Mailbox 11 is not full |
22 | NEWMSGSTATUSMB11 | R/W | 0h | 1 if there are messages present in Mailbox 11 |
21 | NOTFULLSTATUSMB10 | R/W | 1h | 1 if Mailbox 10 is not full |
20 | NEWMSGSTATUSMB10 | R/W | 0h | 1 if there are messages present in Mailbox 10 |
19 | NOTFULLSTATUSMB9 | R/W | 1h | 1 if Mailbox 9 is not full |
18 | NEWMSGSTATUSMB9 | R/W | 0h | 1 if there are messages present in Mailbox 9 |
17 | NOTFULLSTATUSMB8 | R/W | 1h | 1 if Mailbox 8 is not full |
16 | NEWMSGSTATUSMB8 | R/W | 0h | 1 if there are messages present in Mailbox 8 |
15 | NOTFULLSTATUSMB7 | R/W | 1h | 1 if Mailbox 7 is not full |
14 | NEWMSGSTATUSMB7 | R/W | 0h | 1 if there are messages present in Mailbox 7 |
13 | NOTFULLSTATUSMB6 | R/W | 1h | 1 if Mailbox 6 is not full |
12 | NEWMSGSTATUSMB6 | R/W | 0h | 1 if there are messages present in Mailbox 6 |
11 | NOTFULLSTATUSMB5 | R/W | 1h | 1 if Mailbox 5 is not full |
10 | NEWMSGSTATUSMB5 | R/W | 0h | 1 if there are messages present in Mailbox 5 |
9 | NOTFULLSTATUSMB4 | R/W | 1h | 1 if Mailbox 4 is not full |
8 | NEWMSGSTATUSMB4 | R/W | 0h | 1 if there are messages present in Mailbox 4 |
7 | NOTFULLSTATUSMB3 | R/W | 1h | 1 if Mailbox 3 is not full |
6 | NEWMSGSTATUSMB3 | R/W | 0h | 1 if there are messages present in Mailbox 3 |
5 | NOTFULLSTATUSMB2 | R/W | 1h | 1 if Mailbox 2 is not full |
4 | NEWMSGSTATUSMB2 | R/W | 0h | 1 if there are messages present in Mailbox 2 |
3 | NOTFULLSTATUSMB1 | R/W | 1h | 1 if Mailbox 1 is not full |
2 | NEWMSGSTATUSMB1 | R/W | 0h | 1 if there are messages present in Mailbox 1 |
1 | NOTFULLSTATUSMB0 | R/W | 1h | 1 if Mailbox 0 is not full |
0 | NEWMSGSTATUSMB0 | R/W | 0h | 1 if there are messages present in Mailbox 0 |
MAILBOX_IRQ_STATUS_CLR_j is shown in Figure 7-10 and described in Table 7-33.
Return to Summary Table.
The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a given bit to clear this bit. However, if the hardware still has pending, enabled events, the interrupt will fire again in two cycles. Write 0 has no effect.
Offset = 104h + (j * 10h); where j = 0h to 3h
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0104h + formula |
MAILBOX0_REGS1 | 2901 0104h + formula |
MAILBOX0_REGS2 | 2902 0104h + formula |
MAILBOX0_REGS3 | 2903 0104h + formula |
MAILBOX0_REGS4 | 2904 0104h + formula |
MAILBOX0_REGS5 | 2905 0104h + formula |
MAILBOX0_REGS6 | 2906 0104h + formula |
MAILBOX0_REGS7 | 2907 0104h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NOTFULLSTATUSMB15 | NEWMSGSTATUSMB15 | NOTFULLSTATUSMB14 | NEWMSGSTATUSMB14 | NOTFULLSTATUSMB13 | NEWMSGSTATUSMB13 | NOTFULLSTATUSMB12 | NEWMSGSTATUSMB12 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NOTFULLSTATUSMB11 | NEWMSGSTATUSMB11 | NOTFULLSTATUSMB10 | NEWMSGSTATUSMB10 | NOTFULLSTATUSMB9 | NEWMSGSTATUSMB9 | NOTFULLSTATUSMB8 | NEWMSGSTATUSMB8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NOTFULLSTATUSMB7 | NEWMSGSTATUSMB7 | NOTFULLSTATUSMB6 | NEWMSGSTATUSMB6 | NOTFULLSTATUSMB5 | NEWMSGSTATUSMB5 | NOTFULLSTATUSMB4 | NEWMSGSTATUSMB4 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTFULLSTATUSMB3 | NEWMSGSTATUSMB3 | NOTFULLSTATUSMB2 | NEWMSGSTATUSMB2 | NOTFULLSTATUSMB1 | NEWMSGSTATUSMB1 | NOTFULLSTATUSMB0 | NEWMSGSTATUSMB0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NOTFULLSTATUSMB15 | R/W | 0h | 1 if Mailbox 15 is not full and this interrupt bit is enabled |
30 | NEWMSGSTATUSMB15 | R/W | 0h | 1 if there are messages present in Mailbox 15 and this interrupt bit is enabled |
29 | NOTFULLSTATUSMB14 | R/W | 0h | 1 if Mailbox 14 is not full and this interrupt bit is enabled |
28 | NEWMSGSTATUSMB14 | R/W | 0h | 1 if there are messages present in Mailbox 14 and this interrupt bit is enabled |
27 | NOTFULLSTATUSMB13 | R/W | 0h | 1 if Mailbox 13 is not full and this interrupt bit is enabled |
26 | NEWMSGSTATUSMB13 | R/W | 0h | 1 if there are messages present in Mailbox 13 and this interrupt bit is enabled |
25 | NOTFULLSTATUSMB12 | R/W | 0h | 1 if Mailbox 12 is not full and this interrupt bit is enabled |
24 | NEWMSGSTATUSMB12 | R/W | 0h | 1 if there are messages present in Mailbox 12 and this interrupt bit is enabled |
23 | NOTFULLSTATUSMB11 | R/W | 0h | 1 if Mailbox 11 is not full and this interrupt bit is enabled |
22 | NEWMSGSTATUSMB11 | R/W | 0h | 1 if there are messages present in Mailbox 11 and this interrupt bit is enabled |
21 | NOTFULLSTATUSMB10 | R/W | 0h | 1 if Mailbox 10 is not full and this interrupt bit is enabled |
20 | NEWMSGSTATUSMB10 | R/W | 0h | 1 if there are messages present in Mailbox 10 and this interrupt bit is enabled |
19 | NOTFULLSTATUSMB9 | R/W | 0h | 1 if Mailbox 9 is not full and this interrupt bit is enabled |
18 | NEWMSGSTATUSMB9 | R/W | 0h | 1 if there are messages present in Mailbox 9 and this interrupt bit is enabled |
17 | NOTFULLSTATUSMB8 | R/W | 0h | 1 if Mailbox 8 is not full and this interrupt bit is enabled |
16 | NEWMSGSTATUSMB8 | R/W | 0h | 1 if there are messages present in Mailbox 8 and this interrupt bit is enabled |
15 | NOTFULLSTATUSMB7 | R/W | 0h | 1 if Mailbox 7 is not full and this interrupt bit is enabled |
14 | NEWMSGSTATUSMB7 | R/W | 0h | 1 if there are messages present in Mailbox 7 and this interrupt bit is enabled |
13 | NOTFULLSTATUSMB6 | R/W | 0h | 1 if Mailbox 6 is not full and this interrupt bit is enabled |
12 | NEWMSGSTATUSMB6 | R/W | 0h | 1 if there are messages present in Mailbox 6 and this interrupt bit is enabled |
11 | NOTFULLSTATUSMB5 | R/W | 0h | 1 if Mailbox 5 is not full and this interrupt bit is enabled |
10 | NEWMSGSTATUSMB5 | R/W | 0h | 1 if there are messages present in Mailbox 5 and this interrupt bit is enabled |
9 | NOTFULLSTATUSMB4 | R/W | 0h | 1 if Mailbox 4 is not full and this interrupt bit is enabled |
8 | NEWMSGSTATUSMB4 | R/W | 0h | 1 if there are messages present in Mailbox 4 and this interrupt bit is enabled |
7 | NOTFULLSTATUSMB3 | R/W | 0h | 1 if Mailbox 3 is not full and this interrupt bit is enabled |
6 | NEWMSGSTATUSMB3 | R/W | 0h | 1 if there are messages present in Mailbox 3 and this interrupt bit is enabled |
5 | NOTFULLSTATUSMB2 | R/W | 0h | 1 if Mailbox 2 is not full and this interrupt bit is enabled |
4 | NEWMSGSTATUSMB2 | R/W | 0h | 1 if there are messages present in Mailbox 2 and this interrupt bit is enabled |
3 | NOTFULLSTATUSMB1 | R/W | 0h | 1 if Mailbox 1 is not full and this interrupt bit is enabled |
2 | NEWMSGSTATUSMB1 | R/W | 0h | 1 if there are messages present in Mailbox 1 and this interrupt bit is enabled |
1 | NOTFULLSTATUSMB0 | R/W | 0h | 1 if Mailbox 0 is not full and this interrupt bit is enabled |
0 | NEWMSGSTATUSMB0 | R/W | 0h | 1 if there are messages present in Mailbox 0 and this interrupt bit is enabled |
MAILBOX_IRQ_ENABLE_SET_j is shown in Figure 7-11 and described in Table 7-35.
Return to Summary Table.
The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source. Write 0 has no effect.
Offset = 108h + (j * 10h); where j = 0h to 3h
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0108h + formula |
MAILBOX0_REGS1 | 2901 0108h + formula |
MAILBOX0_REGS2 | 2902 0108h + formula |
MAILBOX0_REGS3 | 2903 0108h + formula |
MAILBOX0_REGS4 | 2904 0108h + formula |
MAILBOX0_REGS5 | 2905 0108h + formula |
MAILBOX0_REGS6 | 2906 0108h + formula |
MAILBOX0_REGS7 | 2907 0108h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NOTFULLENABLEMB15 | NEWMSGENABLEMB15 | NOTFULLENABLEMB14 | NEWMSGENABLEMB14 | NOTFULLENABLEMB13 | NEWMSGENABLEMB13 | NOTFULLENABLEMB12 | NEWMSGENABLEMB12 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NOTFULLENABLEMB11 | NEWMSGENABLEMB11 | NOTFULLENABLEMB10 | NEWMSGENABLEMB10 | NOTFULLENABLEMB9 | NEWMSGENABLEMB9 | NOTFULLENABLEMB8 | NEWMSGENABLEMB8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NOTFULLENABLEMB7 | NEWMSGENABLEMB7 | NOTFULLENABLEMB6 | NEWMSGENABLEMB6 | NOTFULLENABLEMB5 | NEWMSGENABLEMB5 | NOTFULLENABLEMB4 | NEWMSGENABLEMB4 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTFULLENABLEMB3 | NEWMSGENABLEMB3 | NOTFULLENABLEMB2 | NEWMSGENABLEMB2 | NOTFULLENABLEMB1 | NEWMSGENABLEMB1 | NOTFULLENABLEMB0 | NEWMSGENABLEMB0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NOTFULLENABLEMB15 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
30 | NEWMSGENABLEMB15 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
29 | NOTFULLENABLEMB14 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
28 | NEWMSGENABLEMB14 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
27 | NOTFULLENABLEMB13 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
26 | NEWMSGENABLEMB13 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
25 | NOTFULLENABLEMB12 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
24 | NEWMSGENABLEMB12 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
23 | NOTFULLENABLEMB11 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
22 | NEWMSGENABLEMB11 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
21 | NOTFULLENABLEMB10 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
20 | NEWMSGENABLEMB10 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
19 | NOTFULLENABLEMB9 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
18 | NEWMSGENABLEMB9 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
17 | NOTFULLENABLEMB8 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
16 | NEWMSGENABLEMB8 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
15 | NOTFULLENABLEMB7 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
14 | NEWMSGENABLEMB7 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
13 | NOTFULLENABLEMB6 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
12 | NEWMSGENABLEMB6 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
11 | NOTFULLENABLEMB5 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
10 | NEWMSGENABLEMB5 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
9 | NOTFULLENABLEMB4 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
8 | NEWMSGENABLEMB4 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
7 | NOTFULLENABLEMB3 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
6 | NEWMSGENABLEMB3 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
5 | NOTFULLENABLEMB2 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
4 | NEWMSGENABLEMB2 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
3 | NOTFULLENABLEMB1 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
2 | NEWMSGENABLEMB1 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
1 | NOTFULLENABLEMB0 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
0 | NEWMSGENABLEMB0 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action. |
MAILBOX_IRQ_ENABLE_CLR_j is shown in Figure 7-12 and described in Table 7-37.
Return to Summary Table.
The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source. Write 0 has no effect.
Offset = 10Ch + (j * 10h); where j = 0h to 3h
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 010Ch + formula |
MAILBOX0_REGS1 | 2901 010Ch + formula |
MAILBOX0_REGS2 | 2902 010Ch + formula |
MAILBOX0_REGS3 | 2903 010Ch + formula |
MAILBOX0_REGS4 | 2904 010Ch + formula |
MAILBOX0_REGS5 | 2905 010Ch + formula |
MAILBOX0_REGS6 | 2906 010Ch + formula |
MAILBOX0_REGS7 | 2907 010Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NOTFULLENABLEMB15 | NEWMSGENABLEMB15 | NOTFULLENABLEMB14 | NEWMSGENABLEMB14 | NOTFULLENABLEMB13 | NEWMSGENABLEMB13 | NOTFULLENABLEMB12 | NEWMSGENABLEMB12 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NOTFULLENABLEMB11 | NEWMSGENABLEMB11 | NOTFULLENABLEMB10 | NEWMSGENABLEMB10 | NOTFULLENABLEMB9 | NEWMSGENABLEMB9 | NOTFULLENABLEMB8 | NEWMSGENABLEMB8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NOTFULLENABLEMB7 | NEWMSGENABLEMB7 | NOTFULLENABLEMB6 | NEWMSGENABLEMB6 | NOTFULLENABLEMB5 | NEWMSGENABLEMB5 | NOTFULLENABLEMB4 | NEWMSGENABLEMB4 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOTFULLENABLEMB3 | NEWMSGENABLEMB3 | NOTFULLENABLEMB2 | NEWMSGENABLEMB2 | NOTFULLENABLEMB1 | NEWMSGENABLEMB1 | NOTFULLENABLEMB0 | NEWMSGENABLEMB0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NOTFULLENABLEMB15 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
30 | NEWMSGENABLEMB15 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
29 | NOTFULLENABLEMB14 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
28 | NEWMSGENABLEMB14 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
27 | NOTFULLENABLEMB13 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
26 | NEWMSGENABLEMB13 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
25 | NOTFULLENABLEMB12 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
24 | NEWMSGENABLEMB12 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
23 | NOTFULLENABLEMB11 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
22 | NEWMSGENABLEMB11 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
21 | NOTFULLENABLEMB10 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
20 | NEWMSGENABLEMB10 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
19 | NOTFULLENABLEMB9 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
18 | NEWMSGENABLEMB9 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
17 | NOTFULLENABLEMB8 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
16 | NEWMSGENABLEMB8 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
15 | NOTFULLENABLEMB7 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
14 | NEWMSGENABLEMB7 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
13 | NOTFULLENABLEMB6 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
12 | NEWMSGENABLEMB6 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
11 | NOTFULLENABLEMB5 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
10 | NEWMSGENABLEMB5 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
9 | NOTFULLENABLEMB4 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
8 | NEWMSGENABLEMB4 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
7 | NOTFULLENABLEMB3 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
6 | NEWMSGENABLEMB3 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
5 | NOTFULLENABLEMB2 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
4 | NEWMSGENABLEMB2 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
3 | NOTFULLENABLEMB1 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
2 | NEWMSGENABLEMB1 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
1 | NOTFULLENABLEMB0 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
0 | NEWMSGENABLEMB0 | R/W | 0h | Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action. |
MAILBOX_IRQ_EOI is shown in Figure 7-13 and described in Table 7-39.
Return to Summary Table.
This is the EOI register with which the software is enabled to do the interrupt clearance.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MAILBOX0_REGS0 | 2900 0140h |
MAILBOX0_REGS1 | 2901 0140h |
MAILBOX0_REGS2 | 2902 0140h |
MAILBOX0_REGS3 | 2903 0140h |
MAILBOX0_REGS4 | 2904 0140h |
MAILBOX0_REGS5 | 2905 0140h |
MAILBOX0_REGS6 | 2906 0140h |
MAILBOX0_REGS7 | 2907 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI3 | EOI2 | EOI1 | EOI0 | |||
W-X | W-0h | W-0h | W-0h | W-0h | |||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | X | |
3 | EOI3 | W | 0h | Software EOI signal for the user 3 interrupt |
2 | EOI2 | W | 0h | Software EOI signal for the user 2 interrupt |
1 | EOI1 | W | 0h | Software EOI signal for the user 1 interrupt |
0 | EOI0 | W | 0h | Software EOI signal for the user 0 interrupt |