SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Figure 12-172 shows all of the MCSPI interface signals in controller mode.
Table 12-323 describes the MCSPI I/O signals in controller mode.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
---|---|---|---|---|
MCU_MCSPI[1-0] | ||||
SPICLK | MCU_SPI[1-0]_CLK | O | MCSPI Serial clock output for controller mode. | HiZ |
SPIDAT[0] | MCU_SPI[1-0]_D0 | O(3) | MCSPI Data I/O for controller mode. | HiZ |
SPIDAT[1] | MCU_SPI[1-0]_D1 | I(4) | MCSPI Data I/O for controller mode. | HiZ |
SPIEN[i] | MCU_SPI[1-0]_CSi | O | MCSPI Chip-select i output for controller mode | HiZ |
MCSPI[4-0] | ||||
SPICLK | SPI[4-0]_CLK | O | MCSPI Serial clock output for controller mode. | HiZ |
SPIDAT[0] | SPI[4-0]_D0 | O(3) | MCSPI Data I/O for controller mode. | HiZ |
SPIDAT[1] | SPI[4-0]_D1 | I(4) | MCSPI Data I/O for controller mode. | HiZ |
SPIEN[i] | SPI[4-0]_CSi | O | MCSPI Chip-select i output for controller mode | HiZ |
For SPI[4-0]_CLK and MCU_SPI[1-0]_CLK signals to work properly, the RXACTIVE bit of the appropriate CTRLMMR_MCU_PADCONFIGx/ CTRLMMR_PADCONFIGy registers should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.