SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | FSS0_OSPI_0 Physical Address |
---|---|---|---|---|
0h | 32 | FSS0_OSPI_0_rev | Aggregator Revision Register | 0071 6000h |
8h | 32 | FSS0_OSPI_0_vector | ECC Vector Register | 0071 6008h |
Ch | 32 | FSS0_OSPI_0_stat | Misc Status | 0071 600Ch |
10h | 32 | FSS0_OSPI_0_reserved_svbus | Reserved Area for Serial VBUS Registers | 0071 6010h |
3Ch | 32 | FSS0_OSPI_0_sec_eoi_reg | EOI Register | 0071 603Ch |
40h | 32 | FSS0_OSPI_0_sec_status_reg0 | Interrupt Status Register 0 | 0071 6040h |
80h | 32 | FSS0_OSPI_0_sec_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 6080h |
C0h | 32 | FSS0_OSPI_0_sec_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 60C0h |
13Ch | 32 | FSS0_OSPI_0_ded_eoi_reg | EOI Register | 0071 613Ch |
140h | 32 | FSS0_OSPI_0_ded_status_reg0 | Interrupt Status Register 0 | 0071 6140h |
180h | 32 | FSS0_OSPI_0_ded_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 6180h |
1C0h | 32 | FSS0_OSPI_0_ded_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 61C0h |
200h | 32 | FSS0_OSPI_0_aggr_enable_set | AGGR interrupt enable set Register | 0071 6200h |
204h | 32 | FSS0_OSPI_0_aggr_enable_clr | AGGR interrupt enable clear Register | 0071 6204h |
208h | 32 | FSS0_OSPI_0_aggr_status_set | AGGR interrupt status set Register | 0071 6208h |
20Ch | 32 | FSS0_OSPI_0_aggr_status_clr | AGGR interrupt status clear Register | 0071 620Ch |
Offset | Length | Acronym | Register Name | FSS0_OSPI_0 Physical Address |
---|---|---|---|---|
0h | 32 | FSS0_OSPI_0_config_reg | 0FC4 0000h | |
4h | 32 | FSS0_OSPI_0_dev_instr_rd_config_reg | 0FC4 0004h | |
8h | 32 | FSS0_OSPI_0_dev_instr_wr_config_reg | 0FC4 0008h | |
Ch | 32 | FSS0_OSPI_0_dev_delay_reg | 0FC4 000Ch | |
10h | 32 | FSS0_OSPI_0_rd_data_capture_reg | 0FC4 0010h | |
14h | 32 | FSS0_OSPI_0_dev_size_config_reg | 0FC4 0014h | |
18h | 32 | FSS0_OSPI_0_sram_partition_cfg_reg | 0FC4 0018h | |
1Ch | 32 | FSS0_OSPI_0_ind_AHB_addr_trigger_reg | 0FC4 001Ch | |
20h | 32 | FSS0_OSPI_0_dma_periph_config_reg | 0FC4 0020h | |
24h | 32 | FSS0_OSPI_0_remap_addr_reg | 0FC4 0024h | |
28h | 32 | FSS0_OSPI_0_mode_bit_config_reg | 0FC4 0028h | |
2Ch | 32 | FSS0_OSPI_0_sram_fill_reg | 0FC4 002Ch | |
30h | 32 | FSS0_OSPI_0_tx_thresh_reg | 0FC4 0030h | |
34h | 32 | FSS0_OSPI_0_rx_thresh_reg | 0FC4 0034h | |
38h | 32 | FSS0_OSPI_0_write_completion_ctrl_reg | 0FC4 0038h | |
3Ch | 32 | FSS0_OSPI_0_no_of_polls_bef_exp_reg | 0FC4 003Ch | |
40h | 32 | FSS0_OSPI_0_irq_status_reg | 0FC4 0040h | |
44h | 32 | FSS0_OSPI_0_irq_mask_reg | 0FC4 0044h | |
50h | 32 | FSS0_OSPI_0_lower_wr_prot_reg | 0FC4 0050h | |
54h | 32 | FSS0_OSPI_0_upper_wr_prot_reg | 0FC4 0054h | |
58h | 32 | FSS0_OSPI_0_wr_prot_ctrl_reg | 0FC4 0058h | |
60h | 32 | FSS0_OSPI_0_indirect_read_xfer_ctrl_reg | 0FC4 0060h | |
64h | 32 | FSS0_OSPI_0_indirect_read_xfer_watermark_reg | 0FC4 0064h | |
68h | 32 | FSS0_OSPI_0_indirect_read_xfer_start_reg | 0FC4 0068h | |
6Ch | 32 | FSS0_OSPI_0_indirect_read_xfer_num_bytes_reg | 0FC4 006Ch | |
70h | 32 | FSS0_OSPI_0_indirect_write_xfer_ctrl_reg | 0FC4 0070h | |
74h | 32 | FSS0_OSPI_0_indirect_write_xfer_watermark_reg | 0FC4 0074h | |
78h | 32 | FSS0_OSPI_0_indirect_write_xfer_start_reg | 0FC4 0078h | |
7Ch | 32 | FSS0_OSPI_0_indirect_write_xfer_num_bytes_reg | 0FC4 007Ch | |
80h | 32 | FSS0_OSPI_0_indirect_trigger_addr_range_reg | 0FC4 0080h | |
8Ch | 32 | FSS0_OSPI_0_flash_command_ctrl_mem_reg | 0FC4 008Ch | |
90h | 32 | FSS0_OSPI_0_flash_cmd_ctrl_reg | 0FC4 0090h | |
94h | 32 | FSS0_OSPI_0_flash_cmd_addr_reg | 0FC4 0094h | |
A0h | 32 | FSS0_OSPI_0_flash_rd_data_lower_reg | 0FC4 00A0h | |
A4h | 32 | FSS0_OSPI_0_flash_rd_data_upper_reg | 0FC4 00A4h | |
A8h | 32 | FSS0_OSPI_0_flash_wr_data_lower_reg | 0FC4 00A8h | |
ACh | 32 | FSS0_OSPI_0_flash_wr_data_upper_reg | 0FC4 00ACh | |
B0h | 32 | FSS0_OSPI_0_polling_flash_status_reg | 0FC4 00B0h | |
B4h | 32 | FSS0_OSPI_0_phy_configuration_reg | 0FC4 00B4h | |
B8h | 32 | FSS0_OSPI_0_phy_master_control_reg | 0FC4 00B8h | |
BCh | 32 | FSS0_OSPI_0_dll_observable_lower_reg | 0FC4 00BCh | |
C0h | 32 | FSS0_OSPI_0_dll_observable_upper_reg | 0FC4 00C0h | |
E0h | 32 | FSS0_OSPI_0_opcode_ext_lower_reg | 0FC4 00E0h | |
E4h | 32 | FSS0_OSPI_0_opcode_ext_upper_reg | 0FC4 00E4h | |
FCh | 32 | FSS0_OSPI_0_module_id_reg | 0FC4 00FCh |
Offset | Length | Acronym | Register Name | FSS0_OSPI_0 Physical Address |
---|---|---|---|---|
0h | 32 | FSS0_OSPI_0_PID | Revision Register | 0FC4 4000h |
4h | 32 | FSS0_OSPI_0_CTRL | Control Register | 0FC4 4004h |
8h | 32 | FSS0_OSPI_0_STAT | Status Regsiter | 0FC4 4008h |
20h | 32 | FSS0_OSPI_0_EOI | End Of Interrupt | 0FC4 4020h |
Short Description: Aggregator Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 11010100000 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
11101 | 10 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | Scheme |
29 - 28 | BU | R | 2h | bu |
27 - 16 | MODULE_ID | R | 6A0h | Module ID |
15 - 11 | REVRTL | R | 1Dh | RTL version |
10 - 8 | REVMAJ | R | 2h | Major version |
7 - 6 | CUSTOM | R | 0h | Custom version |
5 - 0 | REVMIN | R | 0h | Minor version |
Short Description: ECC Vector Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RD_SVBUS_DONE | RD_SVBUS_ADDRESS | |||||||||||||
NONE | R/W1TC | R/W | |||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||||||||||
R/W1TS | NONE | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
24 | RD_SVBUS_DONE | R/W1TC | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23 - 16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1TS | 0h | Write 1 to trigger a read on the serial VBUS |
RESERVED | NONE | Reserved | ||
10 - 0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
Short Description: Misc Status
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 600Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||
NONE | R | ||||||||||||||
1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
10 - 0 | NUM_RAMS | R | 1h | Indicates the number of RAMS serviced by the ECC aggregator |
Short Description: Reserved Area for Serial VBUS Registers
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Serial VBUS register data |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 603Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_PEND | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | SRAM_PEND | R/W1TS | 0h | Interrupt Pending Status for sram_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_SET | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | SRAM_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for sram_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 60C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_CLR | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | SRAM_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for sram_pend |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 613Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_PEND | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | SRAM_PEND | R/W1TS | 0h | Interrupt Pending Status for sram_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_SET | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | SRAM_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for sram_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 61C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_CLR | ||||||||||||||
NONE | R/W1TC | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | SRAM_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for sram_pend |
Short Description: AGGR interrupt enable set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TS | R/W1TS | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TS | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1TS | 0h | interrupt enable set for parity errors |
Short Description: AGGR interrupt enable clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TC | R/W1TC | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TC | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1TC | 0h | interrupt enable clear for parity errors |
Short Description: AGGR interrupt status set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 6208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WI | R/WI | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WI | 0h | interrupt status set for svbus timeout errors |
1 - 0 | PARITY | R/WI | 0h | interrupt status set for parity errors |
Short Description: AGGR interrupt status clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0071 620Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WD | R/WD | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WD | 0h | interrupt status clear for svbus timeout errors |
1 - 0 | PARITY | R/WD | 0h | interrupt status clear for parity errors |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IDLE_FLD | DUAL_BYTE_OPCODE_EN_FLD | CRC_ENABLE_FLD | CONFIG_RESV2_FLD | PIPELINE_PHY_FLD | ENABLE_DTR_PROTOCOL_FLD | ENABLE_AHB_DECODER_FLD | MSTR_BAUD_DIV_FLD | ENTER_XIP_MODE_IMM_FLD | ENTER_XIP_MODE_FLD | ENB_AHB_ADDR_REMAP_FLD | |||||
R | R/W | R/W | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |||||
1 | 0 | 0 | 0 | 0 | 0 | 0 | 1111 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENB_DMA_IF_FLD | WR_PROT_FLASH_FLD | PERIPH_CS_LINES_FLD | PERIPH_SEL_DEC_FLD | ENB_LEGACY_IP_MODE_FLD | ENB_DIR_ACC_CTLR_FLD | RESET_CFG_FLD | RESET_PIN_FLD | HOLD_PIN_FLD | PHY_MODE_ENABLE_FLD | SEL_CLK_PHASE_FLD | SEL_CLK_POL_FLD | ENB_SPI_FLD | |||
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |||
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IDLE_FLD | R | 1h | Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal. |
30 | DUAL_BYTE_OPCODE_EN_FLD | R/W | 0h | Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device is configured to work in another SPI Mode. If enabled, the supplementing bytes are taken from Opcode Extension Register [Lower] and from Opcode Extension Register [Upper]. |
29 | CRC_ENABLE_FLD | R/W | 0h | CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode. |
28 - 26 | CONFIG_RESV2_FLD | R | 0h | Reserved |
25 | PIPELINE_PHY_FLD | R/W | 0h | Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise. |
24 | ENABLE_DTR_PROTOCOL_FLD | R/W | 0h | Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol. |
23 | ENABLE_AHB_DECODER_FLD | R/W | 0h | Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines [bits [13:10]]. Value=1 Active slave is selected based on actual AHB address [the partition for each device is calculated with respect to bits [28:21] of Device Size Configuration Register] |
22 - 19 | MSTR_BAUD_DIV_FLD | R/W | Fh | Master Mode Baud Rate Divisor: SPI baud rate = [master reference clock] baud_rate_divisor |
18 | ENTER_XIP_MODE_IMM_FLD | R/W | 0h | Enter XIP Mode immediately: Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the external device wakes up in XIP mode [as per the contents of its non- volatile configuration register]. The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited. |
17 | ENTER_XIP_MODE_FLD | R/W | 0h | Enter XIP Mode on next READ: Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled, then setting to ?1? will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited. |
16 | ENB_AHB_ADDR_REMAP_FLD | R/W | 0h | Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1, the incoming AHB address will be adapted and sent to the FLASH device as [address + N], where N is the value stored in the remap address register. |
15 | ENB_DMA_IF_FLD | R/W | 0h | Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable |
14 | WR_PROT_FLASH_FLD | R/W | 0h | Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary. |
13 - 10 | PERIPH_CS_LINES_FLD | R/W | 0h | Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0, ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 [no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0] |
9 | PERIPH_SEL_DEC_FLD | R/W | 0h | Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode [n_ss_out = ss] |
8 | ENB_LEGACY_IP_MODE_FLD | R/W | 0h | Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode, any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines,4,2 or 1 byte transfers are permitted and controlled via the HSIZE input. |
7 | ENB_DIR_ACC_CTLR_FLD | R/W | 1h | Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word [FF_W] is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access Controller are both disabled, all AHB requested are completed with an error response. |
6 | RESET_CFG_FLD | R/W | 0h | RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output] |
5 | RESET_PIN_FLD | R/W | 0h | Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature |
4 | HOLD_PIN_FLD | R/W | 0h | Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature |
3 | PHY_MODE_ENABLE_FLD | R/W | 0h | PHY mode enable: When enabled, the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module. |
2 | SEL_CLK_PHASE_FLD | R/W | 0h | Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word |
1 | SEL_CLK_POL_FLD | R/W | 0h | Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high |
0 | ENB_SPI_FLD | R/W | 1h | Octal-SPI Enable: 0 : disable the Octal-SPI, once current transfer of the data word [FF_W] is complete. 1 : enable the Octal-SPI, when spi_enable = 0, all output enables are inactive and all pins are set to input mode. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_INSTR_RESV5_FLD | DUMMY_RD_CLK_CYCLES_FLD | RD_INSTR_RESV4_FLD | MODE_BIT_ENABLE_FLD | RD_INSTR_RESV3_FLD | DATA_XFER_TYPE_EXT_MODE_FLD | ||||||||||
R | R/W | R | R/W | R | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 0 | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_INSTR_RESV2_FLD | ADDR_XFER_TYPE_STD_MODE_FLD | RD_INSTR_RESV1_FLD | DDR_EN_FLD | INSTR_TYPE_FLD | RD_OPCODE_NON_XIP_FLD | ||||||||||
R | R/W | R | R/W | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 11 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 29 | RD_INSTR_RESV5_FLD | R | 0h | Reserved |
28 - 24 | DUMMY_RD_CLK_CYCLES_FLD | R/W | 0h | Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction. |
23 - 21 | RD_INSTR_RESV4_FLD | R | 0h | Reserved |
20 | MODE_BIT_ENABLE_FLD | R/W | 0h | Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes. |
19 - 18 | RD_INSTR_RESV3_FLD | R | 0h | Reserved |
17 - 16 | DATA_XFER_TYPE_EXT_MODE_FLD | R/W | 0h | Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs. |
15 - 14 | RD_INSTR_RESV2_FLD | R | 0h | Reserved |
13 - 12 | ADDR_XFER_TYPE_STD_MODE_FLD | R/W | 0h | Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0] |
11 | RD_INSTR_RESV1_FLD | R | 0h | Reserved |
10 | DDR_EN_FLD | R/W | 0h | DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands |
9 - 8 | INSTR_TYPE_FLD | R/W | 0h | Instruction Type: 0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1 : Use DIO-SPI mode [Instructions, Address and Data always sent on DQ0 and DQ1] 2 : Use QIO-SPI mode [Instructions, Address and Data always sent on DQ0, DQ1, DQ2 and DQ3] 3 : Use Octal-IO-SPI mode [Instructions, Address and Data always sent on DQ[7:0]] |
7 - 0 | RD_OPCODE_NON_XIP_FLD | R/W | 3h | Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WR_INSTR_RESV4_FLD | DUMMY_WR_CLK_CYCLES_FLD | WR_INSTR_RESV3_FLD | DATA_XFER_TYPE_EXT_MODE_FLD | ||||||||||||
R | R/W | R | R/W | ||||||||||||
0 | 0 | 0 | 0 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WR_INSTR_RESV2_FLD | ADDR_XFER_TYPE_STD_MODE_FLD | WR_INSTR_RESV1_FLD | WEL_DIS_FLD | WR_OPCODE_FLD | |||||||||||
R | R/W | R | R/W | R/W | |||||||||||
0 | 0 | 0 | 0 | 10 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 29 | WR_INSTR_RESV4_FLD | R | 0h | Reserved |
28 - 24 | DUMMY_WR_CLK_CYCLES_FLD | R/W | 0h | Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction. |
23 - 18 | WR_INSTR_RESV3_FLD | R | 0h | Reserved |
17 - 16 | DATA_XFER_TYPE_EXT_MODE_FLD | R/W | 0h | Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs. |
15 - 14 | WR_INSTR_RESV2_FLD | R | 0h | Reserved |
13 - 12 | ADDR_XFER_TYPE_STD_MODE_FLD | R/W | 0h | Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0] |
11 - 9 | WR_INSTR_RESV1_FLD | R | 0h | Reserved |
8 | WEL_DIS_FLD | R/W | 0h | WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC |
7 - 0 | WR_OPCODE_FLD | R/W | 2h | Write Opcode |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
D_NSS_FLD | D_BTWN_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D_AFTER_FLD | D_INIT_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | D_NSS_FLD | R/W | 0h | Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period. |
23 - 16 | D_BTWN_FLD | R/W | 0h | Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty. |
15 - 8 | D_AFTER_FLD | R/W | 0h | Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default, the chip select will be deasserted on the cycle following the completion of the current transaction. |
7 - 0 | D_INIT_FLD | R/W | 0h | Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_DATA_RESV3_FLD | DDR_READ_DELAY_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_DATA_RESV2_FLD | DQS_ENABLE_FLD | RD_DATA_RESV1_FLD | SAMPLE_EDGE_SEL_FLD | DELAY_FLD | BYPASS_FLD | ||||||||||
R | R/W | R | R/W | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 20 | RD_DATA_RESV3_FLD | R | 0h | Reserved |
19 - 16 | DDR_READ_DELAY_FLD | R/W | 0h | DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored. |
15 - 9 | RD_DATA_RESV2_FLD | R | 0h | Reserved |
8 | DQS_ENABLE_FLD | R/W | 0h | DQS enable bit: If enabled, signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.. |
7 - 6 | RD_DATA_RESV1_FLD | R | 0h | Reserved |
5 | SAMPLE_EDGE_SEL_FLD | R/W | 0h | Sample edge selection: Choose edge on which data outputs from flash memory will be sampled |
4 - 1 | DELAY_FLD | R/W | 0h | Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles |
0 | BYPASS_FLD | R/W | 1h | Bypass the adapted loopback clock circuit |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DEV_SIZE_RESV_FLD | MEM_SIZE_ON_CS3_FLD | MEM_SIZE_ON_CS2_FLD | MEM_SIZE_ON_CS1_FLD | MEM_SIZE_ON_CS0_FLD | BYTES_PER_SUBSECTOR_FLD | ||||||||||
R | R/W | R/W | R/W | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 10000 | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYTES_PER_DEVICE_PAGE_FLD | NUM_ADDR_BYTES_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
100000000 | 10 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 29 | DEV_SIZE_RESV_FLD | R | 0h | Reserved |
28 - 27 | MEM_SIZE_ON_CS3_FLD | R/W | 0h | Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb. |
26 - 25 | MEM_SIZE_ON_CS2_FLD | R/W | 0h | Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb. |
24 - 23 | MEM_SIZE_ON_CS1_FLD | R/W | 0h | Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb. |
22 - 21 | MEM_SIZE_ON_CS0_FLD | R/W | 0h | Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb. |
20 - 16 | BYTES_PER_SUBSECTOR_FLD | R/W | 10h | Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number. |
15 - 4 | BYTES_PER_DEVICE_PAGE_FLD | R/W | 100h | Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries. |
3 - 0 | NUM_ADDR_BYTES_FLD | R/W | 2h | Number of address bytes. A value of 0 indicates 1 byte. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SRAM_PARTITION_RESV_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRAM_PARTITION_RESV_FLD | ADDR_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 10000000 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 8 | SRAM_PARTITION_RESV_FLD | R | 0h | Reserved |
7 - 0 | ADDR_FLD | R/W | 80h | Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM, in units of SRAM locations. By default, half of the SRAM is reserved for indirect read operation, and half for indirect write. The size of this register will scale with the depth of the SRAM. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | ADDR_FLD | R/W | 0h | This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DMA_PERIPH_RESV2_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_PERIPH_RESV2_FLD | NUM_BURST_REQ_BYTES_FLD | DMA_PERIPH_RESV1_FLD | NUM_SINGLE_REQ_BYTES_FLD | ||||||||||||
R | R/W | R | R/W | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 12 | DMA_PERIPH_RESV2_FLD | R | 0h | Reserved |
11 - 8 | NUM_BURST_REQ_BYTES_FLD | R/W | 0h | Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**[value in this register] which will simplify implementation. |
7 - 4 | DMA_PERIPH_RESV1_FLD | R | 0h | Reserved |
3 - 0 | NUM_SINGLE_REQ_BYTES_FLD | R/W | 0h | Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**[value in this register] which will simplify implementation. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VALUE_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | VALUE_FLD | R/W | 0h | This register is used to remap an incoming AHB address to a different address used by the FLASH device. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_CRC_DATA_LOW_FLD | RX_CRC_DATA_UP_FLD | ||||||||||||||
R | R | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_OUT_ENABLE_FLD | MODE_BIT_RESV1_FLD | CHUNK_SIZE_FLD | MODE_FLD | ||||||||||||
R/W | R | R/W | R/W | ||||||||||||
0 | 0 | 10 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | RX_CRC_DATA_LOW_FLD | R | 0h | RX CRC data [lower] The first CRC byte returned after RX data chunk. |
23 - 16 | RX_CRC_DATA_UP_FLD | R | 0h | RX CRC data [upper] The second CRC byte returned after RX data chunk. |
15 | CRC_OUT_ENABLE_FLD | R/W | 0h | CRC# output enable bit When enabled, the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly. |
14 - 11 | MODE_BIT_RESV1_FLD | R | 0h | Reserved |
10 - 8 | CHUNK_SIZE_FLD | R/W | 2h | It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers. |
7 - 0 | MODE_FLD | R/W | 0h | These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled. |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SRAM_FILL_INDAC_WRITE_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRAM_FILL_INDAC_READ_FLD | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 16 | SRAM_FILL_INDAC_WRITE_FLD | R | 0h | SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition |
15 - 0 | SRAM_FILL_INDAC_READ_FLD | R | 0h | SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_THRESH_RESV_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_THRESH_RESV_FLD | LEVEL_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 5 | TX_THRESH_RESV_FLD | R | 0h | Reserved |
4 - 0 | LEVEL_FLD | R/W | 1h | Defines the level at which the small TX FIFO not full interrupt is generated |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_THRESH_RESV_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_THRESH_RESV_FLD | LEVEL_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 5 | RX_THRESH_RESV_FLD | R | 0h | Reserved |
4 - 0 | LEVEL_FLD | R/W | 1h | Defines the level at which the small RX FIFO not empty interrupt is generated |
Short Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
POLL_REP_DELAY_FLD | POLL_COUNT_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
0 | 1 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_POLLING_EXP_FLD | DISABLE_POLLING_FLD | POLLING_POLARITY_FLD | WR_COMP_CTRL_RESV1_FLD | POLLING_BIT_INDEX_FLD | OPCODE_FLD | ||||||||||
R/W | R/W | R/W | R | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 101 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | POLL_REP_DELAY_FLD | R/W | 0h | Defines additional delay for maintain Chip Select de-asserted during auto-polling phase |
23 - 16 | POLL_COUNT_FLD | R/W | 1h | Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register. |
15 | ENABLE_POLLING_EXP_FLD | R/W | 0h | Set to '1' for enabling auto-polling expiration. |
14 | DISABLE_POLLING_FLD | R/W | 0h | This switches off the automatic polling function |
13 | POLLING_POLARITY_FLD | R/W | 0h | Defines the polling polarity. If '1', then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0', then the write transfer to the device will be complete if the polled bit is equal to '0'. |
12 - 11 | WR_COMP_CTRL_RESV1_FLD | R | 0h | Reserved |
10 - 8 | POLLING_BIT_INDEX_FLD | R/W | 0h | Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for. |
7 - 0 | OPCODE_FLD | R/W | 5h | Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default, this will poll the standard device STATUS register using opcode 0x05 |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NO_OF_POLLS_BEF_EXP_FLD | |||||||||||||||
R/W | |||||||||||||||
11111111111111111111111111111111 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NO_OF_POLLS_BEF_EXP_FLD | |||||||||||||||
R/W | |||||||||||||||
11111111111111111111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | NO_OF_POLLS_BEF_EXP_FLD | R/W | FFFFFFFFh | Number of polls cycles before expiration |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQ_STAT_RESV_FLD | ECC_FAIL_FLD | TX_CRC_CHUNK_BRK_FLD | RX_CRC_DATA_VAL_FLD | RX_CRC_DATA_ERR_FLD | |||||||||||
R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||||||||||
0 | 0 | 0 | 0 | 0 | |||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IRQ_STAT_RESV1_FLD | STIG_REQ_INT_FLD | POLL_EXP_INT_FLD | INDRD_SRAM_FULL_FLD | RX_FIFO_FULL_FLD | RX_FIFO_NOT_EMPTY_FLD | TX_FIFO_FULL_FLD | TX_FIFO_NOT_FULL_FLD | RECV_OVERFLOW_FLD | INDIRECT_XFER_LEVEL_BREACH_FLD | ILLEGAL_ACCESS_DET_FLD | PROT_WR_ATTEMPT_FLD | INDIRECT_READ_REJECT_FLD | INDIRECT_OP_DONE_FLD | UNDERFLOW_DET_FLD | MODE_M_FAIL_FLD |
R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 20 | IRQ_STAT_RESV_FLD | R | 0h | Reserved |
19 | ECC_FAIL_FLD | R/W1TC | 0h | ECC failure This interrupt informs the system that Flash Device reported ECC error. |
18 | TX_CRC_CHUNK_BRK_FLD | R/W1TC | 0h | TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk. |
17 | RX_CRC_DATA_VAL_FLD | R/W1TC | 0h | RX CRC data valid New RX CRC data was captured from Flash Device |
16 | RX_CRC_DATA_ERR_FLD | R/W1TC | 0h | RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller. |
15 | IRQ_STAT_RESV1_FLD | R | 0h | Reserved |
14 | STIG_REQ_INT_FLD | R/W1TC | 0h | The controller is ready for getting another STIG request. |
13 | POLL_EXP_INT_FLD | R/W1TC | 0h | The maximum number of programmed polls cycles is expired |
12 | INDRD_SRAM_FULL_FLD | R/W1TC | 0h | Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation |
11 | RX_FIFO_FULL_FLD | R/W1TC | 0h | Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full |
10 | RX_FIFO_NOT_EMPTY_FLD | R/W1TC | 0h | Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries, 1 : FIFO has >= THRESHOLD entries |
9 | TX_FIFO_FULL_FLD | R/W1TC | 0h | Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full, 1 : FIFO is full |
8 | TX_FIFO_NOT_FULL_FLD | R/W1TC | 0h | Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries, 1 : FIFO has less than THRESHOLD entries |
7 | RECV_OVERFLOW_FLD | R/W1TC | 0h | Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0 : no overflow has been detected. 1 : an overflow has occurred. |
6 | INDIRECT_XFER_LEVEL_BREACH_FLD | R/W1TC | 0h | Indirect Transfer Watermark Level Breached |
5 | ILLEGAL_ACCESS_DET_FLD | R/W1TC | 0h | Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger. |
4 | PROT_WR_ATTEMPT_FLD | R/W1TC | 0h | Write to protected area was attempted and rejected. |
3 | INDIRECT_READ_REJECT_FLD | R/W1TC | 0h | Indirect operation was requested but could not be accepted. Two indirect operations already in storage. |
2 | INDIRECT_OP_DONE_FLD | R/W1TC | 0h | Indirect Operation Complete: Controller has completed last triggered indirect operation |
1 | UNDERFLOW_DET_FLD | R/W1TC | 0h | Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation This bit is reset only by a system reset and cleared only when the register is read. |
0 | MODE_M_FAIL_FLD | R/W1TC | 0h | Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read. 0 : no mode fault has been detected 1 : a mode fault has occurred |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQ_MASK_RESV_FLD | ECC_FAIL_MASK_FLD | TX_CRC_CHUNK_BRK_MASK_FLD | RX_CRC_DATA_VAL_MASK_FLD | RX_CRC_DATA_ERR_MASK_FLD | |||||||||||
R | R/W | R/W | R/W | R/W | |||||||||||
0 | 0 | 0 | 0 | 0 | |||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IRQ_MASK_RESV1_FLD | STIG_REQ_MASK_FLD | POLL_EXP_INT_MASK_FLD | INDRD_SRAM_FULL_MASK_FLD | RX_FIFO_FULL_MASK_FLD | RX_FIFO_NOT_EMPTY_MASK_FLD | TX_FIFO_FULL_MASK_FLD | TX_FIFO_NOT_FULL_MASK_FLD | RECV_OVERFLOW_MASK_FLD | INDIRECT_XFER_LEVEL_BREACH_MASK_FLD | ILLEGAL_ACCESS_DET_MASK_FLD | PROT_WR_ATTEMPT_MASK_FLD | INDIRECT_READ_REJECT_MASK_FLD | INDIRECT_OP_DONE_MASK_FLD | UNDERFLOW_DET_MASK_FLD | MODE_M_FAIL_MASK_FLD |
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 20 | IRQ_MASK_RESV_FLD | R | 0h | Reserved |
19 | ECC_FAIL_MASK_FLD | R/W | 0h | ECC failure Mask |
18 | TX_CRC_CHUNK_BRK_MASK_FLD | R/W | 0h | TX CRC chunk was broken Mask |
17 | RX_CRC_DATA_VAL_MASK_FLD | R/W | 0h | RX CRC data valid Mask |
16 | RX_CRC_DATA_ERR_MASK_FLD | R/W | 0h | RX CRC data error Mask |
15 | IRQ_MASK_RESV1_FLD | R | 0h | Reserved |
14 | STIG_REQ_MASK_FLD | R/W | 0h | STIG request completion Mask |
13 | POLL_EXP_INT_MASK_FLD | R/W | 0h | Polling expiration detected Mask |
12 | INDRD_SRAM_FULL_MASK_FLD | R/W | 0h | Indirect Read Partition overflow mask |
11 | RX_FIFO_FULL_MASK_FLD | R/W | 0h | Small RX FIFO full Mask |
10 | RX_FIFO_NOT_EMPTY_MASK_FLD | R/W | 0h | Small RX FIFO not empty Mask |
9 | TX_FIFO_FULL_MASK_FLD | R/W | 0h | Small TX FIFO full Mask |
8 | TX_FIFO_NOT_FULL_MASK_FLD | R/W | 0h | Small TX FIFO not full Mask |
7 | RECV_OVERFLOW_MASK_FLD | R/W | 0h | Receive Overflow Mask |
6 | INDIRECT_XFER_LEVEL_BREACH_MASK_FLD | R/W | 0h | Transfer Watermark Breach Mask |
5 | ILLEGAL_ACCESS_DET_MASK_FLD | R/W | 0h | Illegal Access Detected Mask |
4 | PROT_WR_ATTEMPT_MASK_FLD | R/W | 0h | Protected Area Write Attempt Mask |
3 | INDIRECT_READ_REJECT_MASK_FLD | R/W | 0h | Indirect Read Reject Mask |
2 | INDIRECT_OP_DONE_MASK_FLD | R/W | 0h | Indirect Complete Mask |
1 | UNDERFLOW_DET_MASK_FLD | R/W | 0h | Underflow Detected Mask |
0 | MODE_M_FAIL_MASK_FLD | R/W | 0h | Mode M Failure Mask |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SUBSECTOR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUBSECTOR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | SUBSECTOR_FLD | R/W | 0h | The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SUBSECTOR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUBSECTOR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | SUBSECTOR_FLD | R/W | 0h | The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WR_PROT_CTRL_RESV_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WR_PROT_CTRL_RESV_FLD | ENB_FLD | INV_FLD | |||||||||||||
R | R/W | R/W | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 2 | WR_PROT_CTRL_RESV_FLD | R | 0h | Reserved |
1 | ENB_FLD | R/W | 0h | Write Protection Enable Bit: When set to 1, any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source triggered. When set to 0, the protection region is disabled. |
0 | INV_FLD | R/W | 0h | Write Protection Inversion Bit: When set to 1, the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0, the protection region defined in the lower and upper write protection registers is the region that the system is not permitted to write to. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INDIR_RD_XFER_RESV_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INDIR_RD_XFER_RESV_FLD | NUM_IND_OPS_DONE_FLD | IND_OPS_DONE_STATUS_FLD | RD_QUEUED_FLD | SRAM_FULL_FLD | RD_STATUS_FLD | CANCEL_FLD | START_FLD | ||||||||
R | R | R/W1TC | R | R/W1TC | R | W | W | ||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 8 | INDIR_RD_XFER_RESV_FLD | R | 0h | Reserved |
7 - 6 | NUM_IND_OPS_DONE_FLD | R | 0h | This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it. |
5 | IND_OPS_DONE_STATUS_FLD | R/W1TC | 0h | Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it. |
4 | RD_QUEUED_FLD | R | 0h | Two indirect read operations have been queued |
3 | SRAM_FULL_FLD | R/W1TC | 0h | SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.; indirect operation [status] |
2 | RD_STATUS_FLD | R | 0h | Indirect Read Status: Indirect read operation in progress [status] |
1 | CANCEL_FLD | W | 0h | Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations. |
0 | START_FLD | W | 0h | Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
LEVEL_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | LEVEL_FLD | R/W | 0h | Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark, an interrupt is also generated. This field can be disabled by writing a value of all zeroes. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | ADDR_FLD | R/W | 0h | This is the start address from which the indirect access will commence its READ operation. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 006Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VALUE_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | VALUE_FLD | R/W | 0h | This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INDIR_WR_XFER_RESV2_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INDIR_WR_XFER_RESV2_FLD | NUM_IND_OPS_DONE_FLD | IND_OPS_DONE_STATUS_FLD | WR_QUEUED_FLD | INDIR_WR_XFER_RESV1_FLD | WR_STATUS_FLD | CANCEL_FLD | START_FLD | ||||||||
R | R | R/W1TC | R | R | R | W | W | ||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 8 | INDIR_WR_XFER_RESV2_FLD | R | 0h | Reserved |
7 - 6 | NUM_IND_OPS_DONE_FLD | R | 0h | This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it. |
5 | IND_OPS_DONE_STATUS_FLD | R/W1TC | 0h | Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it. |
4 | WR_QUEUED_FLD | R | 0h | Two indirect write operations have been queued |
3 | INDIR_WR_XFER_RESV1_FLD | R | 0h | Reserved |
2 | WR_STATUS_FLD | R | 0h | Indirect Write Status: Indirect write operation in progress [status] |
1 | CANCEL_FLD | W | 0h | Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations. |
0 | START_FLD | W | 0h | Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
LEVEL_FLD | |||||||||||||||
R/W | |||||||||||||||
11111111111111111111111111111111 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL_FLD | |||||||||||||||
R/W | |||||||||||||||
11111111111111111111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | LEVEL_FLD | R/W | FFFFFFFFh | Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark, an interrupt is also generated. This field can be disabled by writing a value of all ones. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | ADDR_FLD | R/W | 0h | Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 007Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VALUE_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | VALUE_FLD | R/W | 0h | Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IND_RANGE_RESV1_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IND_RANGE_RESV1_FLD | IND_RANGE_WIDTH_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 100 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 4 | IND_RANGE_RESV1_FLD | R | 0h | Reserved |
3 - 0 | IND_RANGE_WIDTH_FLD | R/W | 4h | This is the address offset of Indirect Trigger Address Register. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 008Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLASH_COMMAND_CTRL_MEM_RESV1_FLD | MEM_BANK_ADDR_FLD | FLASH_COMMAND_CTRL_MEM_RESV2_FLD | NB_OF_STIG_READ_BYTES_FLD | ||||||||||||
R | R/W | R | R/W | ||||||||||||
0 | 0 | 0 | 0 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_BANK_READ_DATA_FLD | FLASH_COMMAND_CTRL_MEM_RESV3_FLD | MEM_BANK_REQ_IN_PROGRESS_FLD | TRIGGER_MEM_BANK_REQ_FLD | ||||||||||||
R | R | R | W | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 29 | FLASH_COMMAND_CTRL_MEM_RESV1_FLD | R | 0h | Reserved |
28 - 20 | MEM_BANK_ADDR_FLD | R/W | 0h | The address of the Memory Bank which data will be read from. |
19 | FLASH_COMMAND_CTRL_MEM_RESV2_FLD | R | 0h | Reserved |
18 - 16 | NB_OF_STIG_READ_BYTES_FLD | R/W | 0h | It defines the number of read bytes for the extended STIG. |
15 - 8 | MEM_BANK_READ_DATA_FLD | R | 0h | Last requested data from the STIG Memory Bank. |
7 - 2 | FLASH_COMMAND_CTRL_MEM_RESV3_FLD | R | 0h | Reserved |
1 | MEM_BANK_REQ_IN_PROGRESS_FLD | R | 0h | Memory Bank data request in progress. |
0 | TRIGGER_MEM_BANK_REQ_FLD | W | 0h | Trigger the Memory Bank data request. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMD_OPCODE_FLD | ENB_READ_DATA_FLD | NUM_RD_DATA_BYTES_FLD | ENB_COMD_ADDR_FLD | ENB_MODE_BIT_FLD | NUM_ADDR_BYTES_FLD | ||||||||||
R/W | R/W | R/W | R/W | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 0 | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENB_WRITE_DATA_FLD | NUM_WR_DATA_BYTES_FLD | NUM_DUMMY_CYCLES_FLD | FLASH_CMD_CTRL_RESV1_FLD | STIG_MEM_BANK_EN_FLD | CMD_EXEC_STATUS_FLD | CMD_EXEC_FLD | |||||||||
R/W | R/W | R/W | R | R/W | R | W | |||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | CMD_OPCODE_FLD | R/W | 0h | Command Opcode: The command opcode field should be setup before triggering the command. For example, 0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to issue commands to the device will make use of the instruction type of the device instruction configuration register. If this field is set to 2'b00, then the command opcode, command address, command dummy bytes and command data will all be transferred in a serial fashion. If this field is set to 2'b01, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. |
23 | ENB_READ_DATA_FLD | R/W | 0h | Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device. |
22 - 20 | NUM_RD_DATA_BYTES_FLD | R/W | 0h | Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes. |
19 | ENB_COMD_ADDR_FLD | R/W | 0h | Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field. |
18 | ENB_MODE_BIT_FLD | R/W | 0h | Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes. |
17 - 16 | NUM_ADDR_BYTES_FLD | R/W | 0h | Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes |
15 | ENB_WRITE_DATA_FLD | R/W | 0h | Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device. |
14 - 12 | NUM_WR_DATA_BYTES_FLD | R/W | 0h | Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for 8 bytes. |
11 - 7 | NUM_DUMMY_CYCLES_FLD | R/W | 0h | Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register. |
6 - 3 | FLASH_CMD_CTRL_RESV1_FLD | R | 0h | Reserved |
2 | STIG_MEM_BANK_EN_FLD | R/W | 0h | STIG Memory Bank enable bit. |
1 | CMD_EXEC_STATUS_FLD | R | 0h | Command execution in progress. |
0 | CMD_EXEC_FLD | W | 0h | Execute the command. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | ADDR_FLD | R/W | 0h | Command Address: This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the address used by the command specified in the opcode field [bits 31:24] of the Flash Command Control register. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA_FLD | R | 0h | This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA_FLD | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA_FLD | R | 0h | This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low. |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA_FLD | R/W | 0h | Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the Flash Command Control register. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA_FLD | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA_FLD | R/W | 0h | Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the Flash Command Control register. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DEVICE_STATUS_RSVD_FLD2 | DEVICE_STATUS_NB_DUMMY | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEVICE_STATUS_RSVD_FLD1 | DEVICE_STATUS_VALID_FLD | DEVICE_STATUS_FLD | |||||||||||||
R | R | R | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 20 | DEVICE_STATUS_RSVD_FLD2 | R | 0h | Reserved |
19 - 16 | DEVICE_STATUS_NB_DUMMY | R/W | 0h | Number of dummy cycles for auto-polling |
15 - 9 | DEVICE_STATUS_RSVD_FLD1 | R | 0h | Reserved |
8 | DEVICE_STATUS_VALID_FLD | R | 0h | Device Status Valid: This should be set when value in bits from 7 to 0 is valid. |
7 - 0 | DEVICE_STATUS_FLD | R | 0h | Defines actual Status Register of Device |
Short Description:
Long Description:
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Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PHY_CONFIG_RESYNC_FLD | PHY_CONFIG_RESET_FLD | PHY_CONFIG_RX_DLL_BYPASS_FLD | PHY_CONFIG_RESV2_FLD | PHY_CONFIG_TX_DLL_DELAY_FLD | |||||||||||
W | W | R/W | R | R/W | |||||||||||
0 | 1 | 0 | 0 | 0 | |||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_CONFIG_RESV1_FLD | PHY_CONFIG_RX_DLL_DELAY_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PHY_CONFIG_RESYNC_FLD | W | 0h | This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields. |
30 | PHY_CONFIG_RESET_FLD | W | 1h | DLL Reset bit: This bit is used for reset of Delay Lines by software. |
29 | PHY_CONFIG_RX_DLL_BYPASS_FLD | R/W | 0h | RX DLL Bypass: This field determines id RX DLL is bypassed. |
28 - 23 | PHY_CONFIG_RESV2_FLD | R | 0h | Reserved |
22 - 16 | PHY_CONFIG_TX_DLL_DELAY_FLD | R/W | 0h | TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk. |
15 - 7 | PHY_CONFIG_RESV1_FLD | R | 0h | Reserved |
6 - 0 | PHY_CONFIG_RX_DLL_DELAY_FLD | R/W | 0h | RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PHY_MASTER_CONTROL_RESV3_FLD | PHY_MASTER_LOCK_MODE_FLD | PHY_MASTER_BYPASS_MODE_FLD | PHY_MASTER_PHASE_DETECT_SELECTOR_FLD | PHY_MASTER_CONTROL_RESV2_FLD | PHY_MASTER_NB_INDICATIONS_FLD | ||||||||||
R | R/W | R/W | R/W | R | R/W | ||||||||||
0 | 0 | 1 | 0 | 0 | 0 | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_MASTER_CONTROL_RESV1_FLD | PHY_MASTER_INITIAL_DELAY_FLD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 25 | PHY_MASTER_CONTROL_RESV3_FLD | R | 0h | Reserved |
24 | PHY_MASTER_LOCK_MODE_FLD | R/W | 0h | Determines if the master delay line locks on a full cycle or half cycle of delay. |
23 | PHY_MASTER_BYPASS_MODE_FLD | R/W | 1h | Controls the bypass mode of the master and slave DLLs. |
22 - 20 | PHY_MASTER_PHASE_DETECT_SELECTOR_FLD | R/W | 0h | Selects the number of delay elements to be inserted between the phase detect flip-flops. |
19 | PHY_MASTER_CONTROL_RESV2_FLD | R | 0h | Reserved |
18 - 16 | PHY_MASTER_NB_INDICATIONS_FLD | R/W | 0h | Holds the number of consecutive increment or decrement indications. |
15 - 7 | PHY_MASTER_CONTROL_RESV1_FLD | R | 0h | Reserved |
6 - 0 | PHY_MASTER_INITIAL_DELAY_FLD | R/W | 0h | This value is the initial delay value for the DLL. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD | DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD | ||||||||||||||
R | R | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD | DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD | DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD | DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD | DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD | |||||||||||
R | R | R | R | R | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD | R | 0h | Holds the state of the cumulative dll_lock_inc register. |
23 - 16 | DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD | R | 0h | Holds the state of the cumulative dll_lock_dec register. |
15 | DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD | R | 0h | This bit indicates that lock of loopback is done. |
14 - 8 | DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD | R | 0h | Reports the DLL encoder value from the master DLL to the slave DLLs. |
7 - 3 | DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD | R | 0h | Reports the number of increments or decrements required for the master DLL to complete the locking process. |
2 - 1 | DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD | R | 0h | Defines the mode in which the DLL has achieved the lock. |
0 | DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD | R | 0h | Indicates status of DLL. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DLL_OBSERVABLE_UPPER_RESV2_FLD | DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD | ||||||||||||||
R | R | ||||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLL_OBSERVABLE_UPPER_RESV1_FLD | DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD | ||||||||||||||
R | R | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 23 | DLL_OBSERVABLE_UPPER_RESV2_FLD | R | 0h | Reserved |
22 - 16 | DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD | R | 0h | Holds the encoded value for the TX delay line for this slice. |
15 - 7 | DLL_OBSERVABLE_UPPER_RESV1_FLD | R | 0h | Reserved |
6 - 0 | DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD | R | 0h | Holds the encoded value for the RX delay line for this slice. |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EXT_READ_OPCODE_FLD | EXT_WRITE_OPCODE_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
10011 | 11101101 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXT_POLL_OPCODE_FLD | EXT_STIG_OPCODE_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
11111010 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | EXT_READ_OPCODE_FLD | R/W | 13h | Supplement byte of any Read Opcode |
23 - 16 | EXT_WRITE_OPCODE_FLD | R/W | EDh | Supplement byte of any Write Opcode |
15 - 8 | EXT_POLL_OPCODE_FLD | R/W | FAh | Supplement byte of any Polling Opcode |
7 - 0 | EXT_STIG_OPCODE_FLD | R/W | 0h | Supplement byte of any STIG Opcode |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WEL_OPCODE_FLD | EXT_WEL_OPCODE_FLD | ||||||||||||||
R/W | R/W | ||||||||||||||
110 | 11111001 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPCODE_EXT_UPPER_RESV1_FLD | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | WEL_OPCODE_FLD | R/W | 6h | First byte of any WEL Opcode |
23 - 16 | EXT_WEL_OPCODE_FLD | R/W | F9h | Supplement byte of any WEL Opcode |
15 - 0 | OPCODE_EXT_UPPER_RESV1_FLD | R | 0h | Reserved |
Short Description:
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 00FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FIX_PATCH_FLD | MODULE_ID_FLD | ||||||||||||||
R | R | ||||||||||||||
11 | 11 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODULE_ID_FLD | MODULE_ID_RESV_FLD | CONF_FLD | |||||||||||||
R | R | R | |||||||||||||
11 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 24 | FIX_PATCH_FLD | R | 3h | Fix/path number related to revision described by 3 LSBs of this register |
23 - 8 | MODULE_ID_FLD | R | 3h | Module/Revision ID number |
7 - 2 | MODULE_ID_RESV_FLD | R | 0h | Reserved |
1 - 0 | CONF_FLD | R | 0h | Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration |
Short Description: Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 100001110100 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R | R | R | R | ||||||||||||
1111 | 1 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | PID register scheme |
29 - 28 | BU | R | 2h | Business Unit: 10 = Processors |
27 - 16 | MODULE_ID | R | 874h | Module ID |
15 - 11 | RTL | R | Fh | RTL revision. Will vary depending on release. |
10 - 8 | MAJOR | R | 1h | Major revision |
7 - 6 | CUSTOM | R | 0h | Custom |
5 - 0 | MINOR | R | 0h | Minor revision |
Short Description: Control Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 4004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIPELINE_MODE_FLUSH | RESERVED | |||||||||||||
NONE | R/W | NONE | |||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | PIPELINE_MODE_FLUSH | R/W | 0h | 1 - Flush Cadence Flash Controller FIFO by forcin gAHB SEL low. 0 - AHB Sel to Cadence Controller is 1 |
RESERVED | NONE | Reserved |
Short Description: Status Regsiter
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MEM_INIT_DONE | RESERVED | |||||||||||||
NONE | R | NONE | |||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | MEM_INIT_DONE | R | 0h | 0:Memory Initialization is in progress, 1:Memory Intialization Done |
RESERVED | NONE | Reserved |
Short Description: End Of Interrupt
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
FSS0_OSPI_0 | 0FC4 4020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI | ||||||||||||||
NONE | W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | EOI | W | 0h | Write with bit position of targetted interrupt. (E.g. Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt |
Access Type | Code | Description |
---|---|---|
R | R | Read |
R/W1TC | R/W1TC | Read/Write 1 To Clear |
R/W | R/W | Read / Write |
R/W1TS | R/W1TS | Read/Write 1 To Set |
R/WI | R/WI | Read/Write Increment. A write to this bit field increments the specified register bit field by the amount written. |
R/WD | R/WD | Read/Write Decrement. A write to this bit field decrements the specified register bit field by the amount written. |
W | W | Write |