SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-4411 lists the memory-mapped registers for the EQEP modules. All register offset addresses not listed in Table 12-4411 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
EQEP0_REG | 2320 0000h |
EQEP1_REG | 2321 0000h |
EQEP2_REG | 2322 0000h |
Offset | Acronym | Register Name | EQEP0_REG Physical Address | EQEP1_REG Physical Address | EQEP2_REG Physical Address |
---|---|---|---|---|---|
0h | EQEP_QPOSCNT | QEP Position Counter Register | 2320 0000h | 2321 0000h | 2322 0000h |
4h | EQEP_QPOSINIT | Position Counter Initialization Register | 2320 0004h | 2321 0004h | 2322 0004h |
8h | EQEP_QPOSMAX | Maximum Position Count Register | 2320 0008h | 2321 0008h | 2322 0008h |
Ch | EQEP_QPOSCMP | Position Compare Register | 2320 000Ch | 2321 000Ch | 2322 000Ch |
10h | EQEP_QPOSILAT | Index Position Latch Register | 2320 0010h | 2321 0010h | 2322 0010h |
14h | EQEP_QPOSSLAT | Strobe Position Latch Register | 2320 0014h | 2321 0014h | 2322 0014h |
18h | EQEP_QPOSLAT | QEP Position Counter Latch Register | 2320 0018h | 2321 0018h | 2322 0018h |
1Ch | EQEP_QUTMR | QEP Unit Timer Register | 2320 001Ch | 2321 001Ch | 2322 001Ch |
20h | EQEP_QUPRD | QEP Unit Period Register | 2320 0020h | 2321 0020h | 2322 0020h |
24h | EQEP_QWD_TMR_PRD | QEP Watchdog Timer and Period Register | 2320 0024h | 2321 0024h | 2322 0024h |
28h | EQEP_QDEC_QEP_CTL | Quadrature Decoder and QEP Control Register | 2320 0028h | 2321 0028h | 2322 0028h |
2Ch | EQEP_QCAP_QPOS_CTL | QEP Capture and Position Compare Control Register | 2320 002Ch | 2321 002Ch | 2322 002Ch |
30h | EQEP_QINT_EN_FLG | QEP Interrupt Control and Flag Register | 2320 0030h | 2321 0030h | 2322 0030h |
34h | EQEP_QINT_CLR_FRC | QEP Interrupt Clear and Forcing Register | 2320 0034h | 2321 0034h | 2322 0034h |
38h | EQEP_QEP_STS_CT | QEP Status and Capture Timer Register | 2320 0038h | 2321 0038h | 2322 0038h |
3Ch | EQEP_QC_PRD_TLAT | QEP Capture Period and Timer Latch Register | 2320 003Ch | 2321 003Ch | 2322 003Ch |
40h | EQEP_QCPRDLAT | QEP Capture Period Latch Register | 2320 0040h | 2321 0040h | 2322 0040h |
5Ch | EQEP_PID | Peripheral ID Register | 2320 005Ch | 2321 005Ch | 2322 005Ch |
EQEP_QPOSCNT is shown in Figure 12-2326 and described in Table 12-4413.
Return to Summary Table.
QEP Position Counter register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0000h |
EQEP1_REG | 2321 0000h |
EQEP2_REG | 2322 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POSCNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | POSCNT | R/W | 0h | This
32-bit Position Counter register counts up/down on every QEP
pulse based on direction input. |
EQEP_QPOSINIT is shown in Figure 12-2327 and described in Table 12-4415.
Return to Summary Table.
Position Counter Initialization register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0004h |
EQEP1_REG | 2321 0004h |
EQEP2_REG | 2322 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITPOS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | INITPOS | R/W | 0h | This
register contains the position value to be used to initialize
the Position Counter based on external strobe or Index event.
|
EQEP_QPOSMAX is shown in Figure 12-2328 and described in Table 12-4417.
Return to Summary Table.
Maximum Position Count register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0008h |
EQEP1_REG | 2321 0008h |
EQEP2_REG | 2322 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXPOS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAXPOS | R/W | 0h | This register contains the maximum Position Counter value for error checking in index reset mode or to reset the Position Counter based on the maximum count value. |
EQEP_QPOSCMP is shown in Figure 12-2329 and described in Table 12-4419.
Return to Summary Table.
Position Compare register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 000Ch |
EQEP1_REG | 2321 000Ch |
EQEP2_REG | 2322 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POSCMP | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | POSCMP | R/W | 0h | Position compare value in this register is compared with the Position Counter (EQEP_QPOSCNT[31-0] POSCNT) to optionally generate interrupt on compare match. |
EQEP_QPOSILAT is shown in Figure 12-2330 and described in Table 12-4421.
Return to Summary Table.
Index Position Latch register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0010h |
EQEP1_REG | 2321 0010h |
EQEP2_REG | 2322 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPOSLAT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IPOSLAT | R | 0h | Position Counter value can be latched into this register on index event as defined by the EQEP_QDEC_QEP_CTL[21-20] IEL bit field. |
EQEP_QPOSSLAT is shown in Figure 12-2331 and described in Table 12-4423.
Return to Summary Table.
Strobe Position Latch register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0014h |
EQEP1_REG | 2321 0014h |
EQEP2_REG | 2322 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPOSLAT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SPOSLAT | R | 0h | Position Counter value can be latched into this register on strobe event as defined by the EQEP_QDEC_QEP_CTL[22] SEL bit. |
EQEP_QPOSLAT is shown in Figure 12-2332 and described in Table 12-4425.
Return to Summary Table.
QEP Position Counter Latch register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0018h |
EQEP1_REG | 2321 0018h |
EQEP2_REG | 2322 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POSLAT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | POSLAT | R | 0h | Position Counter value can be latched into this register on unit time out event. |
EQEP_QUTMR is shown in Figure 12-2333 and described in Table 12-4427.
Return to Summary Table.
QEP Unit Timer register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 001Ch |
EQEP1_REG | 2321 001Ch |
EQEP2_REG | 2322 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UNITTMR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UNITTMR | R/W | 0h | This
register acts as time base for unit time event generation. |
EQEP_QUPRD is shown in Figure 12-2334 and described in Table 12-4429.
Return to Summary Table.
QEP Unit Period register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0020h |
EQEP1_REG | 2321 0020h |
EQEP2_REG | 2322 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UNITPRD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UNITPRD | R/W | 0h | This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt. |
EQEP_QWD_TMR_PRD is shown in Figure 12-2335 and described in Table 12-4431.
Return to Summary Table.
QEP Watchdog Timer and Period register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0024h |
EQEP1_REG | 2321 0024h |
EQEP2_REG | 2322 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QWDPRD | QWDTMR | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | QWDPRD | R/W | 0h | This
field contains the time-out count for the QEP peripheral watch
dog timer. |
15-0 | QWDTMR | R/W | 0h | This
field acts as time base for watch dog to detect stalls. |
EQEP_QDEC_QEP_CTL is shown in Figure 12-2336 and described in Table 12-4433.
Return to Summary Table.
Quadrature Decoder and QEP Control register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0028h |
EQEP1_REG | 2321 0028h |
EQEP2_REG | 2322 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FREE_SOFT | PCRM | SEI | IEI | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SWI | SEL | IEL | QPEN | QCLM | UTE | WDE | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
QSRC | SOEN | SPSEL | XCR | SWAP | IGATE | QAP | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QBP | QIP | QSP | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | FREE_SOFT | R/W | 0h | POSCNT Behavior: |
29-28 | PCRM | R/W | 0h | Position Counter Reset Mode: |
27-26 | SEI | R/W | 0h | Strobe Event Initialization of Position Counter: |
25-24 | IEI | R/W | 0h | Index Event Initialization of Position Counter: |
23 | SWI | R/W | 0h | Software Initialization of Position Counter: |
22 | SEL | R/W | 0h | Strobe Event Latch of Position Counter: |
21-20 | IEL | R/W | 0h | Index Event Latch of Position Counter (Software Index
Marker): |
19 | QPEN | R/W | 0h | Quadrature Position Counter Enable/Software Reset: |
18 | QCLM | R/W | 0h | EQEP
Capture Latch Mode: |
17 | UTE | R/W | 0h | QEP
Unit Timer Enable: |
16 | WDE | R/W | 0h | QEP
Watchdog Enable: |
15-14 | QSRC | R/W | 0h | Position Counter Source selection: |
13 | SOEN | R/W | 0h | Enable Position Compare Sync Output: |
12 | SPSEL | R/W | 0h | Sync
Output Pin Selection: |
11 | XCR | R/W | 0h | External Clock Rate: |
10 | SWAP | R/W | 0h | CLK/DIR Signal Source for Position Counter: |
9 | IGATE | R/W | 0h | Index Pulse Gating Option: |
8 | QAP | R/W | 0h | QEPA
Input Polarity: |
7 | QBP | R/W | 0h | QEPB
Input Polarity: |
6 | QIP | R/W | 0h | QEPI
Input Polarity: |
5 | QSP | R/W | 0h | QEPS
Input Polarity: |
4-0 | RESERVED | R | 0h | Reserved |
EQEP_QCAP_QPOS_CTL is shown in Figure 12-2337 and described in Table 12-4435.
Return to Summary Table.
QEP Capture and Position Compare Control register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 002Ch |
EQEP1_REG | 2321 002Ch |
EQEP2_REG | 2322 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PCSHDW | PCLOAD | PCPOL | PCE | PCSPW | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PCSPW | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CEN | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCPS | UPPS | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PCSHDW | R/W | 0h | Position-Compare Shadow Enable: |
30 | PCLOAD | R/W | 0h | Position Compare Shadow Load Mode: |
29 | PCPOL | R/W | 0h | Polarity of Sync Output: |
28 | PCE | R/W | 0h | Position Compare Enable/Disable: |
27-16 | PCSPW | R/W | 0h | Select Pulse Width Period in EQEP_FICLK Cycles: |
15 | CEN | R/W | 0h | Enable EQEP Capture: |
14-7 | RESERVED | R | 0h | Reserved |
6-4 | CCPS | R/W | 0h | EQEP
Capture Timer Clock Prescalar: |
3-0 | UPPS | R/W | 0h | Unit
Position Event Prescalar: |
EQEP_QINT_EN_FLG is shown in Figure 12-2338 and described in Table 12-4437.
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QEP Interrupt Control and Flag register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0030h |
EQEP1_REG | 2321 0030h |
EQEP2_REG | 2322 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | UTOI_FLG | IELI_FLG | SELI_FLG | PCMI_FLG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PCRI_FLG | PCOI_FLG | PCUI_FLG | WTOI_FLG | QDCI_FLG | QPEI_FLG | PCEI_FLG | INT_FLG |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | UTOI_EN | IELI_EN | SELI_EN | PCMI_EN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCRI_EN | PCOI_EN | PCUI_EN | WTOI_EN | QDCI_EN | QPEI_EN | PCEI_EN | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27 | UTOI_FLG | R | 0h | Unit
Time Out Interrupt Flag: |
26 | IELI_FLG | R | 0h | Index Event Latch Interrupt Flag: |
25 | SELI_FLG | R | 0h | Strobe Event Latch Interrupt Flag: |
24 | PCMI_FLG | R | 0h | EQEP
Compare Match Event Interrupt Flag: |
23 | PCRI_FLG | R | 0h | Position Compare Ready Interrupt Flag: |
22 | PCOI_FLG | R | 0h | Position Counter Overflow Interrupt Flag: |
21 | PCUI_FLG | R | 0h | Position Counter Underflow Interrupt Flag: |
20 | WTOI_FLG | R | 0h | Watchdog Timeout Interrupt Flag: |
19 | QDCI_FLG | R | 0h | Quadrature Direction Change Interrupt Flag: |
18 | QPEI_FLG | R | 0h | Quadrature Phase Error Interrupt Flag: |
17 | PCEI_FLG | R | 0h | Position Counter Error Interrupt Flag: |
16 | INT_FLG | R | 0h | Global Interrupt Status Flag: |
15-12 | RESERVED | R | 0h | Reserved |
11 | UTOI_EN | R/W | 0h | Unit
Time Out Interrupt Enable: |
10 | IELI_EN | R/W | 0h | Index Event Latch Interrupt Enable: |
9 | SELI_EN | R/W | 0h | Strobe Event Latch Interrupt Enable: |
8 | PCMI_EN | R/W | 0h | Position Compare Match Interrupt Enable: |
7 | PCRI_EN | R/W | 0h | Position Compare Ready Interrupt Enable: |
6 | PCOI_EN | R/W | 0h | Position Counter Overflow Interrupt Enable: |
5 | PCUI_EN | R/W | 0h | Position Counter Underflow Interrupt Enable: |
4 | WTOI_EN | R/W | 0h | Watchdog Time Out Interrupt Enable: |
3 | QDCI_EN | R/W | 0h | Quadrature Direction Change Interrupt Enable: |
2 | QPEI_EN | R/W | 0h | Quadrature Phase Error Interrupt Enable: |
1 | PCEI_EN | R/W | 0h | Position Counter Error Interrupt Enable: |
0 | RESERVED | R | 0h | Reserved |
EQEP_QINT_CLR_FRC is shown in Figure 12-2339 and described in Table 12-4439.
Return to Summary Table.
QEP Interrupt Clear and Forcing register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0034h |
EQEP1_REG | 2321 0034h |
EQEP2_REG | 2322 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | UTOI_FRC | IELI_FRC | SELI_FRC | PCMI_FRC | |||
R-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PCRI_FRC | PCOI_FRC | PCUI_FRC | WTOI_FRC | QDCI_FRC | QPEI_FRC | PCEI_FRC | RESERVED |
W1S-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | UTOI_CLR | IELI_CLR | SELI_CLR | PCMI_CLR | |||
R-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCRI_CLR | PCOI_CLR | PCUI_CLR | WTOI_CLR | QDCI_CLR | QPEI_CLR | PCEI_CLR | INT_CLR |
W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h |
LEGEND: W = Write Only; W1C = Write 1 to Clear Bit; W1S = Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27 | UTOI_FRC | W1S | 0h | Unit
Time Out Interrupt Force: |
26 | IELI_FRC | W1S | 0h | Index Event Latch Interrupt Force: |
25 | SELI_FRC | W1S | 0h | Strobe Event Latch Interrupt Force: |
24 | PCMI_FRC | W1S | 0h | Position Compare Match Interrupt Force: |
23 | PCRI_FRC | W1S | 0h | Position Compare Ready Interrupt Force: |
22 | PCOI_FRC | W1S | 0h | Position Counter Overflow Interrupt Force: |
21 | PCUI_FRC | W1S | 0h | Position Counter Underflow Interrupt Force: |
20 | WTOI_FRC | W1S | 0h | Watchdog Time Out Interrupt Force: |
19 | QDCI_FRC | W1S | 0h | Quadrature Direction Change Interrupt Force: |
18 | QPEI_FRC | W1S | 0h | Quadrature Phase Error Interrupt Force: |
17 | PCEI_FRC | W1S | 0h | Position Counter Error Interrupt Force: |
16-12 | RESERVED | R | 0h | Reserved |
11 | UTOI_CLR | W1C | 0h | Clear Unit Time Out Interrupt Flag: |
10 | IELI_CLR | W1C | 0h | Clear Index Event Latch Interrupt Flag: |
9 | SELI_CLR | W1C | 0h | Clear Strobe Event Latch Interrupt Flag: |
8 | PCMI_CLR | W1C | 0h | Clear QEP Compare Match Event Interrupt Flag: |
7 | PCRI_CLR | W1C | 0h | Clear Position Compare Ready Interrupt Flag: |
6 | PCOI_CLR | W1C | 0h | Clear Position Counter Overflow Interrupt Flag: |
5 | PCUI_CLR | W1C | 0h | Clear Position Counter Underflow Interrupt Flag: |
4 | WTOI_CLR | W1C | 0h | Clear Watchdog Timeout Interrupt Flag: |
3 | QDCI_CLR | W1C | 0h | Clear Quadrature Direction Change Interrupt Flag: |
2 | QPEI_CLR | W1C | 0h | Clear Quadrature Phase Error Interrupt Flag: |
1 | PCEI_CLR | W1C | 0h | Clear Position Counter Error Interrupt Flag: |
0 | INT_CLR | W1C | 0h | Global Interrupt Clear Flag: |
EQEP_QEP_STS_CT is shown in Figure 12-2340 and described in Table 12-4441.
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QEP Status and Capture Timer register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0038h |
EQEP1_REG | 2321 0038h |
EQEP2_REG | 2322 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
QCTMR | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
QCTMR | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FIDF | QDF | QDLF | COEF | CDEF | FIMF | PCEF |
R-0h | R-0h | R-0h | R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | QCTMR | R/W | 0h | This field provides time base for edge capture unit. |
15-7 | RESERVED | R | 0h | Reserved |
6 | FIDF | R | 0h | Direction on First Index Marker |
5 | QDF | R | 0h | Quadrature Direction Flag |
4 | QDLF | R | 0h | EQEP
Direction Latch Flag |
3 | COEF | R/W1C | 0h | Capture Overflow Error Flag |
2 | CDEF | R/W1C | 0h | Capture Direction Error Flag 1h = Direction change occurred between the capture position event |
1 | FIMF | R/W1C | 0h | First Index Marker Flag |
0 | PCEF | R | 0h | Position Counter Error Flag |
EQEP_QC_PRD_TLAT is shown in Figure 12-2341 and described in Table 12-4443.
Return to Summary Table.
QEP Capture Period and Timer Latch register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 003Ch |
EQEP1_REG | 2321 003Ch |
EQEP2_REG | 2322 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QCTMRLAT | QCPRD | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | QCTMRLAT | R | 0h | EQEP
Capture Timer value can be latched into this register on two
events: |
15-0 | QCPRD | R/W | 0h | This field holds the period count value between the last successive EQEP position events. |
EQEP_QCPRDLAT is shown in Figure 12-2342 and described in Table 12-4445.
Return to Summary Table.
QEP Capture Period Latch register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 0040h |
EQEP1_REG | 2321 0040h |
EQEP2_REG | 2322 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | QCPRDLAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | QCPRDLAT | R | 0h | EQEP
capture period value can be latched into this register on two
events: |
EQEP_PID is shown in Figure 12-2343 and described in Table 12-4447.
Return to Summary Table.
Peripheral ID register
Instance | Physical Address |
---|---|
EQEP0_REG | 2320 005Ch |
EQEP1_REG | 2321 005Ch |
EQEP2_REG | 2322 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION | |||||||||||||||||||||||||||||||
44D31903h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVISION | R | 44D31903h | TI
Internal Data |