SPRUIM2H May   2020  â€“ October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Glossary
    3.     Related Documentation From Texas Instruments
    4.     6
    5.     Support Resources
    6.     Trademarks
    7.     Export Control Notice
  3. 1 Introduction
    1. 1.1 Device Overview
    2.     12
    3. 1.2 Functional Block Diagram
      1. 1.2.1 Module Allocation and Instances within Device Domains
    4. 1.3 Device MAIN Domain
      1. 1.3.1  Arm Cortex-A53 Subsystem (A53SS)
      2.      Arm Cortex-R5F Processor (R5FSS)
      3. 1.3.2  Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      4. 1.3.3  DDR 16-bit Subsystem (DDR16)
      5. 1.3.4  Region-based Address Translation Module (RAT)
      6. 1.3.5  Data Movement Subsystem (DMSS)
      7. 1.3.6  Mailbox (MAILBOX)
      8. 1.3.7  Spinlock (SPINLOCK)
      9. 1.3.8  Analog-to-Digital Converter (ADC)
      10. 1.3.9  General Purpose Input/Output Interface (GPIO)
      11. 1.3.10 Inter-Integrated Circuit Interface (I2C)
      12. 1.3.11 Serial Peripheral Interface (SPI)
      13. 1.3.12 Universal Asynchronous Receiver/Transmitter (UART)
      14. 1.3.13 3-port Gigabit Ethernet Switch (CPSW3G)
      15. 1.3.14 Peripheral Component Interconnect Express Subsystem (PCIE)
      16. 1.3.15 Serializer/Deserializer (SERDES)
      17. 1.3.16 Universal Serial Bus 3.1 Subsystem (USBSS)
      18. 1.3.17 General Purpose Memory Controller (GPMC)
      19. 1.3.18 Error Location Module (ELM)
      20. 1.3.19 Flash Subsystem (FSS) with Octal Serial Peripheral Interface (OSPI)
      21. 1.3.20 Multi-Media Card/Secure Digital Interface (MMCSD)
      22. 1.3.21 Enhanced Capture Module (ECAP)
      23. 1.3.22 Enhanced Pulse-Width Modulation Module (EPWM)
      24. 1.3.23 Enhanced Quadrature Encoder Pulse Module (EQEP)
      25. 1.3.24 Controller Area Network (MCAN)
      26. 1.3.25 Fast Serial Interface Receiver (FSI_RX)
      27. 1.3.26 Fast Serial Interface Transmitter (FSI_TX)
      28. 1.3.27 Timers
      29. 1.3.28 Internal Diagnostics Modules
    5. 1.4 Device MCU Domain
      1. 1.4.1 MCU Arm Cortex M4F Subsystem (MCU_M4FSS)
      2. 1.4.2 MCU General Purpose Input/Output Interface (MCU_GPIO)
      3. 1.4.3 MCU Inter-Integrated Circuit Interface (MCU_I2C)
      4. 1.4.4 MCU Multi-channel Serial Peripheral Interface (MCU_SPI)
      5. 1.4.5 MCU Universal Asynchronous Receiver/Transmitter (MCU_UART)
      6. 1.4.6 MCU Timers
      7. 1.4.7 MCU Internal Diagnostics Modules
    6. 1.5 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 Processors View Memory Map
    4. 2.4 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1  Terminology
    2. 3.2  System Interconnect Overview
    3. 3.3  Initiator/Target Connectivity
    4. 3.4  Interrupt Condition for Interconnect
    5. 3.5  IO Coherency Support
    6. 3.6  Quality of Service (QoS) Block
      1.      66
    7. 3.7  Route ID
      1.      68
    8. 3.8  ISC and Firewall
      1. 3.8.1 Initiator-Side Security Controls (ISC)
        1.       71
        2. 3.8.1.1 ISC MMR
      2. 3.8.2 Transaction Attributes for BCDMA and PktDMA Transactions
      3. 3.8.3 Firewall Block
        1.       75
        2. 3.8.3.1 Region Based Firewall Programming
    9. 3.9  System Interconnect Integration
      1. 3.9.1 Interconnect Integration in MAIN/MCU Domain
    10. 3.10 System Interconnect Registers
      1. 3.10.1 CBASS Registers
        1. 3.10.1.1    ERR_PID Registers
        2. 3.10.1.2    ERR_DESTINATION_ID Registers
        3. 3.10.1.3    ERR_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.1.4    ERR_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.1.5    ERR_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.1.6    ERR_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.1.7    ERR_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.1.8    ERR_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.1.9    ERR_ERR_INTR_RAW_STAT Registers
        10. 3.10.1.10   ERR_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.1.11   ERR_ERR_INTR_ENABLE_SET Registers
        12. 3.10.1.12   ERR_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.1.13   ERR_EOI Registers
        14. 3.10.1.14   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_CONTROL Registers
        15. 3.10.1.15   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_0 Registers
        16. 3.10.1.16   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_1 Registers
        17. 3.10.1.17   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_2 Registers
        18. 3.10.1.18   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_L Registers
        19. 3.10.1.19   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_H Registers
        20. 3.10.1.20   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_L Registers
        21. 3.10.1.21   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_H Registers
        22. 3.10.1.22   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_CONTROL Registers
        23. 3.10.1.23   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_0 Registers
        24. 3.10.1.24   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_1 Registers
        25. 3.10.1.25   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_2 Registers
        26. 3.10.1.26   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_L Registers
        27. 3.10.1.27   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_H Registers
        28. 3.10.1.28   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_L Registers
        29. 3.10.1.29   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_H Registers
        30. 3.10.1.30   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_CONTROL Registers
        31. 3.10.1.31   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_0 Registers
        32. 3.10.1.32   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_1 Registers
        33. 3.10.1.33   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_2 Registers
        34. 3.10.1.34   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_L Registers
        35. 3.10.1.35   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_H Registers
        36. 3.10.1.36   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_L Registers
        37. 3.10.1.37   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_H Registers
        38. 3.10.1.38   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_CONTROL Registers
        39. 3.10.1.39   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_0 Registers
        40. 3.10.1.40   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_1 Registers
        41. 3.10.1.41   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_2 Registers
        42. 3.10.1.42   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_L Registers
        43. 3.10.1.43   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_H Registers
        44. 3.10.1.44   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_L Registers
        45. 3.10.1.45   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_H Registers
        46. 3.10.1.46   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_CONTROL Registers
        47. 3.10.1.47   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_0 Registers
        48. 3.10.1.48   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_1 Registers
        49. 3.10.1.49   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_2 Registers
        50. 3.10.1.50   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_L Registers
        51. 3.10.1.51   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_H Registers
        52. 3.10.1.52   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_L Registers
        53. 3.10.1.53   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_H Registers
        54. 3.10.1.54   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_CONTROL Registers
        55. 3.10.1.55   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_0 Registers
        56. 3.10.1.56   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_1 Registers
        57. 3.10.1.57   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_2 Registers
        58. 3.10.1.58   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_L Registers
        59. 3.10.1.59   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_H Registers
        60. 3.10.1.60   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_L Registers
        61. 3.10.1.61   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_H Registers
        62. 3.10.1.62   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_CONTROL Registers
        63. 3.10.1.63   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_0 Registers
        64. 3.10.1.64   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_1 Registers
        65. 3.10.1.65   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_2 Registers
        66. 3.10.1.66   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_L Registers
        67. 3.10.1.67   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_H Registers
        68. 3.10.1.68   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_L Registers
        69. 3.10.1.69   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_H Registers
        70. 3.10.1.70   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_CONTROL Registers
        71. 3.10.1.71   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_0 Registers
        72. 3.10.1.72   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_1 Registers
        73. 3.10.1.73   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_2 Registers
        74. 3.10.1.74   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_L Registers
        75. 3.10.1.75   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_H Registers
        76. 3.10.1.76   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_L Registers
        77. 3.10.1.77   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_H Registers
        78. 3.10.1.78   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_CONTROL Registers
        79. 3.10.1.79   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_0 Registers
        80. 3.10.1.80   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_1 Registers
        81. 3.10.1.81   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_2 Registers
        82. 3.10.1.82   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_L Registers
        83. 3.10.1.83   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_H Registers
        84. 3.10.1.84   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_L Registers
        85. 3.10.1.85   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_H Registers
        86. 3.10.1.86   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_CONTROL Registers
        87. 3.10.1.87   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_0 Registers
        88. 3.10.1.88   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_1 Registers
        89. 3.10.1.89   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_2 Registers
        90. 3.10.1.90   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_L Registers
        91. 3.10.1.91   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_H Registers
        92. 3.10.1.92   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_L Registers
        93. 3.10.1.93   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_H Registers
        94. 3.10.1.94   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_CONTROL Registers
        95. 3.10.1.95   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_0 Registers
        96. 3.10.1.96   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_1 Registers
        97. 3.10.1.97   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_2 Registers
        98. 3.10.1.98   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_L Registers
        99. 3.10.1.99   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_H Registers
        100. 3.10.1.100  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_L Registers
        101. 3.10.1.101  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_H Registers
        102. 3.10.1.102  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_CONTROL Registers
        103. 3.10.1.103  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_0 Registers
        104. 3.10.1.104  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_1 Registers
        105. 3.10.1.105  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_2 Registers
        106. 3.10.1.106  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_L Registers
        107. 3.10.1.107  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_H Registers
        108. 3.10.1.108  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_L Registers
        109. 3.10.1.109  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_H Registers
        110. 3.10.1.110  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_CONTROL Registers
        111. 3.10.1.111  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_0 Registers
        112. 3.10.1.112  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_1 Registers
        113. 3.10.1.113  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_2 Registers
        114. 3.10.1.114  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_L Registers
        115. 3.10.1.115  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_H Registers
        116. 3.10.1.116  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_L Registers
        117. 3.10.1.117  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_H Registers
        118. 3.10.1.118  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_CONTROL Registers
        119. 3.10.1.119  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_0 Registers
        120. 3.10.1.120  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_1 Registers
        121. 3.10.1.121  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_2 Registers
        122. 3.10.1.122  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_L Registers
        123. 3.10.1.123  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_H Registers
        124. 3.10.1.124  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_L Registers
        125. 3.10.1.125  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_H Registers
        126. 3.10.1.126  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_CONTROL Registers
        127. 3.10.1.127  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_0 Registers
        128. 3.10.1.128  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_1 Registers
        129. 3.10.1.129  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_2 Registers
        130. 3.10.1.130  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_L Registers
        131. 3.10.1.131  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_H Registers
        132. 3.10.1.132  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_L Registers
        133. 3.10.1.133  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_H Registers
        134. 3.10.1.134  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_CONTROL Registers
        135. 3.10.1.135  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_0 Registers
        136. 3.10.1.136  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_1 Registers
        137. 3.10.1.137  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_2 Registers
        138. 3.10.1.138  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_L Registers
        139. 3.10.1.139  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_H Registers
        140. 3.10.1.140  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_L Registers
        141. 3.10.1.141  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_H Registers
        142. 3.10.1.142  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_CONTROL Registers
        143. 3.10.1.143  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_0 Registers
        144. 3.10.1.144  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_1 Registers
        145. 3.10.1.145  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_2 Registers
        146. 3.10.1.146  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_L Registers
        147. 3.10.1.147  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_H Registers
        148. 3.10.1.148  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_L Registers
        149. 3.10.1.149  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_H Registers
        150. 3.10.1.150  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_CONTROL Registers
        151. 3.10.1.151  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_0 Registers
        152. 3.10.1.152  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_1 Registers
        153. 3.10.1.153  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_2 Registers
        154. 3.10.1.154  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_L Registers
        155. 3.10.1.155  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_H Registers
        156. 3.10.1.156  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_L Registers
        157. 3.10.1.157  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_H Registers
        158. 3.10.1.158  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_CONTROL Registers
        159. 3.10.1.159  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_0 Registers
        160. 3.10.1.160  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_1 Registers
        161. 3.10.1.161  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_2 Registers
        162. 3.10.1.162  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_L Registers
        163. 3.10.1.163  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_H Registers
        164. 3.10.1.164  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_L Registers
        165. 3.10.1.165  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_H Registers
        166. 3.10.1.166  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_CONTROL Registers
        167. 3.10.1.167  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_0 Registers
        168. 3.10.1.168  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_1 Registers
        169. 3.10.1.169  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_2 Registers
        170. 3.10.1.170  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_L Registers
        171. 3.10.1.171  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_H Registers
        172. 3.10.1.172  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_L Registers
        173. 3.10.1.173  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_H Registers
        174. 3.10.1.174  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_CONTROL Registers
        175. 3.10.1.175  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_0 Registers
        176. 3.10.1.176  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_1 Registers
        177. 3.10.1.177  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_2 Registers
        178. 3.10.1.178  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_L Registers
        179. 3.10.1.179  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_H Registers
        180. 3.10.1.180  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_L Registers
        181. 3.10.1.181  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_H Registers
        182. 3.10.1.182  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_CONTROL Registers
        183. 3.10.1.183  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_0 Registers
        184. 3.10.1.184  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_1 Registers
        185. 3.10.1.185  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_2 Registers
        186. 3.10.1.186  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_L Registers
        187. 3.10.1.187  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_H Registers
        188. 3.10.1.188  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_L Registers
        189. 3.10.1.189  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_H Registers
        190. 3.10.1.190  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_CONTROL Registers
        191. 3.10.1.191  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_0 Registers
        192. 3.10.1.192  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_1 Registers
        193. 3.10.1.193  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_2 Registers
        194. 3.10.1.194  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_L Registers
        195. 3.10.1.195  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_H Registers
        196. 3.10.1.196  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_L Registers
        197. 3.10.1.197  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_H Registers
        198. 3.10.1.198  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_CONTROL Registers
        199. 3.10.1.199  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_0 Registers
        200. 3.10.1.200  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_1 Registers
        201. 3.10.1.201  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_2 Registers
        202. 3.10.1.202  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_L Registers
        203. 3.10.1.203  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_H Registers
        204. 3.10.1.204  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_L Registers
        205. 3.10.1.205  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_H Registers
        206. 3.10.1.206  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_CONTROL Registers
        207. 3.10.1.207  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_0 Registers
        208. 3.10.1.208  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_1 Registers
        209. 3.10.1.209  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_2 Registers
        210. 3.10.1.210  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_L Registers
        211. 3.10.1.211  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_H Registers
        212. 3.10.1.212  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_L Registers
        213. 3.10.1.213  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_H Registers
        214. 3.10.1.214  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_CONTROL Registers
        215. 3.10.1.215  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_0 Registers
        216. 3.10.1.216  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_1 Registers
        217. 3.10.1.217  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_2 Registers
        218. 3.10.1.218  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_L Registers
        219. 3.10.1.219  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_H Registers
        220. 3.10.1.220  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_L Registers
        221. 3.10.1.221  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_H Registers
        222. 3.10.1.222  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_CONTROL Registers
        223. 3.10.1.223  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_0 Registers
        224. 3.10.1.224  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_1 Registers
        225. 3.10.1.225  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_2 Registers
        226. 3.10.1.226  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_L Registers
        227. 3.10.1.227  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_H Registers
        228. 3.10.1.228  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_L Registers
        229. 3.10.1.229  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_H Registers
        230. 3.10.1.230  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_CONTROL Registers
        231. 3.10.1.231  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_0 Registers
        232. 3.10.1.232  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_1 Registers
        233. 3.10.1.233  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_2 Registers
        234. 3.10.1.234  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_L Registers
        235. 3.10.1.235  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_H Registers
        236. 3.10.1.236  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_L Registers
        237. 3.10.1.237  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_H Registers
        238. 3.10.1.238  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_CONTROL Registers
        239. 3.10.1.239  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_0 Registers
        240. 3.10.1.240  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_1 Registers
        241. 3.10.1.241  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_2 Registers
        242. 3.10.1.242  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_L Registers
        243. 3.10.1.243  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_H Registers
        244. 3.10.1.244  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_L Registers
        245. 3.10.1.245  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_H Registers
        246. 3.10.1.246  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_CONTROL Registers
        247. 3.10.1.247  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_0 Registers
        248. 3.10.1.248  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_1 Registers
        249. 3.10.1.249  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_2 Registers
        250. 3.10.1.250  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_L Registers
        251. 3.10.1.251  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_H Registers
        252. 3.10.1.252  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_L Registers
        253. 3.10.1.253  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_H Registers
        254. 3.10.1.254  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_CONTROL Registers
        255. 3.10.1.255  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_0 Registers
        256. 3.10.1.256  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_1 Registers
        257. 3.10.1.257  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_2 Registers
        258. 3.10.1.258  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_L Registers
        259. 3.10.1.259  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_H Registers
        260. 3.10.1.260  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_L Registers
        261. 3.10.1.261  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_H Registers
        262. 3.10.1.262  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_CONTROL Registers
        263. 3.10.1.263  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_0 Registers
        264. 3.10.1.264  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_1 Registers
        265. 3.10.1.265  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_2 Registers
        266. 3.10.1.266  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_L Registers
        267. 3.10.1.267  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_H Registers
        268. 3.10.1.268  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_L Registers
        269. 3.10.1.269  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_H Registers
        270. 3.10.1.270  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_CONTROL Registers
        271. 3.10.1.271  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_0 Registers
        272. 3.10.1.272  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_1 Registers
        273. 3.10.1.273  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_2 Registers
        274. 3.10.1.274  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_L Registers
        275. 3.10.1.275  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_H Registers
        276. 3.10.1.276  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_L Registers
        277. 3.10.1.277  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_H Registers
        278. 3.10.1.278  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_CONTROL Registers
        279. 3.10.1.279  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_0 Registers
        280. 3.10.1.280  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_1 Registers
        281. 3.10.1.281  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_2 Registers
        282. 3.10.1.282  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_L Registers
        283. 3.10.1.283  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_H Registers
        284. 3.10.1.284  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_L Registers
        285. 3.10.1.285  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_H Registers
        286. 3.10.1.286  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_CONTROL Registers
        287. 3.10.1.287  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_0 Registers
        288. 3.10.1.288  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_1 Registers
        289. 3.10.1.289  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_2 Registers
        290. 3.10.1.290  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_L Registers
        291. 3.10.1.291  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_H Registers
        292. 3.10.1.292  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_L Registers
        293. 3.10.1.293  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_H Registers
        294. 3.10.1.294  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_CONTROL Registers
        295. 3.10.1.295  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_0 Registers
        296. 3.10.1.296  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_1 Registers
        297. 3.10.1.297  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_2 Registers
        298. 3.10.1.298  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_L Registers
        299. 3.10.1.299  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_H Registers
        300. 3.10.1.300  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_L Registers
        301. 3.10.1.301  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_H Registers
        302. 3.10.1.302  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_CONTROL Registers
        303. 3.10.1.303  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_0 Registers
        304. 3.10.1.304  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_1 Registers
        305. 3.10.1.305  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_2 Registers
        306. 3.10.1.306  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_L Registers
        307. 3.10.1.307  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_H Registers
        308. 3.10.1.308  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_L Registers
        309. 3.10.1.309  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_H Registers
        310. 3.10.1.310  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_CONTROL Registers
        311. 3.10.1.311  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_0 Registers
        312. 3.10.1.312  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_1 Registers
        313. 3.10.1.313  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_2 Registers
        314. 3.10.1.314  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_L Registers
        315. 3.10.1.315  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_H Registers
        316. 3.10.1.316  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_L Registers
        317. 3.10.1.317  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_H Registers
        318. 3.10.1.318  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_CONTROL Registers
        319. 3.10.1.319  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_0 Registers
        320. 3.10.1.320  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_1 Registers
        321. 3.10.1.321  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_2 Registers
        322. 3.10.1.322  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_L Registers
        323. 3.10.1.323  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_H Registers
        324. 3.10.1.324  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_L Registers
        325. 3.10.1.325  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_H Registers
        326. 3.10.1.326  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_CONTROL Registers
        327. 3.10.1.327  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_0 Registers
        328. 3.10.1.328  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_1 Registers
        329. 3.10.1.329  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_2 Registers
        330. 3.10.1.330  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_L Registers
        331. 3.10.1.331  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_H Registers
        332. 3.10.1.332  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_L Registers
        333. 3.10.1.333  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_H Registers
        334. 3.10.1.334  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_CONTROL Registers
        335. 3.10.1.335  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_0 Registers
        336. 3.10.1.336  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_1 Registers
        337. 3.10.1.337  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_2 Registers
        338. 3.10.1.338  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_L Registers
        339. 3.10.1.339  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_H Registers
        340. 3.10.1.340  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_L Registers
        341. 3.10.1.341  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_H Registers
        342. 3.10.1.342  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_CONTROL Registers
        343. 3.10.1.343  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_0 Registers
        344. 3.10.1.344  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_1 Registers
        345. 3.10.1.345  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_2 Registers
        346. 3.10.1.346  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_L Registers
        347. 3.10.1.347  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_H Registers
        348. 3.10.1.348  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_L Registers
        349. 3.10.1.349  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_H Registers
        350. 3.10.1.350  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_CONTROL Registers
        351. 3.10.1.351  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_0 Registers
        352. 3.10.1.352  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_1 Registers
        353. 3.10.1.353  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_2 Registers
        354. 3.10.1.354  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_L Registers
        355. 3.10.1.355  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_H Registers
        356. 3.10.1.356  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_L Registers
        357. 3.10.1.357  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_H Registers
        358. 3.10.1.358  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_CONTROL Registers
        359. 3.10.1.359  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_0 Registers
        360. 3.10.1.360  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_1 Registers
        361. 3.10.1.361  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_2 Registers
        362. 3.10.1.362  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_L Registers
        363. 3.10.1.363  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_H Registers
        364. 3.10.1.364  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_L Registers
        365. 3.10.1.365  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_H Registers
        366. 3.10.1.366  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_CONTROL Registers
        367. 3.10.1.367  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_0 Registers
        368. 3.10.1.368  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_1 Registers
        369. 3.10.1.369  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_2 Registers
        370. 3.10.1.370  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_L Registers
        371. 3.10.1.371  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_H Registers
        372. 3.10.1.372  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_L Registers
        373. 3.10.1.373  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_H Registers
        374. 3.10.1.374  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_CONTROL Registers
        375. 3.10.1.375  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_0 Registers
        376. 3.10.1.376  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_1 Registers
        377. 3.10.1.377  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_2 Registers
        378. 3.10.1.378  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_L Registers
        379. 3.10.1.379  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_H Registers
        380. 3.10.1.380  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_L Registers
        381. 3.10.1.381  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_H Registers
        382. 3.10.1.382  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_CONTROL Registers
        383. 3.10.1.383  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_0 Registers
        384. 3.10.1.384  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_1 Registers
        385. 3.10.1.385  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_2 Registers
        386. 3.10.1.386  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_L Registers
        387. 3.10.1.387  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_H Registers
        388. 3.10.1.388  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_L Registers
        389. 3.10.1.389  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_H Registers
        390. 3.10.1.390  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_CONTROL Registers
        391. 3.10.1.391  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_0 Registers
        392. 3.10.1.392  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_1 Registers
        393. 3.10.1.393  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_2 Registers
        394. 3.10.1.394  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_L Registers
        395. 3.10.1.395  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_H Registers
        396. 3.10.1.396  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_L Registers
        397. 3.10.1.397  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_H Registers
        398. 3.10.1.398  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_CONTROL Registers
        399. 3.10.1.399  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_0 Registers
        400. 3.10.1.400  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_1 Registers
        401. 3.10.1.401  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_2 Registers
        402. 3.10.1.402  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_L Registers
        403. 3.10.1.403  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_H Registers
        404. 3.10.1.404  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_L Registers
        405. 3.10.1.405  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_H Registers
        406. 3.10.1.406  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_CONTROL Registers
        407. 3.10.1.407  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_0 Registers
        408. 3.10.1.408  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_1 Registers
        409. 3.10.1.409  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_2 Registers
        410. 3.10.1.410  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_L Registers
        411. 3.10.1.411  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_H Registers
        412. 3.10.1.412  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_L Registers
        413. 3.10.1.413  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_H Registers
        414. 3.10.1.414  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_CONTROL Registers
        415. 3.10.1.415  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_0 Registers
        416. 3.10.1.416  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_1 Registers
        417. 3.10.1.417  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_2 Registers
        418. 3.10.1.418  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_L Registers
        419. 3.10.1.419  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_H Registers
        420. 3.10.1.420  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_L Registers
        421. 3.10.1.421  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_H Registers
        422. 3.10.1.422  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_CONTROL Registers
        423. 3.10.1.423  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_0 Registers
        424. 3.10.1.424  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_1 Registers
        425. 3.10.1.425  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_2 Registers
        426. 3.10.1.426  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_L Registers
        427. 3.10.1.427  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_H Registers
        428. 3.10.1.428  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_L Registers
        429. 3.10.1.429  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_H Registers
        430. 3.10.1.430  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_CONTROL Registers
        431. 3.10.1.431  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_0 Registers
        432. 3.10.1.432  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_1 Registers
        433. 3.10.1.433  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_2 Registers
        434. 3.10.1.434  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_L Registers
        435. 3.10.1.435  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_H Registers
        436. 3.10.1.436  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_L Registers
        437. 3.10.1.437  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_H Registers
        438. 3.10.1.438  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_CONTROL Registers
        439. 3.10.1.439  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_0 Registers
        440. 3.10.1.440  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_1 Registers
        441. 3.10.1.441  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_2 Registers
        442. 3.10.1.442  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_L Registers
        443. 3.10.1.443  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_H Registers
        444. 3.10.1.444  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_L Registers
        445. 3.10.1.445  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_H Registers
        446. 3.10.1.446  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_CONTROL Registers
        447. 3.10.1.447  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_0 Registers
        448. 3.10.1.448  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_1 Registers
        449. 3.10.1.449  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_2 Registers
        450. 3.10.1.450  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_L Registers
        451. 3.10.1.451  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_H Registers
        452. 3.10.1.452  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_L Registers
        453. 3.10.1.453  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_H Registers
        454. 3.10.1.454  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_CONTROL Registers
        455. 3.10.1.455  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_0 Registers
        456. 3.10.1.456  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_1 Registers
        457. 3.10.1.457  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_2 Registers
        458. 3.10.1.458  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_L Registers
        459. 3.10.1.459  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_H Registers
        460. 3.10.1.460  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_L Registers
        461. 3.10.1.461  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_H Registers
        462. 3.10.1.462  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_CONTROL Registers
        463. 3.10.1.463  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_0 Registers
        464. 3.10.1.464  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_1 Registers
        465. 3.10.1.465  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_2 Registers
        466. 3.10.1.466  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_L Registers
        467. 3.10.1.467  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_H Registers
        468. 3.10.1.468  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_L Registers
        469. 3.10.1.469  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_H Registers
        470. 3.10.1.470  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_CONTROL Registers
        471. 3.10.1.471  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_0 Registers
        472. 3.10.1.472  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_1 Registers
        473. 3.10.1.473  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_2 Registers
        474. 3.10.1.474  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_L Registers
        475. 3.10.1.475  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_H Registers
        476. 3.10.1.476  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_L Registers
        477. 3.10.1.477  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_H Registers
        478. 3.10.1.478  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_CONTROL Registers
        479. 3.10.1.479  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_0 Registers
        480. 3.10.1.480  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_1 Registers
        481. 3.10.1.481  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_2 Registers
        482. 3.10.1.482  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_L Registers
        483. 3.10.1.483  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_H Registers
        484. 3.10.1.484  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_L Registers
        485. 3.10.1.485  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_H Registers
        486. 3.10.1.486  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_CONTROL Registers
        487. 3.10.1.487  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_0 Registers
        488. 3.10.1.488  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_1 Registers
        489. 3.10.1.489  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_2 Registers
        490. 3.10.1.490  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_L Registers
        491. 3.10.1.491  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_H Registers
        492. 3.10.1.492  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_L Registers
        493. 3.10.1.493  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_H Registers
        494. 3.10.1.494  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_CONTROL Registers
        495. 3.10.1.495  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_0 Registers
        496. 3.10.1.496  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_1 Registers
        497. 3.10.1.497  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_2 Registers
        498. 3.10.1.498  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_L Registers
        499. 3.10.1.499  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_H Registers
        500. 3.10.1.500  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_L Registers
        501. 3.10.1.501  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_H Registers
        502. 3.10.1.502  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_CONTROL Registers
        503. 3.10.1.503  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_0 Registers
        504. 3.10.1.504  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_1 Registers
        505. 3.10.1.505  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_2 Registers
        506. 3.10.1.506  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_L Registers
        507. 3.10.1.507  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_H Registers
        508. 3.10.1.508  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_L Registers
        509. 3.10.1.509  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_H Registers
        510. 3.10.1.510  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_CONTROL Registers
        511. 3.10.1.511  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_0 Registers
        512. 3.10.1.512  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_1 Registers
        513. 3.10.1.513  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_2 Registers
        514. 3.10.1.514  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_L Registers
        515. 3.10.1.515  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_H Registers
        516. 3.10.1.516  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_L Registers
        517. 3.10.1.517  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_H Registers
        518. 3.10.1.518  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_CONTROL Registers
        519. 3.10.1.519  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_0 Registers
        520. 3.10.1.520  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_1 Registers
        521. 3.10.1.521  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_2 Registers
        522. 3.10.1.522  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_L Registers
        523. 3.10.1.523  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_H Registers
        524. 3.10.1.524  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_L Registers
        525. 3.10.1.525  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_H Registers
        526. 3.10.1.526  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_CONTROL Registers
        527. 3.10.1.527  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_0 Registers
        528. 3.10.1.528  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_1 Registers
        529. 3.10.1.529  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_2 Registers
        530. 3.10.1.530  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_L Registers
        531. 3.10.1.531  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_H Registers
        532. 3.10.1.532  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_L Registers
        533. 3.10.1.533  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_H Registers
        534. 3.10.1.534  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_CONTROL Registers
        535. 3.10.1.535  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_0 Registers
        536. 3.10.1.536  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_1 Registers
        537. 3.10.1.537  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_2 Registers
        538. 3.10.1.538  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_L Registers
        539. 3.10.1.539  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_H Registers
        540. 3.10.1.540  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_L Registers
        541. 3.10.1.541  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_H Registers
        542. 3.10.1.542  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_CONTROL Registers
        543. 3.10.1.543  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_0 Registers
        544. 3.10.1.544  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_1 Registers
        545. 3.10.1.545  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_2 Registers
        546. 3.10.1.546  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_L Registers
        547. 3.10.1.547  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_H Registers
        548. 3.10.1.548  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_L Registers
        549. 3.10.1.549  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_H Registers
        550. 3.10.1.550  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_CONTROL Registers
        551. 3.10.1.551  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_0 Registers
        552. 3.10.1.552  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_1 Registers
        553. 3.10.1.553  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_2 Registers
        554. 3.10.1.554  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_L Registers
        555. 3.10.1.555  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_H Registers
        556. 3.10.1.556  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_L Registers
        557. 3.10.1.557  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_H Registers
        558. 3.10.1.558  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_CONTROL Registers
        559. 3.10.1.559  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_0 Registers
        560. 3.10.1.560  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_1 Registers
        561. 3.10.1.561  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_2 Registers
        562. 3.10.1.562  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_L Registers
        563. 3.10.1.563  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_H Registers
        564. 3.10.1.564  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_L Registers
        565. 3.10.1.565  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_H Registers
        566. 3.10.1.566  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_CONTROL Registers
        567. 3.10.1.567  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_0 Registers
        568. 3.10.1.568  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_1 Registers
        569. 3.10.1.569  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_2 Registers
        570. 3.10.1.570  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_L Registers
        571. 3.10.1.571  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_H Registers
        572. 3.10.1.572  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_L Registers
        573. 3.10.1.573  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_H Registers
        574. 3.10.1.574  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_CONTROL Registers
        575. 3.10.1.575  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_0 Registers
        576. 3.10.1.576  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_1 Registers
        577. 3.10.1.577  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_2 Registers
        578. 3.10.1.578  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_L Registers
        579. 3.10.1.579  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_H Registers
        580. 3.10.1.580  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_L Registers
        581. 3.10.1.581  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_H Registers
        582. 3.10.1.582  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_CONTROL Registers
        583. 3.10.1.583  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_0 Registers
        584. 3.10.1.584  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_1 Registers
        585. 3.10.1.585  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_2 Registers
        586. 3.10.1.586  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_L Registers
        587. 3.10.1.587  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_H Registers
        588. 3.10.1.588  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_L Registers
        589. 3.10.1.589  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_H Registers
        590. 3.10.1.590  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_CONTROL Registers
        591. 3.10.1.591  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_0 Registers
        592. 3.10.1.592  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_1 Registers
        593. 3.10.1.593  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_2 Registers
        594. 3.10.1.594  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_L Registers
        595. 3.10.1.595  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_H Registers
        596. 3.10.1.596  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_L Registers
        597. 3.10.1.597  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_H Registers
        598. 3.10.1.598  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_CONTROL Registers
        599. 3.10.1.599  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_0 Registers
        600. 3.10.1.600  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_1 Registers
        601. 3.10.1.601  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_2 Registers
        602. 3.10.1.602  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_L Registers
        603. 3.10.1.603  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_H Registers
        604. 3.10.1.604  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_L Registers
        605. 3.10.1.605  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_H Registers
        606. 3.10.1.606  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_CONTROL Registers
        607. 3.10.1.607  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_0 Registers
        608. 3.10.1.608  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_1 Registers
        609. 3.10.1.609  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_2 Registers
        610. 3.10.1.610  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_L Registers
        611. 3.10.1.611  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_H Registers
        612. 3.10.1.612  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_L Registers
        613. 3.10.1.613  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_H Registers
        614. 3.10.1.614  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_CONTROL Registers
        615. 3.10.1.615  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_0 Registers
        616. 3.10.1.616  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_1 Registers
        617. 3.10.1.617  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_2 Registers
        618. 3.10.1.618  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_L Registers
        619. 3.10.1.619  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_H Registers
        620. 3.10.1.620  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_L Registers
        621. 3.10.1.621  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_H Registers
        622. 3.10.1.622  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_CONTROL Registers
        623. 3.10.1.623  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_0 Registers
        624. 3.10.1.624  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_1 Registers
        625. 3.10.1.625  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_2 Registers
        626. 3.10.1.626  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_L Registers
        627. 3.10.1.627  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_H Registers
        628. 3.10.1.628  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_L Registers
        629. 3.10.1.629  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_H Registers
        630. 3.10.1.630  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_CONTROL Registers
        631. 3.10.1.631  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_0 Registers
        632. 3.10.1.632  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_1 Registers
        633. 3.10.1.633  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_2 Registers
        634. 3.10.1.634  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_L Registers
        635. 3.10.1.635  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_H Registers
        636. 3.10.1.636  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_L Registers
        637. 3.10.1.637  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_H Registers
        638. 3.10.1.638  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_CONTROL Registers
        639. 3.10.1.639  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_0 Registers
        640. 3.10.1.640  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_1 Registers
        641. 3.10.1.641  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_2 Registers
        642. 3.10.1.642  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_L Registers
        643. 3.10.1.643  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_H Registers
        644. 3.10.1.644  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_L Registers
        645. 3.10.1.645  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_H Registers
        646. 3.10.1.646  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_CONTROL Registers
        647. 3.10.1.647  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_0 Registers
        648. 3.10.1.648  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_1 Registers
        649. 3.10.1.649  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_2 Registers
        650. 3.10.1.650  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_L Registers
        651. 3.10.1.651  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_H Registers
        652. 3.10.1.652  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_L Registers
        653. 3.10.1.653  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_H Registers
        654. 3.10.1.654  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_CONTROL Registers
        655. 3.10.1.655  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_0 Registers
        656. 3.10.1.656  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_1 Registers
        657. 3.10.1.657  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_2 Registers
        658. 3.10.1.658  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_L Registers
        659. 3.10.1.659  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_H Registers
        660. 3.10.1.660  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_L Registers
        661. 3.10.1.661  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_H Registers
        662. 3.10.1.662  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_CONTROL Registers
        663. 3.10.1.663  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_0 Registers
        664. 3.10.1.664  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_1 Registers
        665. 3.10.1.665  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_2 Registers
        666. 3.10.1.666  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_L Registers
        667. 3.10.1.667  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_H Registers
        668. 3.10.1.668  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_L Registers
        669. 3.10.1.669  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_H Registers
        670. 3.10.1.670  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_CONTROL Registers
        671. 3.10.1.671  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_0 Registers
        672. 3.10.1.672  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_1 Registers
        673. 3.10.1.673  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_2 Registers
        674. 3.10.1.674  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_L Registers
        675. 3.10.1.675  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_H Registers
        676. 3.10.1.676  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_L Registers
        677. 3.10.1.677  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_H Registers
        678. 3.10.1.678  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_CONTROL Registers
        679. 3.10.1.679  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_0 Registers
        680. 3.10.1.680  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_1 Registers
        681. 3.10.1.681  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_2 Registers
        682. 3.10.1.682  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_L Registers
        683. 3.10.1.683  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_H Registers
        684. 3.10.1.684  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_L Registers
        685. 3.10.1.685  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_H Registers
        686. 3.10.1.686  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_CONTROL Registers
        687. 3.10.1.687  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_0 Registers
        688. 3.10.1.688  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_1 Registers
        689. 3.10.1.689  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_2 Registers
        690. 3.10.1.690  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_L Registers
        691. 3.10.1.691  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_H Registers
        692. 3.10.1.692  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_L Registers
        693. 3.10.1.693  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_H Registers
        694. 3.10.1.694  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_CONTROL Registers
        695. 3.10.1.695  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_0 Registers
        696. 3.10.1.696  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_1 Registers
        697. 3.10.1.697  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_2 Registers
        698. 3.10.1.698  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_L Registers
        699. 3.10.1.699  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_H Registers
        700. 3.10.1.700  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_L Registers
        701. 3.10.1.701  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_H Registers
        702. 3.10.1.702  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_CONTROL Registers
        703. 3.10.1.703  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_0 Registers
        704. 3.10.1.704  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_1 Registers
        705. 3.10.1.705  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_2 Registers
        706. 3.10.1.706  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_L Registers
        707. 3.10.1.707  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_H Registers
        708. 3.10.1.708  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_L Registers
        709. 3.10.1.709  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_H Registers
        710. 3.10.1.710  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_CONTROL Registers
        711. 3.10.1.711  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_0 Registers
        712. 3.10.1.712  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_1 Registers
        713. 3.10.1.713  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_2 Registers
        714. 3.10.1.714  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_L Registers
        715. 3.10.1.715  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_H Registers
        716. 3.10.1.716  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_L Registers
        717. 3.10.1.717  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_H Registers
        718. 3.10.1.718  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_CONTROL Registers
        719. 3.10.1.719  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_L Registers
        720. 3.10.1.720  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_H Registers
        721. 3.10.1.721  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_L Registers
        722. 3.10.1.722  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_H Registers
        723. 3.10.1.723  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_DEF_CONTROL Registers
        724. 3.10.1.724  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_CONTROL Registers
        725. 3.10.1.725  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_L Registers
        726. 3.10.1.726  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_H Registers
        727. 3.10.1.727  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_L Registers
        728. 3.10.1.728  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_H Registers
        729. 3.10.1.729  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_DEF_CONTROL Registers
        730. 3.10.1.730  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_CONTROL Registers
        731. 3.10.1.731  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_L Registers
        732. 3.10.1.732  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_H Registers
        733. 3.10.1.733  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_L Registers
        734. 3.10.1.734  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_H Registers
        735. 3.10.1.735  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_DEF_CONTROL Registers
        736. 3.10.1.736  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_CONTROL Registers
        737. 3.10.1.737  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_L Registers
        738. 3.10.1.738  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_H Registers
        739. 3.10.1.739  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_L Registers
        740. 3.10.1.740  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_H Registers
        741. 3.10.1.741  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_DEF_CONTROL Registers
        742. 3.10.1.742  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_CONTROL Registers
        743. 3.10.1.743  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        744. 3.10.1.744  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        745. 3.10.1.745  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        746. 3.10.1.746  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        747. 3.10.1.747  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_DEF_CONTROL Registers
        748. 3.10.1.748  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_CONTROL Registers
        749. 3.10.1.749  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        750. 3.10.1.750  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        751. 3.10.1.751  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        752. 3.10.1.752  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        753. 3.10.1.753  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_DEF_CONTROL Registers
        754. 3.10.1.754  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_CONTROL Registers
        755. 3.10.1.755  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        756. 3.10.1.756  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        757. 3.10.1.757  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        758. 3.10.1.758  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        759. 3.10.1.759  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_DEF_CONTROL Registers
        760. 3.10.1.760  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_CONTROL Registers
        761. 3.10.1.761  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        762. 3.10.1.762  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        763. 3.10.1.763  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        764. 3.10.1.764  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        765. 3.10.1.765  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_DEF_CONTROL Registers
        766. 3.10.1.766  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_CONTROL Registers
        767. 3.10.1.767  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        768. 3.10.1.768  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        769. 3.10.1.769  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        770. 3.10.1.770  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        771. 3.10.1.771  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_DEF_CONTROL Registers
        772. 3.10.1.772  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_CONTROL Registers
        773. 3.10.1.773  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        774. 3.10.1.774  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        775. 3.10.1.775  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        776. 3.10.1.776  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        777. 3.10.1.777  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_DEF_CONTROL Registers
        778. 3.10.1.778  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_CONTROL Registers
        779. 3.10.1.779  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        780. 3.10.1.780  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        781. 3.10.1.781  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        782. 3.10.1.782  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        783. 3.10.1.783  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_DEF_CONTROL Registers
        784. 3.10.1.784  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_CONTROL Registers
        785. 3.10.1.785  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        786. 3.10.1.786  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        787. 3.10.1.787  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        788. 3.10.1.788  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        789. 3.10.1.789  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_DEF_CONTROL Registers
        790. 3.10.1.790  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_CONTROL Registers
        791. 3.10.1.791  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        792. 3.10.1.792  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        793. 3.10.1.793  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        794. 3.10.1.794  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        795. 3.10.1.795  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_DEF_CONTROL Registers
        796. 3.10.1.796  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_CONTROL Registers
        797. 3.10.1.797  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        798. 3.10.1.798  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        799. 3.10.1.799  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        800. 3.10.1.800  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        801. 3.10.1.801  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_DEF_CONTROL Registers
        802. 3.10.1.802  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Registers
        803. 3.10.1.803  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        804. 3.10.1.804  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        805. 3.10.1.805  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        806. 3.10.1.806  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        807. 3.10.1.807  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Registers
        808. 3.10.1.808  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Registers
        809. 3.10.1.809  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Registers
        810. 3.10.1.810  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Registers
        811. 3.10.1.811  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Registers
        812. 3.10.1.812  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Registers
        813. 3.10.1.813  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Registers
        814. 3.10.1.814  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Registers
        815. 3.10.1.815  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Registers
        816. 3.10.1.816  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Registers
        817. 3.10.1.817  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Registers
        818. 3.10.1.818  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Registers
        819. 3.10.1.819  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Registers
        820. 3.10.1.820  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Registers
        821. 3.10.1.821  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Registers
        822. 3.10.1.822  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Registers
        823. 3.10.1.823  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Registers
        824. 3.10.1.824  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Registers
        825. 3.10.1.825  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Registers
        826. 3.10.1.826  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Registers
        827. 3.10.1.827  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Registers
        828. 3.10.1.828  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Registers
        829. 3.10.1.829  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Registers
        830. 3.10.1.830  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Registers
        831. 3.10.1.831  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Registers
        832. 3.10.1.832  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Registers
        833. 3.10.1.833  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Registers
        834. 3.10.1.834  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Registers
        835. 3.10.1.835  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Registers
        836. 3.10.1.836  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Registers
        837. 3.10.1.837  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Registers
        838. 3.10.1.838  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Registers
        839. 3.10.1.839  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Registers
        840. 3.10.1.840  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Registers
        841. 3.10.1.841  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Registers
        842. 3.10.1.842  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Registers
        843. 3.10.1.843  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Registers
        844. 3.10.1.844  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Registers
        845. 3.10.1.845  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Registers
        846. 3.10.1.846  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Registers
        847. 3.10.1.847  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Registers
        848. 3.10.1.848  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Registers
        849. 3.10.1.849  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Registers
        850. 3.10.1.850  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Registers
        851. 3.10.1.851  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Registers
        852. 3.10.1.852  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Registers
        853. 3.10.1.853  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Registers
        854. 3.10.1.854  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Registers
        855. 3.10.1.855  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Registers
        856. 3.10.1.856  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Registers
        857. 3.10.1.857  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Registers
        858. 3.10.1.858  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Registers
        859. 3.10.1.859  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Registers
        860. 3.10.1.860  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Registers
        861. 3.10.1.861  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Registers
        862. 3.10.1.862  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Registers
        863. 3.10.1.863  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Registers
        864. 3.10.1.864  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Registers
        865. 3.10.1.865  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Registers
        866. 3.10.1.866  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Registers
        867. 3.10.1.867  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Registers
        868. 3.10.1.868  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Registers
        869. 3.10.1.869  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Registers
        870. 3.10.1.870  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Registers
        871. 3.10.1.871  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Registers
        872. 3.10.1.872  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Registers
        873. 3.10.1.873  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Registers
        874. 3.10.1.874  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Registers
        875. 3.10.1.875  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Registers
        876. 3.10.1.876  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Registers
        877. 3.10.1.877  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Registers
        878. 3.10.1.878  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Registers
        879. 3.10.1.879  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Registers
        880. 3.10.1.880  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Registers
        881. 3.10.1.881  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Registers
        882. 3.10.1.882  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Registers
        883. 3.10.1.883  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Registers
        884. 3.10.1.884  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        885. 3.10.1.885  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        886. 3.10.1.886  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        887. 3.10.1.887  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        888. 3.10.1.888  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Registers
        889. 3.10.1.889  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Registers
        890. 3.10.1.890  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Registers
        891. 3.10.1.891  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Registers
        892. 3.10.1.892  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Registers
        893. 3.10.1.893  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Registers
        894. 3.10.1.894  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Registers
        895. 3.10.1.895  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Registers
        896. 3.10.1.896  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Registers
        897. 3.10.1.897  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Registers
        898. 3.10.1.898  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Registers
        899. 3.10.1.899  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Registers
        900. 3.10.1.900  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Registers
        901. 3.10.1.901  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Registers
        902. 3.10.1.902  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Registers
        903. 3.10.1.903  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Registers
        904. 3.10.1.904  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Registers
        905. 3.10.1.905  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Registers
        906. 3.10.1.906  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Registers
        907. 3.10.1.907  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Registers
        908. 3.10.1.908  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Registers
        909. 3.10.1.909  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Registers
        910. 3.10.1.910  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Registers
        911. 3.10.1.911  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Registers
        912. 3.10.1.912  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Registers
        913. 3.10.1.913  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Registers
        914. 3.10.1.914  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Registers
        915. 3.10.1.915  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Registers
        916. 3.10.1.916  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Registers
        917. 3.10.1.917  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Registers
        918. 3.10.1.918  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Registers
        919. 3.10.1.919  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Registers
        920. 3.10.1.920  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Registers
        921. 3.10.1.921  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Registers
        922. 3.10.1.922  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Registers
        923. 3.10.1.923  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Registers
        924. 3.10.1.924  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Registers
        925. 3.10.1.925  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Registers
        926. 3.10.1.926  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Registers
        927. 3.10.1.927  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Registers
        928. 3.10.1.928  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Registers
        929. 3.10.1.929  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Registers
        930. 3.10.1.930  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Registers
        931. 3.10.1.931  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Registers
        932. 3.10.1.932  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Registers
        933. 3.10.1.933  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Registers
        934. 3.10.1.934  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Registers
        935. 3.10.1.935  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Registers
        936. 3.10.1.936  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Registers
        937. 3.10.1.937  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Registers
        938. 3.10.1.938  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Registers
        939. 3.10.1.939  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Registers
        940. 3.10.1.940  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Registers
        941. 3.10.1.941  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Registers
        942. 3.10.1.942  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Registers
        943. 3.10.1.943  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Registers
        944. 3.10.1.944  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Registers
        945. 3.10.1.945  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Registers
        946. 3.10.1.946  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Registers
        947. 3.10.1.947  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Registers
        948. 3.10.1.948  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Registers
        949. 3.10.1.949  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Registers
        950. 3.10.1.950  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Registers
        951. 3.10.1.951  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Registers
        952. 3.10.1.952  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Registers
        953. 3.10.1.953  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Registers
        954. 3.10.1.954  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Registers
        955. 3.10.1.955  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Registers
        956. 3.10.1.956  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Registers
        957. 3.10.1.957  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Registers
        958. 3.10.1.958  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Registers
        959. 3.10.1.959  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Registers
        960. 3.10.1.960  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Registers
        961. 3.10.1.961  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Registers
        962. 3.10.1.962  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Registers
        963. 3.10.1.963  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Registers
        964. 3.10.1.964  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_CONTROL Registers
        965. 3.10.1.965  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_L Registers
        966. 3.10.1.966  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_H Registers
        967. 3.10.1.967  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_L Registers
        968. 3.10.1.968  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_H Registers
        969. 3.10.1.969  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_CONTROL Registers
        970. 3.10.1.970  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_L Registers
        971. 3.10.1.971  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_H Registers
        972. 3.10.1.972  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_L Registers
        973. 3.10.1.973  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_H Registers
        974. 3.10.1.974  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_CONTROL Registers
        975. 3.10.1.975  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_L Registers
        976. 3.10.1.976  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_H Registers
        977. 3.10.1.977  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_L Registers
        978. 3.10.1.978  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_H Registers
        979. 3.10.1.979  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_CONTROL Registers
        980. 3.10.1.980  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_L Registers
        981. 3.10.1.981  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_H Registers
        982. 3.10.1.982  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_L Registers
        983. 3.10.1.983  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_H Registers
        984. 3.10.1.984  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_CONTROL Registers
        985. 3.10.1.985  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_L Registers
        986. 3.10.1.986  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_H Registers
        987. 3.10.1.987  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_L Registers
        988. 3.10.1.988  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_H Registers
        989. 3.10.1.989  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_CONTROL Registers
        990. 3.10.1.990  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_L Registers
        991. 3.10.1.991  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_H Registers
        992. 3.10.1.992  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_L Registers
        993. 3.10.1.993  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_H Registers
        994. 3.10.1.994  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_CONTROL Registers
        995. 3.10.1.995  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_L Registers
        996. 3.10.1.996  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_H Registers
        997. 3.10.1.997  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_L Registers
        998. 3.10.1.998  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_H Registers
        999. 3.10.1.999  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_CONTROL Registers
        1000. 3.10.1.1000 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_L Registers
        1001. 3.10.1.1001 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_H Registers
        1002. 3.10.1.1002 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_L Registers
        1003. 3.10.1.1003 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_H Registers
        1004. 3.10.1.1004 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_DEF_CONTROL Registers
        1005. 3.10.1.1005 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_CONTROL Registers
        1006. 3.10.1.1006 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_L Registers
        1007. 3.10.1.1007 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_H Registers
        1008. 3.10.1.1008 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_L Registers
        1009. 3.10.1.1009 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_H Registers
        1010. 3.10.1.1010 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_CONTROL Registers
        1011. 3.10.1.1011 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_L Registers
        1012. 3.10.1.1012 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_H Registers
        1013. 3.10.1.1013 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_L Registers
        1014. 3.10.1.1014 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_H Registers
        1015. 3.10.1.1015 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_CONTROL Registers
        1016. 3.10.1.1016 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_L Registers
        1017. 3.10.1.1017 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_H Registers
        1018. 3.10.1.1018 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_L Registers
        1019. 3.10.1.1019 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_H Registers
        1020. 3.10.1.1020 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_CONTROL Registers
        1021. 3.10.1.1021 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_L Registers
        1022. 3.10.1.1022 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_H Registers
        1023. 3.10.1.1023 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_L Registers
        1024. 3.10.1.1024 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_H Registers
        1025. 3.10.1.1025 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_CONTROL Registers
        1026. 3.10.1.1026 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_L Registers
        1027. 3.10.1.1027 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_H Registers
        1028. 3.10.1.1028 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_L Registers
        1029. 3.10.1.1029 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_H Registers
        1030. 3.10.1.1030 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_CONTROL Registers
        1031. 3.10.1.1031 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_L Registers
        1032. 3.10.1.1032 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_H Registers
        1033. 3.10.1.1033 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_L Registers
        1034. 3.10.1.1034 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_H Registers
        1035. 3.10.1.1035 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_CONTROL Registers
        1036. 3.10.1.1036 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_L Registers
        1037. 3.10.1.1037 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_H Registers
        1038. 3.10.1.1038 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_L Registers
        1039. 3.10.1.1039 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_H Registers
        1040. 3.10.1.1040 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_CONTROL Registers
        1041. 3.10.1.1041 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_L Registers
        1042. 3.10.1.1042 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_H Registers
        1043. 3.10.1.1043 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_L Registers
        1044. 3.10.1.1044 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_H Registers
        1045. 3.10.1.1045 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_DEF_CONTROL Registers
        1046. 3.10.1.1046 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_CONTROL Registers
        1047. 3.10.1.1047 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_L Registers
        1048. 3.10.1.1048 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_H Registers
        1049. 3.10.1.1049 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_L Registers
        1050. 3.10.1.1050 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_H Registers
        1051. 3.10.1.1051 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_DEF_CONTROL Registers
        1052. 3.10.1.1052 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_CONTROL Registers
        1053. 3.10.1.1053 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_L Registers
        1054. 3.10.1.1054 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_H Registers
        1055. 3.10.1.1055 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_L Registers
        1056. 3.10.1.1056 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_H Registers
        1057. 3.10.1.1057 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_DEF_CONTROL Registers
        1058. 3.10.1.1058 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_CONTROL Registers
        1059. 3.10.1.1059 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_L Registers
        1060. 3.10.1.1060 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_H Registers
        1061. 3.10.1.1061 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_L Registers
        1062. 3.10.1.1062 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_H Registers
        1063. 3.10.1.1063 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_DEF_CONTROL Registers
        1064. 3.10.1.1064 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_CONTROL Registers
        1065. 3.10.1.1065 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_L Registers
        1066. 3.10.1.1066 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_H Registers
        1067. 3.10.1.1067 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_L Registers
        1068. 3.10.1.1068 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_H Registers
        1069. 3.10.1.1069 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_CONTROL Registers
        1070. 3.10.1.1070 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_L Registers
        1071. 3.10.1.1071 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_H Registers
        1072. 3.10.1.1072 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_L Registers
        1073. 3.10.1.1073 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_H Registers
        1074. 3.10.1.1074 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_CONTROL Registers
        1075. 3.10.1.1075 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_L Registers
        1076. 3.10.1.1076 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_H Registers
        1077. 3.10.1.1077 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_L Registers
        1078. 3.10.1.1078 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_H Registers
        1079. 3.10.1.1079 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_CONTROL Registers
        1080. 3.10.1.1080 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_L Registers
        1081. 3.10.1.1081 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_H Registers
        1082. 3.10.1.1082 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_L Registers
        1083. 3.10.1.1083 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_H Registers
        1084. 3.10.1.1084 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_CONTROL Registers
        1085. 3.10.1.1085 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_L Registers
        1086. 3.10.1.1086 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_H Registers
        1087. 3.10.1.1087 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_L Registers
        1088. 3.10.1.1088 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_H Registers
        1089. 3.10.1.1089 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_CONTROL Registers
        1090. 3.10.1.1090 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_L Registers
        1091. 3.10.1.1091 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_H Registers
        1092. 3.10.1.1092 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_L Registers
        1093. 3.10.1.1093 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_H Registers
        1094. 3.10.1.1094 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_CONTROL Registers
        1095. 3.10.1.1095 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_L Registers
        1096. 3.10.1.1096 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_H Registers
        1097. 3.10.1.1097 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_L Registers
        1098. 3.10.1.1098 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_H Registers
        1099. 3.10.1.1099 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_CONTROL Registers
        1100. 3.10.1.1100 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_L Registers
        1101. 3.10.1.1101 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_H Registers
        1102. 3.10.1.1102 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_L Registers
        1103. 3.10.1.1103 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_H Registers
        1104. 3.10.1.1104 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_DEF_CONTROL Registers
        1105. 3.10.1.1105 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_CONTROL Registers
        1106. 3.10.1.1106 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_L Registers
        1107. 3.10.1.1107 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_H Registers
        1108. 3.10.1.1108 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_L Registers
        1109. 3.10.1.1109 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_H Registers
        1110. 3.10.1.1110 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_CONTROL Registers
        1111. 3.10.1.1111 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_L Registers
        1112. 3.10.1.1112 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_H Registers
        1113. 3.10.1.1113 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_L Registers
        1114. 3.10.1.1114 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_H Registers
        1115. 3.10.1.1115 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_CONTROL Registers
        1116. 3.10.1.1116 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_L Registers
        1117. 3.10.1.1117 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_H Registers
        1118. 3.10.1.1118 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_L Registers
        1119. 3.10.1.1119 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_H Registers
        1120. 3.10.1.1120 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_CONTROL Registers
        1121. 3.10.1.1121 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_L Registers
        1122. 3.10.1.1122 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_H Registers
        1123. 3.10.1.1123 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_L Registers
        1124. 3.10.1.1124 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_H Registers
        1125. 3.10.1.1125 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_CONTROL Registers
        1126. 3.10.1.1126 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_L Registers
        1127. 3.10.1.1127 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_H Registers
        1128. 3.10.1.1128 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_L Registers
        1129. 3.10.1.1129 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_H Registers
        1130. 3.10.1.1130 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_CONTROL Registers
        1131. 3.10.1.1131 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_L Registers
        1132. 3.10.1.1132 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_H Registers
        1133. 3.10.1.1133 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_L Registers
        1134. 3.10.1.1134 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_H Registers
        1135. 3.10.1.1135 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_CONTROL Registers
        1136. 3.10.1.1136 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_L Registers
        1137. 3.10.1.1137 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_H Registers
        1138. 3.10.1.1138 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_L Registers
        1139. 3.10.1.1139 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_H Registers
        1140. 3.10.1.1140 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_CONTROL Registers
        1141. 3.10.1.1141 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_L Registers
        1142. 3.10.1.1142 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_H Registers
        1143. 3.10.1.1143 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_L Registers
        1144. 3.10.1.1144 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_H Registers
        1145. 3.10.1.1145 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_DEF_CONTROL Registers
        1146. 3.10.1.1146 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_CONTROL Registers
        1147. 3.10.1.1147 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_L Registers
        1148. 3.10.1.1148 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_H Registers
        1149. 3.10.1.1149 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_L Registers
        1150. 3.10.1.1150 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_H Registers
        1151. 3.10.1.1151 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_DEF_CONTROL Registers
        1152. 3.10.1.1152 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_CONTROL Registers
        1153. 3.10.1.1153 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_L Registers
        1154. 3.10.1.1154 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_H Registers
        1155. 3.10.1.1155 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_L Registers
        1156. 3.10.1.1156 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_H Registers
        1157. 3.10.1.1157 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_DEF_CONTROL Registers
        1158. 3.10.1.1158 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_CONTROL Registers
        1159. 3.10.1.1159 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_L Registers
        1160. 3.10.1.1160 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_H Registers
        1161. 3.10.1.1161 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_L Registers
        1162. 3.10.1.1162 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_H Registers
        1163. 3.10.1.1163 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_DEF_CONTROL Registers
        1164. 3.10.1.1164 GLB_PID Registers
        1165. 3.10.1.1165 GLB_DESTINATION_ID Registers
        1166. 3.10.1.1166 GLB_EXCEPTION_LOGGING_CONTROL Registers
        1167. 3.10.1.1167 GLB_EXCEPTION_LOGGING_HEADER0 Registers
        1168. 3.10.1.1168 GLB_EXCEPTION_LOGGING_HEADER1 Registers
        1169. 3.10.1.1169 GLB_EXCEPTION_LOGGING_DATA0 Registers
        1170. 3.10.1.1170 GLB_EXCEPTION_LOGGING_DATA1 Registers
        1171. 3.10.1.1171 GLB_EXCEPTION_LOGGING_DATA2 Registers
        1172. 3.10.1.1172 GLB_EXCEPTION_LOGGING_DATA3 Registers
        1173. 3.10.1.1173 GLB_EXCEPTION_PEND_SET Registers
        1174. 3.10.1.1174 GLB_EXCEPTION_PEND_CLEAR Registers
        1175. 3.10.1.1175 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_MAP0 Registers
        1176. 3.10.1.1176 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_MAP0 Registers
        1177. 3.10.1.1177 QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MAP0 Registers
        1178. 3.10.1.1178 QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MAP0 Registers
        1179. 3.10.1.1179 QOS_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_MAP0 Registers
        1180. 3.10.1.1180 QOS_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_MAP0 Registers
        1181. 3.10.1.1181 QOS_IPULSAR_LITE_MAIN_0_CPU0_RMST_MAP0 Registers
        1182. 3.10.1.1182 QOS_IPULSAR_LITE_MAIN_0_CPU0_WMST_MAP0 Registers
        1183. 3.10.1.1183 QOS_IPULSAR_LITE_MAIN_0_CPU1_RMST_MAP0 Registers
        1184. 3.10.1.1184 QOS_IPULSAR_LITE_MAIN_0_CPU1_WMST_MAP0 Registers
        1185. 3.10.1.1185 QOS_IPULSAR_LITE_MAIN_1_CPU0_RMST_MAP0 Registers
        1186. 3.10.1.1186 QOS_IPULSAR_LITE_MAIN_1_CPU0_WMST_MAP0 Registers
        1187. 3.10.1.1187 QOS_IPULSAR_LITE_MAIN_1_CPU1_RMST_MAP0 Registers
        1188. 3.10.1.1188 QOS_IPULSAR_LITE_MAIN_1_CPU1_WMST_MAP0 Registers
        1189. 3.10.1.1189 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP0 Registers
        1190. 3.10.1.1190 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP1 Registers
        1191. 3.10.1.1191 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP2 Registers
        1192. 3.10.1.1192 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP3 Registers
        1193. 3.10.1.1193 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP4 Registers
        1194. 3.10.1.1194 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP5 Registers
        1195. 3.10.1.1195 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP6 Registers
        1196. 3.10.1.1196 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP7 Registers
        1197. 3.10.1.1197 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP8 Registers
        1198. 3.10.1.1198 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP9 Registers
        1199. 3.10.1.1199 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP10 Registers
        1200. 3.10.1.1200 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP11 Registers
        1201. 3.10.1.1201 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP12 Registers
        1202. 3.10.1.1202 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP13 Registers
        1203. 3.10.1.1203 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP14 Registers
        1204. 3.10.1.1204 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP15 Registers
        1205. 3.10.1.1205 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP0 Registers
        1206. 3.10.1.1206 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP1 Registers
        1207. 3.10.1.1207 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP2 Registers
        1208. 3.10.1.1208 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP3 Registers
        1209. 3.10.1.1209 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP4 Registers
        1210. 3.10.1.1210 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP5 Registers
        1211. 3.10.1.1211 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP6 Registers
        1212. 3.10.1.1212 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP7 Registers
        1213. 3.10.1.1213 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP8 Registers
        1214. 3.10.1.1214 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP9 Registers
        1215. 3.10.1.1215 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP10 Registers
        1216. 3.10.1.1216 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP11 Registers
        1217. 3.10.1.1217 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP12 Registers
        1218. 3.10.1.1218 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP13 Registers
        1219. 3.10.1.1219 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP14 Registers
        1220. 3.10.1.1220 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP15 Registers
        1221. 3.10.1.1221 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP0 Registers
        1222. 3.10.1.1222 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP1 Registers
        1223. 3.10.1.1223 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP2 Registers
        1224. 3.10.1.1224 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP3 Registers
        1225. 3.10.1.1225 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP4 Registers
        1226. 3.10.1.1226 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP5 Registers
        1227. 3.10.1.1227 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP6 Registers
        1228. 3.10.1.1228 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP7 Registers
        1229. 3.10.1.1229 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP0 Registers
        1230. 3.10.1.1230 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP1 Registers
        1231. 3.10.1.1231 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP2 Registers
        1232. 3.10.1.1232 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP3 Registers
        1233. 3.10.1.1233 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP4 Registers
        1234. 3.10.1.1234 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP5 Registers
        1235. 3.10.1.1235 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP6 Registers
        1236. 3.10.1.1236 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP7 Registers
        1237. 3.10.1.1237 QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MAP0 Registers
        1238. 3.10.1.1238 QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MAP0 Registers
        1239. 3.10.1.1239 QOS_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_MAP0 Registers
        1240. 3.10.1.1240 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP0 Registers
        1241. 3.10.1.1241 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP1 Registers
        1242. 3.10.1.1242 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP2 Registers
        1243. 3.10.1.1243 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP3 Registers
        1244. 3.10.1.1244 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP4 Registers
        1245. 3.10.1.1245 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP5 Registers
        1246. 3.10.1.1246 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP6 Registers
        1247. 3.10.1.1247 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP7 Registers
        1248. 3.10.1.1248 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP0 Registers
        1249. 3.10.1.1249 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP1 Registers
        1250. 3.10.1.1250 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP2 Registers
        1251. 3.10.1.1251 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP3 Registers
        1252. 3.10.1.1252 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP4 Registers
        1253. 3.10.1.1253 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP5 Registers
        1254. 3.10.1.1254 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP6 Registers
        1255. 3.10.1.1255 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP7 Registers
        1256. 3.10.1.1256 QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_MAP0 Registers
        1257. 3.10.1.1257 QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_MAP0 Registers
        1258. 3.10.1.1258 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_CONTROL Registers
        1259. 3.10.1.1259 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_L Registers
        1260. 3.10.1.1260 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_H Registers
        1261. 3.10.1.1261 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_L Registers
        1262. 3.10.1.1262 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_H Registers
        1263. 3.10.1.1263 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_DEF_CONTROL Registers
        1264. 3.10.1.1264 QOS_IBLAZAR_MCU_0_VBUSP_M_MAP0 Registers
        1265. 3.10.1.1265 Access Table
      2. 3.10.2 CBASS_FW Registers
        1. 3.10.2.1  ERR_REGS_CBASS_FW_PID Registers
        2. 3.10.2.2  ERR_REGS_CBASS_FW_DESTINATION_ID Registers
        3. 3.10.2.3  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.2.4  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.2.5  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.2.6  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.2.7  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.2.8  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.2.9  ERR_REGS_CBASS_FW_ERR_INTR_RAW_STAT Registers
        10. 3.10.2.10 ERR_REGS_CBASS_FW_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.2.11 ERR_REGS_CBASS_FW_ERR_INTR_ENABLE_SET Registers
        12. 3.10.2.12 ERR_REGS_CBASS_FW_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.2.13 ERR_REGS_CBASS_FW_EOI Registers
        14. 3.10.2.14 Access Table
      3. 3.10.3 CBASS_INFRA Registers
        1. 3.10.3.1   ERR_REGS_CBASS_INFRA_PID Registers
        2. 3.10.3.2   ERR_REGS_CBASS_INFRA_DESTINATION_ID Registers
        3. 3.10.3.3   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.3.4   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.3.5   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.3.6   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.3.7   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.3.8   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.3.9   ERR_REGS_CBASS_INFRA_ERR_INTR_RAW_STAT Registers
        10. 3.10.3.10  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.3.11  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLE_SET Registers
        12. 3.10.3.12  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.3.13  ERR_REGS_CBASS_INFRA_EOI Registers
        14. 3.10.3.14  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_CONTROL Registers
        15. 3.10.3.15  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_0 Registers
        16. 3.10.3.16  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_1 Registers
        17. 3.10.3.17  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_2 Registers
        18. 3.10.3.18  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_L Registers
        19. 3.10.3.19  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_H Registers
        20. 3.10.3.20  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_L Registers
        21. 3.10.3.21  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_H Registers
        22. 3.10.3.22  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_CONTROL Registers
        23. 3.10.3.23  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_0 Registers
        24. 3.10.3.24  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_1 Registers
        25. 3.10.3.25  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_2 Registers
        26. 3.10.3.26  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_L Registers
        27. 3.10.3.27  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_H Registers
        28. 3.10.3.28  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_L Registers
        29. 3.10.3.29  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_H Registers
        30. 3.10.3.30  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_CONTROL Registers
        31. 3.10.3.31  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_0 Registers
        32. 3.10.3.32  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_1 Registers
        33. 3.10.3.33  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_2 Registers
        34. 3.10.3.34  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_L Registers
        35. 3.10.3.35  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_H Registers
        36. 3.10.3.36  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_L Registers
        37. 3.10.3.37  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_H Registers
        38. 3.10.3.38  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_CONTROL Registers
        39. 3.10.3.39  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_0 Registers
        40. 3.10.3.40  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_1 Registers
        41. 3.10.3.41  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_2 Registers
        42. 3.10.3.42  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_L Registers
        43. 3.10.3.43  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_H Registers
        44. 3.10.3.44  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_L Registers
        45. 3.10.3.45  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_H Registers
        46. 3.10.3.46  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_CONTROL Registers
        47. 3.10.3.47  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_0 Registers
        48. 3.10.3.48  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_1 Registers
        49. 3.10.3.49  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_2 Registers
        50. 3.10.3.50  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_L Registers
        51. 3.10.3.51  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_H Registers
        52. 3.10.3.52  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_L Registers
        53. 3.10.3.53  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_H Registers
        54. 3.10.3.54  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_CONTROL Registers
        55. 3.10.3.55  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_0 Registers
        56. 3.10.3.56  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_1 Registers
        57. 3.10.3.57  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_2 Registers
        58. 3.10.3.58  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_L Registers
        59. 3.10.3.59  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_H Registers
        60. 3.10.3.60  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_L Registers
        61. 3.10.3.61  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_H Registers
        62. 3.10.3.62  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_CONTROL Registers
        63. 3.10.3.63  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_0 Registers
        64. 3.10.3.64  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_1 Registers
        65. 3.10.3.65  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_2 Registers
        66. 3.10.3.66  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_L Registers
        67. 3.10.3.67  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_H Registers
        68. 3.10.3.68  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_L Registers
        69. 3.10.3.69  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_H Registers
        70. 3.10.3.70  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_CONTROL Registers
        71. 3.10.3.71  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_0 Registers
        72. 3.10.3.72  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_1 Registers
        73. 3.10.3.73  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_2 Registers
        74. 3.10.3.74  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_L Registers
        75. 3.10.3.75  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_H Registers
        76. 3.10.3.76  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_L Registers
        77. 3.10.3.77  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_H Registers
        78. 3.10.3.78  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_CONTROL Registers
        79. 3.10.3.79  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_0 Registers
        80. 3.10.3.80  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_1 Registers
        81. 3.10.3.81  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_2 Registers
        82. 3.10.3.82  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_L Registers
        83. 3.10.3.83  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_H Registers
        84. 3.10.3.84  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_L Registers
        85. 3.10.3.85  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_H Registers
        86. 3.10.3.86  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_CONTROL Registers
        87. 3.10.3.87  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_0 Registers
        88. 3.10.3.88  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_1 Registers
        89. 3.10.3.89  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_2 Registers
        90. 3.10.3.90  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_L Registers
        91. 3.10.3.91  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_H Registers
        92. 3.10.3.92  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_L Registers
        93. 3.10.3.93  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_H Registers
        94. 3.10.3.94  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_CONTROL Registers
        95. 3.10.3.95  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_0 Registers
        96. 3.10.3.96  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_1 Registers
        97. 3.10.3.97  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_2 Registers
        98. 3.10.3.98  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_L Registers
        99. 3.10.3.99  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_H Registers
        100. 3.10.3.100 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_L Registers
        101. 3.10.3.101 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_H Registers
        102. 3.10.3.102 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_CONTROL Registers
        103. 3.10.3.103 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_0 Registers
        104. 3.10.3.104 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_1 Registers
        105. 3.10.3.105 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_2 Registers
        106. 3.10.3.106 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_L Registers
        107. 3.10.3.107 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_H Registers
        108. 3.10.3.108 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_L Registers
        109. 3.10.3.109 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_H Registers
        110. 3.10.3.110 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_CONTROL Registers
        111. 3.10.3.111 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_0 Registers
        112. 3.10.3.112 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_1 Registers
        113. 3.10.3.113 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_2 Registers
        114. 3.10.3.114 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_L Registers
        115. 3.10.3.115 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_H Registers
        116. 3.10.3.116 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_L Registers
        117. 3.10.3.117 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_H Registers
        118. 3.10.3.118 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_CONTROL Registers
        119. 3.10.3.119 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_0 Registers
        120. 3.10.3.120 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_1 Registers
        121. 3.10.3.121 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_2 Registers
        122. 3.10.3.122 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_L Registers
        123. 3.10.3.123 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_H Registers
        124. 3.10.3.124 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_L Registers
        125. 3.10.3.125 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_H Registers
        126. 3.10.3.126 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_CONTROL Registers
        127. 3.10.3.127 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_0 Registers
        128. 3.10.3.128 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_1 Registers
        129. 3.10.3.129 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_2 Registers
        130. 3.10.3.130 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_L Registers
        131. 3.10.3.131 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_H Registers
        132. 3.10.3.132 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_L Registers
        133. 3.10.3.133 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_H Registers
        134. 3.10.3.134 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_CONTROL Registers
        135. 3.10.3.135 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_0 Registers
        136. 3.10.3.136 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_1 Registers
        137. 3.10.3.137 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_2 Registers
        138. 3.10.3.138 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_L Registers
        139. 3.10.3.139 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_H Registers
        140. 3.10.3.140 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_L Registers
        141. 3.10.3.141 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_H Registers
        142. 3.10.3.142 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_CONTROL Registers
        143. 3.10.3.143 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        144. 3.10.3.144 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        145. 3.10.3.145 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        146. 3.10.3.146 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        147. 3.10.3.147 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_DEF_CONTROL Registers
        148. 3.10.3.148 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_CONTROL Registers
        149. 3.10.3.149 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        150. 3.10.3.150 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        151. 3.10.3.151 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        152. 3.10.3.152 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        153. 3.10.3.153 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_DEF_CONTROL Registers
        154. 3.10.3.154 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_CONTROL Registers
        155. 3.10.3.155 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        156. 3.10.3.156 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        157. 3.10.3.157 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        158. 3.10.3.158 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        159. 3.10.3.159 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_DEF_CONTROL Registers
        160. 3.10.3.160 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_CONTROL Registers
        161. 3.10.3.161 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        162. 3.10.3.162 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        163. 3.10.3.163 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        164. 3.10.3.164 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        165. 3.10.3.165 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_DEF_CONTROL Registers
        166. 3.10.3.166 GLB_REGS_CBASS_INFRA_PID Registers
        167. 3.10.3.167 GLB_REGS_CBASS_INFRA_DESTINATION_ID Registers
        168. 3.10.3.168 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_CONTROL Registers
        169. 3.10.3.169 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER0 Registers
        170. 3.10.3.170 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER1 Registers
        171. 3.10.3.171 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA0 Registers
        172. 3.10.3.172 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA1 Registers
        173. 3.10.3.173 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA2 Registers
        174. 3.10.3.174 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA3 Registers
        175. 3.10.3.175 GLB_REGS_CBASS_INFRA_EXCEPTION_PEND_SET Registers
        176. 3.10.3.176 GLB_REGS_CBASS_INFRA_EXCEPTION_PEND_CLEAR Registers
        177. 3.10.3.177 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_MAP0 Registers
        178. 3.10.3.178 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_MAP0 Registers
        179. 3.10.3.179 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_MAP0 Registers
        180. 3.10.3.180 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_MAP0 Registers
        181. 3.10.3.181 Access Table
      4. 3.10.4 CBASS_DBG Registers
        1. 3.10.4.1  ERR_REGS_CBASS_DBG_PID Registers
        2. 3.10.4.2  ERR_REGS_CBASS_DBG_DESTINATION_ID Registers
        3. 3.10.4.3  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.4.4  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.4.5  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.4.6  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.4.7  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.4.8  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.4.9  ERR_REGS_CBASS_DBG_ERR_INTR_RAW_STAT Registers
        10. 3.10.4.10 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.4.11 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLE_SET Registers
        12. 3.10.4.12 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.4.13 ERR_REGS_CBASS_DBG_EOI Registers
        14. 3.10.4.14 Access Table
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Boot Terminology
    2. 4.2 Boot Process
      1. 4.2.1 Public ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
    3. 4.3 Boot Mode Pins
      1. 4.3.1 BOOTMODE Pin Mapping
        1. 4.3.1.1 Primary Boot Mode Selection and Configuration
        2. 4.3.1.2 Backup Boot Mode Selection and Configuration
    4. 4.4 Boot Modes
      1. 4.4.1  OSPI, xSPI, QSPI, SPI Boot
        1. 4.4.1.1 OSPI Boot
          1. 4.4.1.1.1 OSPI Bootloader Operation
            1. 4.4.1.1.1.1 OSPI Initialization Process
            2. 4.4.1.1.1.2 OSPI Loading Process
        2. 4.4.1.2 xSPI Boot
          1. 4.4.1.2.1 xSPI Bootloader Operation
        3. 4.4.1.3 QSPI Boot
          1. 4.4.1.3.1 QSPI Bootloader Operation
            1. 4.4.1.3.1.1 QSPI Initialization Process
            2. 4.4.1.3.1.2 QSPI Loading Process
        4. 4.4.1.4 SPI Boot
          1. 4.4.1.4.1 SPI Bootloader Operation
            1. 4.4.1.4.1.1 SPI Initialization Process
            2. 4.4.1.4.1.2 SPI Loading Process
      2. 4.4.2  I2C Boot
        1. 4.4.2.1 I2C Bootloader Operation
          1. 4.4.2.1.1 I2C Initialization Process
            1. 4.4.2.1.1.1 Block Size
            2. 4.4.2.1.1.2 Addressing
          2. 4.4.2.1.2 I2C Loading Process
            1. 4.4.2.1.2.1 Loading a Boot Image From EEPROM
      3. 4.4.3  SD Card Boot
        1. 4.4.3.1 SD Card Bootloader Operation
      4. 4.4.4  eMMC Boot
        1. 4.4.4.1 eMMC Bootloader Operation
      5. 4.4.5  Ethernet Boot
        1. 4.4.5.1 Ethernet Bootloader Operation
          1. 4.4.5.1.1 Ethernet Initialization Process
          2. 4.4.5.1.2 Ethernet Loading Process
            1. 4.4.5.1.2.1 Ethernet Boot Data Formats
              1. 4.4.5.1.2.1.1 Limitations
              2. 4.4.5.1.2.1.2 BOOTP Request
                1. 4.4.5.1.2.1.2.1 MAC Header (DIX)
                2. 4.4.5.1.2.1.2.2 IPv4 Header
                3. 4.4.5.1.2.1.2.3 UDP Header
                4. 4.4.5.1.2.1.2.4 BOOTP Payload
                5. 4.4.5.1.2.1.2.5 TFTP
          3. 4.4.5.1.3 Ethernet Hand Over Process
      6. 4.4.6  USB Boot
        1. 4.4.6.1 USB Bootloader Operation
          1. 4.4.6.1.1 USB-Specific Attributes
            1. 4.4.6.1.1.1 DFU Device Mode
        2. 4.4.6.2 Limitations for USB DFU and PCIe boot modes
      7. 4.4.7  PCIe Boot
        1. 4.4.7.1 PCIe Bootloader Operation
          1. 4.4.7.1.1 PCIe Initialization Process
          2. 4.4.7.1.2 PCIe Loading Process
        2. 4.4.7.2 Limitations for USB DFU and PCIe boot modes
      8. 4.4.8  UART Boot
        1. 4.4.8.1 UART Bootloader Operation
          1. 4.4.8.1.1 Initialization Process
          2. 4.4.8.1.2 UART Loading Process
            1. 4.4.8.1.2.1 UART XMODEM
          3. 4.4.8.1.3 UART Hand-Over Process
      9. 4.4.9  GPMC NOR Boot
        1. 4.4.9.1 GPMC NOR Bootloader Operation
          1. 4.4.9.1.1 GPMC NOR Initialization Process
          2. 4.4.9.1.2 GPMC NOR Loading Process
      10. 4.4.10 GPMC NAND Boot
        1. 4.4.10.1 GPMC NAND Bootloader Operation
      11. 4.4.11 No boot/Development boot
    5. 4.5 PLL Configuration
    6. 4.6 Boot Parameter Tables
      1. 4.6.1  Common Header
      2. 4.6.2  PLL Setup
      3. 4.6.3  OSPI/QSPI/SPI Boot Parameter Table
      4. 4.6.4  UART Boot Parameter Table
      5. 4.6.5  PCIe Boot Parameter Table
      6. 4.6.6  I2C Boot Parameter Table
      7. 4.6.7  MMCSD/eMMC Boot Parameter Table
      8. 4.6.8  Ethernet Boot Parameter Table
      9. 4.6.9  xSPI Boot Parameter Table
      10. 4.6.10 USB DFU Boot Parameter Table
      11. 4.6.11 USB MSC Boot Parameter Table
      12. 4.6.12 GPMC NOR Boot Parameter Table
      13. 4.6.13 GPMC NAND Boot Parameter Table
    7. 4.7 Boot Image Format
      1. 4.7.1 Overall Structure
      2. 4.7.2 X.509 Certificate
      3. 4.7.3 Organizational Identifier (OID)
      4. 4.7.4 X.509 Extensions Specific to Boot
        1. 4.7.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.7.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.7.5 Extended Boot Info Extension
        1. 4.7.5.1 Impact on HS Device
        2. 4.7.5.2 Extended Boot Info Details
        3. 4.7.5.3 Certificate / Component Types
        4. 4.7.5.4 Extended Boot Encryption Info
        5. 4.7.5.5 Component Ordering
        6. 4.7.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.7.5.7 Device Type and Extended Boot Extension
      6. 4.7.6 Generating X.509 Certificates
        1. 4.7.6.1 Key Generation
          1. 4.7.6.1.1 Degenerate RSA Keys
        2. 4.7.6.2 Configuration Script
        3. 4.7.6.3 Image Data
    8. 4.8 Boot Memory Maps
      1. 4.8.1 Memory Layout/MPU
      2. 4.8.2 Global Memory Addresses Used by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0
        1. 5.1.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Overview
        2. 5.1.1.2 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Integration
        3. 5.1.1.3 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.1.3.1 Description for CTRL_MMR0 and PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.1.3.1.1 Pad Configuration Registers
            2. 5.1.1.3.1.2 Kick Protection Registers
            3. 5.1.1.3.1.3 Proxy Addressing Registers
            4. 5.1.1.3.1.4 CTRL_MMR0 Module Interrupts
            5. 5.1.1.3.1.5 EHRPWM/EQEP Control and Status Registers
            6. 5.1.1.3.1.6 Clock Muxing and Division Registers
            7. 5.1.1.3.1.7 Ethernet Port Operation Control Registers
            8. 5.1.1.3.1.8 DDRSS Dynamic Frequency Change Registers
            9. 5.1.1.3.1.9 Device Feature Registers
        4. 5.1.1.4 Pad Configuration Registers
          1. 5.1.1.4.1 Pad Configuration Register Functional Description
          2. 5.1.1.4.2 Pad Configuration Ball Names
          3. 5.1.1.4.3 PADCFG_CTRL0_CFG0 Registers
        5. 5.1.1.5 CTRL_MMR0 Registers
        6. 5.1.1.6 MAIN_SEC_MMR0_CFG2 Registers
        7. 5.1.1.7 MAIN_SEC_MMR0_CFG0 Registers
      2. 5.1.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0
        1. 5.1.2.1 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.2.3.1.1 Pad Configuration Registers
            2. 5.1.2.3.1.2 Kick Protection Registers
            3. 5.1.2.3.1.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Module Interrupts
            4. 5.1.2.3.1.4 Clock Muxing and Division Registers
            5. 5.1.2.3.1.5 I/O Debounce Control Registers
            6. 5.1.2.3.1.6 PRG Related Registers
            7. 5.1.2.3.1.7 POK Module Registers
        4. 5.1.2.4 MCU_PADCFG_CTRL0_CFG0 Registers
        5. 5.1.2.5 MCU_CTRL_MMR0 Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power System Modules
          1. 5.2.2.1.1 Power OK (POK) Modules
            1. 5.2.2.1.1.1 Configuration Registers
          2. 5.2.2.1.2 Power on Reset (POR) Module
            1. 5.2.2.1.2.1 POR Overview
            2. 5.2.2.1.2.2 POR Integration
          3. 5.2.2.1.3 PoR/Reset Generator (PRG) Modules
            1. 5.2.2.1.3.1 PRG Overview
          4. 5.2.2.1.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.1.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.1.5.1 VTM Overview
              1. 5.2.2.1.5.1.1 VTM Features
              2. 5.2.2.1.5.1.2 VTM Not Supported Features
            2. 5.2.2.1.5.2 VTM Functional Description
              1. 5.2.2.1.5.2.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.1.5.2.1.1 10-bit Temperature Values Versus Temperature
          6. 5.2.2.1.6 Integrated Low-dropout Regulator (LDO)
            1. 5.2.2.1.6.1 SDIO LDO Overview
        2. 5.2.2.2 Power Control Modules
          1. 5.2.2.2.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.2.1.1 PSC Terminology
            2. 5.2.2.2.1.2 PSC Features
            3. 5.2.2.2.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.2.1.3.1 Device Power-Management Layout
            4. 5.2.2.2.1.4 PSC: Executing State Transitions
              1. 5.2.2.2.1.4.1 Power Domain State Transitions
              2. 5.2.2.2.1.4.2 Module State Transitions
              3. 5.2.2.2.1.4.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.2.1.4.4 Recommendations for Power Domain/Module Sequencing
            5. 5.2.2.2.1.5 LPSC Dependencies Overview
          2. 5.2.2.2.2 DMSC-L Power Management Overview
            1. 5.2.2.2.2.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Device Power States and Transitions
      4. 5.2.4 Thermal Management
      5. 5.2.5 Power Registers
        1. 5.2.5.1 VTM Registers
        2. 5.2.5.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Overview
        1. 5.3.1.1 MAIN Domain Supported Resets
        2. 5.3.1.2 MCU Domain Supported Resets
        3. 5.3.1.3 Reset Terminology
        4. 5.3.1.4 Reset Architecture
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
        1. 5.3.3.1 Reset Source Status Registers
        2. 5.3.3.2 MCU_RESETSTATz Status Pin
        3. 5.3.3.3 MCU_SAFETY_ERRORn Status Pin
        4. 5.3.3.4 MAIN_RESETSTATz Status Pin
        5. 5.3.3.5 MAIN_PORz_OUT Status Pin
      4. 5.3.4 Reset Controls
        1. 5.3.4.1 Reset Control Registers
        2. 5.3.4.2 Reset Isolation
      5. 5.3.5 Reset Details
        1. 5.3.5.1 POR Resets
          1. 5.3.5.1.1 SW_MAIN_PORz Reset
          2. 5.3.5.1.2 MCU_PORz Reset
        2. 5.3.5.2 Warm Resets
          1. 5.3.5.2.1 MAIN Domain Warm Reset Sequence Flow
          2. 5.3.5.2.2 MAIN_RESETz_REQ Reset
          3. 5.3.5.2.3 SW_MAIN_WARMRSTz Reset
          4. 5.3.5.2.4 MCU_RESETz Reset
          5. 5.3.5.2.5 SW_MCU_WARMRSTz Reset
        3. 5.3.5.3 DMSC-L Resets
          1. 5.3.5.3.1 DMSC_COLD_OUT_RST_n MAIN Reset
          2. 5.3.5.3.2 DMSC_WARM_OUT_RST_n MAIN Reset
          3. 5.3.5.3.3 DMSC_COLD_OUT_RST_n MCU Reset
        4. 5.3.5.4 VTM Thermal Alert Reset
        5. 5.3.5.5 MAIN ESM_ERRORz Reset
        6. 5.3.5.6 MCU ESM_ERRORz Reset
        7. 5.3.5.7 Reset - High Heating Value (HHV)
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 1800
          3. 5.4.3.1.3 OBSCLK0 Pin
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillator with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 MCU Domain PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRACF Type Output Clocks
              2. 5.4.5.4.1.2.2 PLL Lock
              3. 5.4.5.4.1.2.3 HSDIVIDER
              4. 5.4.5.4.1.2.4 ICG Module
              5. 5.4.5.4.1.2.5 PLL Power Down
              6. 5.4.5.4.1.2.6 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Clocking Registers
        1. 5.4.6.1 PLLCTRL0 Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 MCU_PLL0_CFG Registers
  8. 6 Processors and Accelerators
    1. 6.1 Arm Cortex-A53 Subsystem (A53SS)
      1. 6.1.1 A53SS Overview
        1. 6.1.1.1 A53SS Introduction
        2. 6.1.1.2 A53SS Features
      2. 6.1.2 A53SS Integration
      3. 6.1.3 A53SS Functional Description
        1. 6.1.3.1  A53SS Block Diagram
        2. 6.1.3.2  Arm Cortex-A53 Cluster
        3. 6.1.3.3  A53SS Interfaces and Async Bridges
        4. 6.1.3.4  A53SS Interrupts
          1. 6.1.3.4.1 A53SS Interrupt Inputs
          2. 6.1.3.4.2 A53SS Interrupt Outputs
        5. 6.1.3.5  A53SS Power Management and Clocking
          1. 6.1.3.5.1 A53SS Power Management
          2. 6.1.3.5.2 A53SS Clocking
        6. 6.1.3.6  A53SS Debug
        7. 6.1.3.7  A53SS Global and Debug Timestamps
        8. 6.1.3.8  A53SS Watchdog
        9. 6.1.3.9  A53SS Functional Safety - ECC Error Injection Support
          1. 6.1.3.9.1 A53 ECC Aggregators During Low Power States
          2. 6.1.3.9.2 Auto-initialization of Memories
          3. 6.1.3.9.3 A53 SRAM Safety
          4. 6.1.3.9.4 A53 SRAM ECC Aggregator Configurations
        10. 6.1.3.10 A53SS Boot
        11. 6.1.3.11 A53SS Interprocessor Communication
      4. 6.1.4 A53SS Registers
        1. 6.1.4.1 A53SS Registers
    2. 6.2 Arm Cortex R5F Subsystem (R5FSS)
      1. 6.2.1 R5FSS Overview
        1. 6.2.1.1 R5FSS Features
        2. 6.2.1.2 R5FSS Not Supported Features
      2. 6.2.2 R5FSS Integration
        1. 6.2.2.1 R5FSS Integration in MAIN Domain
      3. 6.2.3 R5FSS Functional Description
        1. 6.2.3.1  R5FSS Block Diagram
        2. 6.2.3.2  R5FSS Cortex-R5F Core
          1. 6.2.3.2.1 L1 Caches
          2. 6.2.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.2.3.2.3 R5FSS Special Signals
        3. 6.2.3.3  R5FSS Interfaces
          1. 6.2.3.3.1 Initiator Interfaces
          2. 6.2.3.3.2 Target Interfaces
        4. 6.2.3.4  R5FSS Power, Clocking and Reset
          1. 6.2.3.4.1 R5FSS Power
          2. 6.2.3.4.2 R5FSS Clocking
          3. 6.2.3.4.3 R5FSS Reset
        5. 6.2.3.5  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.2.3.5.1 VIM Overview
          2. 6.2.3.5.2 VIM Interrupt Inputs
          3. 6.2.3.5.3 VIM Interrupt Outputs
          4. 6.2.3.5.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.2.3.5.5 VIM Interrupt Prioritization
          6. 6.2.3.5.6 VIM ECC Support
          7. 6.2.3.5.7 VIM IDLE State
          8. 6.2.3.5.8 VIM Interrupt Handling
            1. 6.2.3.5.8.1 Servicing IRQ Through Vector Interface
            2. 6.2.3.5.8.2 Servicing IRQ Through MMR Interface
            3. 6.2.3.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.2.3.5.8.4 Servicing FIQ
            5. 6.2.3.5.8.5 Servicing FIQ (Alternative)
        6. 6.2.3.6  R5FSS Region Address Translation (RAT)
          1. 6.2.3.6.1 R5FSS Usage
          2. 6.2.3.6.2 RAT Function
          3. 6.2.3.6.3 How to use RAT Block in R5
          4. 6.2.3.6.4 Example of Using RAT to Access Full 36b SoC Memory Map
        7. 6.2.3.7  R5FSS ECC Support
        8. 6.2.3.8  R5FSS Memory View
        9. 6.2.3.9  R5FSS Interrupts
        10. 6.2.3.10 R5FSS Debug and Trace
        11. 6.2.3.11 R5FSS Boot Options
        12. 6.2.3.12 R5FSS Core Memory ECC Events
      4. 6.2.4 R5FSS Registers
        1. 6.2.4.1 R5FSS_MPIDR Register
        2. 6.2.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.2.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.2.4.4 R5FSS_VIM Registers
        5. 6.2.4.5 R5FSS_RAT Registers
        6. 6.2.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
    3. 6.3 Cortex-M4F Subsystem (MCU_M4FSS)
      1. 6.3.1 MCU_M4FSS Overview
        1. 6.3.1.1 MCU_M4FSS Features
        2. 6.3.1.2 MCU_M4FSS Not Supported Features
      2. 6.3.2 MCU_M4FSS Integration
      3. 6.3.3 MCU_M4FSS Functional Description
        1. 6.3.3.1  MCU_M4FSS Block Diagram
        2. 6.3.3.2  MCU_M4FSS Processor
        3. 6.3.3.3  MCU_M4FSS Internal RAMs
        4. 6.3.3.4  MCU_M4FSS Interfaces
        5. 6.3.3.5  MCU_M4FSS Power, Clocking and Reset
          1. 6.3.3.5.1 MCU_M4FSS Power
          2. 6.3.3.5.2 MCU_M4FSS Clocking
          3. 6.3.3.5.3 MCU_M4FSS Reset
        6. 6.3.3.6  MCU_M4FSS Memory View
        7. 6.3.3.7  MCU_M4FSS RAT
          1. 6.3.3.7.1 Why RAT is needed for M4F
          2. 6.3.3.7.2 RAT Function
          3. 6.3.3.7.3 How to use RAT Block in Blazar M4F
        8. 6.3.3.8  MCU_M4FSS ECC Support
        9. 6.3.3.9  MCU_M4FSS Interrupts
        10. 6.3.3.10 MCU_M4FSS Debug and Trace
        11. 6.3.3.11 MCU_M4FSS Time Sync
        12. 6.3.3.12 MCU_M4FSS SysTick
        13. 6.3.3.13 MCU_M4FSS Initialization
      4. 6.3.4 MCU_M4FSS Registers
        1. 6.3.4.1 M4FSS_RAT_0 Registers
          1. 6.3.4.1.1  RAT__CFG__MMRS_M4FSS_RAT_0_PID Registers
          2. 6.3.4.1.2  RAT__CFG__MMRS_M4FSS_RAT_0_CONFIG Registers
          3. 6.3.4.1.3  RAT__CFG__MMRS_M4FSS_RAT_0_DESTINATION_ID Registers
          4. 6.3.4.1.4  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_CONTROL Registers
          5. 6.3.4.1.5  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_HEADER0 Registers
          6. 6.3.4.1.6  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_HEADER1 Registers
          7. 6.3.4.1.7  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA0 Registers
          8. 6.3.4.1.8  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA1 Registers
          9. 6.3.4.1.9  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA2 Registers
          10. 6.3.4.1.10 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA3 Registers
          11. 6.3.4.1.11 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_PEND_SET Registers
          12. 6.3.4.1.12 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_PEND_CLEAR Registers
          13. 6.3.4.1.13 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_ENABLE_SET Registers
          14. 6.3.4.1.14 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_ENABLE_CLEAR Registers
          15. 6.3.4.1.15 RAT__CFG__MMRS_M4FSS_RAT_0_EOI_REG Registers
          16. 6.3.4.1.16 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_CTRL_J Registers
          17. 6.3.4.1.17 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_BASE_J Registers
          18. 6.3.4.1.18 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_TRANS_L_J Registers
          19. 6.3.4.1.19 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_TRANS_U_J Registers
          20. 6.3.4.1.20 Access Table
    4. 6.4 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      1. 6.4.1  PRU_ICSSG Overview
        1. 6.4.1.1 PRU_ICSSG Key Features
        2. 6.4.1.2 Not Supported Features
      2. 6.4.2  PRU_ICSSG Environment
        1. 6.4.2.1 PRU_ICSSG Internal Pinmux
          1.        PRU_ICSSG I/O Signals
        2. 6.4.2.2 PRU_ICSSG Fast GPIO pins
      3. 6.4.3  PRU_ICSSG Integration
        1.       PRU_ICSSG Clocks
      4. 6.4.4  PRU_ICSSG Top Level Resources Functional Description
        1. 6.4.4.1 PRU_ICSSG Reset Management
        2. 6.4.4.2 PRU_ICSSG Power and Clock Management
          1. 6.4.4.2.1 PRU_ICSSG CORE Clock Generation
          2. 6.4.4.2.2 PRU_ICSSG Idle State
          3. 6.4.4.2.3 PRU_ICSSG Protect
          4. 6.4.4.2.4 Module Clock Configurations at PRU_ICSSG Top Level
        3. 6.4.4.3 Other PRU_ICSSG Module Functional Registers at Subsystem Level
        4. 6.4.4.4 PRU_ICSSG Memory Maps
          1. 6.4.4.4.1 PRU_ICSSG Local Memory Map
            1. 6.4.4.4.1.1 PRU_ICSSG Local Instruction Memory Map
            2. 6.4.4.4.1.2 PRU_ICSSG Local Data Memory Map
          2. 6.4.4.4.2 PRU_ICSSG Global Memory Map
      5. 6.4.5  PRU_ICSSG PRU Cores
        1. 6.4.5.1 PRU Cores Overview
        2. 6.4.5.2 PRU Cores Functional Description
          1. 6.4.5.2.1 PRUs Constant Table
          2. 6.4.5.2.2 PRU Module Interface
            1. 6.4.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input
            2. 6.4.5.2.2.2 Event Interface Mapping (R31): PRU System Events
            3. 6.4.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module
              1. 6.4.5.2.2.3.1 PRU EGPIs Direct Input
              2. 6.4.5.2.2.3.2 PRU EGPIs 16-Bit Parallel Capture
              3. 6.4.5.2.2.3.3 PRU EGPIs 28-Bit Shift In
                1. 6.4.5.2.2.3.3.1 PRU EGPI Programming Model
              4. 6.4.5.2.2.3.4 General-Purpose Outputs (R30): Enhanced PRU GP Module
                1. 6.4.5.2.2.3.4.1 PRU EGPOs Direct Output
                2. 6.4.5.2.2.3.4.2 PRU EGPO Shift Out
                  1. 4.5.2.2.3.4.2.1 PRU EGPO Programming Model
              5. 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering
                1. 6.4.5.2.2.3.5.1 Sigma Delta Block Diagram and Signals
                2. 6.4.5.2.2.3.5.2 PRU R30 / R31 Interface
                3. 6.4.5.2.2.3.5.3 Sigma Delta Description
                4. 6.4.5.2.2.3.5.4 Sigma Delta Basic Programming Example
              6. 6.4.5.2.2.3.6 Three Channel Peripheral Interface
                1. 6.4.5.2.2.3.6.1 Peripheral Interface Block Diagram and Signal Configuration
                2. 6.4.5.2.2.3.6.2 PRU R30 and R31 Interface
                3. 6.4.5.2.2.3.6.3 Clock Generation
                  1. 4.5.2.2.3.6.3.1 Configuration
                  2. 4.5.2.2.3.6.3.2 Clock Output Start Conditions
                    1. 5.2.2.3.6.3.2.1 TX Mode (RX_EN = 0)
                    2. 5.2.2.3.6.3.2.2 RX Mode (RX_EN = 1)
                  3. 4.5.2.2.3.6.3.3 Stop Conditions
                4. 6.4.5.2.2.3.6.4 Three Peripheral Mode Basic Programming Model
                  1. 4.5.2.2.3.6.4.1 Clock Generation
                  2. 4.5.2.2.3.6.4.2 TX - Single Shot
                  3. 4.5.2.2.3.6.4.3 TX - Continuous FIFO Loading
                  4. 4.5.2.2.3.6.4.4 RX - Auto Arm or Non-Auto Arm
        3. 6.4.5.3 PRU_ICSSG RAM Index Allocation
      6. 6.4.6  PRU_ICSSG Broadside Accelerators
        1. 6.4.6.1 PRU_ICSSG Broadside Accelerators Overview
        2. 6.4.6.2 PRU_ICSSG Data Processing Accelerators Functional
          1. 6.4.6.2.1  PRU Multiplier with Accumulation (MPY/MAC)
            1. 6.4.6.2.1.1 PRU MAC Operations
              1. 6.4.6.2.1.1.1 PRU versus MAC Interface
              2. 6.4.6.2.1.1.2 Multiply only mode(default state), MAC_MODE = 0
                1. 6.4.6.2.1.1.2.1 Programming PRU MAC in "Multiply-ONLY" mode
              3. 6.4.6.2.1.1.3 Multiply and Accumulate Mode, MAC_MODE = 1
                1. 6.4.6.2.1.1.3.1 Programming PRU MAC in Multiply and Accumulate Mode
          2. 6.4.6.2.2  PRU CRC16/32 Module
            1. 6.4.6.2.2.1 PRU and CRC16/32 Interface
            2. 6.4.6.2.2.2 CRC Programming Model
            3. 6.4.6.2.2.3 PRU and CRC16/32 Interface (R9:R2)
          3. 6.4.6.2.3  PRU_ICSSG Scratch Pad Memory
            1. 6.4.6.2.3.1 PRU0/1 Scratch Pad Overview
            2. 6.4.6.2.3.2 PRU0 /1 Scratch Pad Operations
              1. 6.4.6.2.3.2.1 Optional XIN/XOUT Shift
              2. 6.4.6.2.3.2.2 Scratch Pad Operations Examples
          4. 6.4.6.2.4  PRU_ICSSG IPC Scratch Pad Memory
          5. 6.4.6.2.5  PRU_ICSSG Broadside (BS) RAM
            1. 6.4.6.2.5.1 Programming the BS RAM
          6. 6.4.6.2.6  PRU_ICSSG SUM32 Hardware Accelerator
          7. 6.4.6.2.7  PRU_ICSSG Byte Swap (BSWAP)
            1. 6.4.6.2.7.1 Byte Order Swap Function
            2. 6.4.6.2.7.2 4_8 Function
            3. 6.4.6.2.7.3 4_16 Function
          8. 6.4.6.2.8  PRU_ICSSG Task Manager
            1. 6.4.6.2.8.1 Task Manager General Purpose Mode
              1. 6.4.6.2.8.1.1 Tasks and Sub-tasks
              2. 6.4.6.2.8.1.2 Task Manager Hardware Context Switching
              3. 6.4.6.2.8.1.3 Task Manager Programming Guide
            2. 6.4.6.2.8.2 Task Manager RX_TX Mode
              1. 6.4.6.2.8.2.1 RX_TX Task Manager Features
              2. 6.4.6.2.8.2.2 Tasks and Sub-tasks
          9. 6.4.6.2.9  PRU_ICSSG Spinlock
            1. 6.4.6.2.9.1 PRU0/1 and RTU_PRU0/1 Spinlock Interface
          10. 6.4.6.2.10 PRU_ICSSG Filter Data Base (FDB)
            1. 6.4.6.2.10.1 FDB Modes of operation
              1. 6.4.6.2.10.1.1 FDB LUT: Hardware operation (HSR Disabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 0h)
              2. 6.4.6.2.10.1.2 FDB LUT: Hardware operation (HSR Enabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 1h)
              3. 6.4.6.2.10.1.3 8KB/16KB Generic broadside RAM mode of operation
                1. 6.4.6.2.10.1.3.1 Broadside (BS) Mapping
              4. 6.4.6.2.10.1.4 FDB General purpose compare mode operation
        3. 6.4.6.3 PRU_ICSSG Data Movement Accelerators Functional
          1. 6.4.6.3.1 PRU_ICSSG XFR2VBUS Hardware Accelerator
            1. 6.4.6.3.1.1 Blocking Conditions
            2. 6.4.6.3.1.2 Read Operation with Auto Disabled
            3. 6.4.6.3.1.3 Read Operation with Auto Enabled
            4. 6.4.6.3.1.4 Write Operation with Auto Disabled
            5. 6.4.6.3.1.5 RTU_PRU/ PRU to XFR2VBUS Interface
            6. 6.4.6.3.1.6 XFR2VBUS Programming Model
          2. 6.4.6.3.2 PRU_ICSSG XFRDMA Functional Operation
            1. 6.4.6.3.2.1 XFRDMA: XFR Bus
              1. 6.4.6.3.2.1.1 XFRDMA: XFR Status
              2. 6.4.6.3.2.1.2 XFRDMA: XFR Bus XOUT
              3. 6.4.6.3.2.1.3 XFRDMA: XFR Bus XOUXFRDMA Functional Operation T Alignment
              4. 6.4.6.3.2.1.4 XFRDMA: XFR Bus XIN
                1. 6.4.6.3.2.1.4.1 XFRDMA: XFR Bus XIN Alignment
            2. 6.4.6.3.2.2 XFRDMA: PSI-L Bus
              1. 6.4.6.3.2.2.1 PRU XFRPSI Mapping
            3. 6.4.6.3.2.3 XFRDMA: Temporary FIFOs
              1. 6.4.6.3.2.3.1 XFRDMA: FIFO Stalls
          3. 6.4.6.3.3 PRU_ICSSG XFR2TR Ring Accelerator
            1. 6.4.6.3.3.1 XFR2TR Programming Model
      7. 6.4.7  PRU_ICSSG Local INTC
        1. 6.4.7.1 PRU_ICSSG Interrupt Controller Functional Description
          1. 6.4.7.1.1 PRU_ICSSG Interrupt Controller Events
          2. 6.4.7.1.2 PRU_ICSSG Interrupt Controller System Events Flow
            1. 6.4.7.1.2.1 PRU_ICSSG Interrupt Processing
              1. 6.4.7.1.2.1.1 PRU_ICSSG Interrupt Enabling
            2. 6.4.7.1.2.2 PRU_ICSSG Interrupt Status Checking
            3. 6.4.7.1.2.3 PRU_ICSSG Interrupt Channel Mapping
              1. 6.4.7.1.2.3.1 PRU_ICSSG Host Interrupt Mapping
              2. 6.4.7.1.2.3.2 PRU_ICSSG Interrupt Prioritization
            4. 6.4.7.1.2.4 PRU_ICSSG Interrupt Nesting
            5. 6.4.7.1.2.5 PRU_ICSSG Interrupt Status Clearing
          3. 6.4.7.1.3 PRU_ICSSG Interrupt Disabling
        2. 6.4.7.2 PRU_ICSSG Interrupt Controller Basic Programming Model
        3. 6.4.7.3 PRU_ICSSG Interrupt Requests Mapping
      8. 6.4.8  PRU_ICSSG UART Module
        1. 6.4.8.1 PRU_ICSSG UART Overview
        2. 6.4.8.2 PRU_ICSSG UART Environment
          1. 6.4.8.2.1 PRU_ICSSG UART Pin Multiplexing
          2. 6.4.8.2.2 PRU_ICSSG UART Signal Descriptions
          3. 6.4.8.2.3 PRU_ICSSG UART Protocol Description and Data Format
            1. 6.4.8.2.3.1 PRU_ICSSG UART Transmission Protocol
            2. 6.4.8.2.3.2 PRU_ICSSG UART Reception Protocol
            3. 6.4.8.2.3.3 PRU_ICSSG UART Data Format
              1. 6.4.8.2.3.3.1 Frame Formatting
          4. 6.4.8.2.4 PRU_ICSSG UART Clock Generation and Control
        3. 6.4.8.3 PRU_ICSSG UART Functional Description
          1. 6.4.8.3.1 PRU_ICSSG UART Functional Block Diagram
          2. 6.4.8.3.2 PRU_ICSSG UART Reset Considerations
            1. 6.4.8.3.2.1 PRU_ICSSG UART Software Reset Considerations
            2. 6.4.8.3.2.2 PRU_ICSSG UART Hardware Reset Considerations
          3. 6.4.8.3.3 PRU_ICSSG UART Power Management
          4. 6.4.8.3.4 PRU_ICSSG UART Interrupt Support
            1. 6.4.8.3.4.1 PRU_ICSSG UART Interrupt Events and Requests
            2. 6.4.8.3.4.2 PRU_ICSSG UART Interrupt Multiplexing
          5. 6.4.8.3.5 2134
          6. 6.4.8.3.6 PRU_ICSSG UART DMA Event Support
          7. 6.4.8.3.7 PRU_ICSSG UART Operations
            1. 6.4.8.3.7.1 PRU_ICSSG UART FIFO Modes
              1. 6.4.8.3.7.1.1 PRU_ICSSG UART FIFO Interrupt Mode
              2. 6.4.8.3.7.1.2 PRU_ICSSG UART FIFO Poll Mode
            2. 6.4.8.3.7.2 PRU_ICSSG UART Autoflow Control
              1. 6.4.8.3.7.2.1 PRU_ICSSG UART Signal UART0_RTS Behavior
              2. 6.4.8.3.7.2.2 PRU_ICSSG UART Signal UART0_CTS Behavior
            3. 6.4.8.3.7.3 PRU_ICSSG UART Loopback Control
          8. 6.4.8.3.8 PRU_ICSSG UART Emulation Considerations
          9. 6.4.8.3.9 PRU_ICSSG UART Exception Processing
            1. 6.4.8.3.9.1 PRU_ICSSG UART Divisor Latch Not Programmed
            2. 6.4.8.3.9.2 Changing Operating Mode During Busy Serial Communication of PRU_ICSSG UART
      9. 6.4.9  PRU_ICSSG ECAP Module
        1. 6.4.9.1 PRU_ICSSG ECAP Functional Description
      10. 6.4.10 PRU_ICSSG PWM Module
        1. 6.4.10.1 PRU_ICSSG PWM Supported Features
        2. 6.4.10.2 PRU_ICSSG PWM States Overview
        3. 6.4.10.3 PRU_ICSSG PWM Trip State Logic
        4. 6.4.10.4 PRU_ICSSG PWM Glitch Filter
      11. 6.4.11 PRU_ICSSG MII_G_RT Module
        1. 6.4.11.1 PRU_ICSSG MII_G_RT Introduction
          1. 6.4.11.1.1 PRU_ICSSG MII_G_RT Features
          2. 6.4.11.1.2 Unsupported Features
          3. 6.4.11.1.3 PRU_ICSSG MII_G_RT Block Diagram
        2. 6.4.11.2 MII_G_RT Functional Description
          1. 6.4.11.2.1 MII_G_RT Data Path Configuration
            1. 6.4.11.2.1.1 Auto-forward with Optional PRU Snoop
            2. 6.4.11.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
            3. 6.4.11.2.1.3 32-byte Double Buffer or Ping-Pong Processing
          2. 6.4.11.2.2 MII_G_RT Definition and Terms
            1. 6.4.11.2.2.1 MII_G_RT Data Frame Structure
            2. 6.4.11.2.2.2 PRU R30 and R31
            3. 6.4.11.2.2.3 RX and TX L1 FIFO Data Movement
            4. 6.4.11.2.2.4 Receive CRC Computation
            5. 6.4.11.2.2.5 Transmit CRC Computation
            6. 6.4.11.2.2.6 Transmit CRC Computation for fragmented frames
          3. 6.4.11.2.3 RX MII Interface
            1. 6.4.11.2.3.1 RX MII Receive Data Latch
            2. 6.4.11.2.3.2 RX MII Start of Frame Detection
            3. 6.4.11.2.3.3 CRC Error Detection
            4. 6.4.11.2.3.4 RX Error Detection and Action
            5. 6.4.11.2.3.5 RX Data Path Options to PRU
            6. 6.4.11.2.3.6 RX MII Port → RX L1 FIFO → PRU
            7. 6.4.11.2.3.7 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
              1. 6.4.11.2.3.7.1 RX L2 Status in mode 0, none IET mode (when ICSS_G_CFG[2] RX_L2_G_EN= 0h)
              2. 6.4.11.2.3.7.2 2181
              3. 6.4.11.2.3.7.3 RX L2 Status for IET Type 1/Type 2 (when MII_G_RT_ICSS_G_CFG[2] RX_L2_G_EN = 1h)
              4. 6.4.11.2.3.7.4 2183
              5. 6.4.11.2.3.7.5 Broadside Stitch FIFO
              6. 6.4.11.2.3.7.6 MII_G_RT RX Classifier
                1. 6.4.11.2.3.7.6.1 RX Rate Counter Block
                2. 6.4.11.2.3.7.6.2 RX Rate Hit Mapping
                3. 6.4.11.2.3.7.6.3 Traffic Class Selector Block
                4. 6.4.11.2.3.7.6.4 PRU_ICSSG RX L2 Filter Block
                  1. 4.11.2.3.7.6.4.1 PRU_ICSSG RX L2 Filter Operation
                  2. 4.11.2.3.7.6.4.2 PRU_ICSSG RX L2 Filter - Type 1 (MAC Filter) Operation
                  3. 4.11.2.3.7.6.4.3 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Operation
                  4. 4.11.2.3.7.6.4.4 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Auto Restart operation
                  5. 4.11.2.3.7.6.4.5 RX SA Hash
                  6. 4.11.2.3.7.6.4.6 RX Connection Hash
          4. 6.4.11.2.4 PRU_ICSSG TX MII Interface
            1. 6.4.11.2.4.1 TX Data Path Options to TX L1 FIFO
              1. 6.4.11.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
                1. 6.4.11.2.4.1.1.1 TX L2 FIFO Features
                2. 6.4.11.2.4.1.1.2 2200
                3. 6.4.11.2.4.1.1.3 TX Insertion
                4. 6.4.11.2.4.1.1.4 TX Preemption
                  1. 4.11.2.4.1.1.4.1 TX Preemption Programming Model
              2. 6.4.11.2.4.1.2 RX L1 FIFO → TX L1 FIFO (Direct Connection) → TX MII Port
          5. 6.4.11.2.5 PRU R31 Command Interface
          6. 6.4.11.2.6 Other Configuration Options
            1. 6.4.11.2.6.1 Nibble and Byte Order
            2. 6.4.11.2.6.2 MII_G_RT Preamble Source
            3. 6.4.11.2.6.3 PRU and MII Port Multiplexer
              1. 6.4.11.2.6.3.1 Receive Multiplexer
              2. 6.4.11.2.6.3.2 Transmit Multiplexer
            4. 6.4.11.2.6.4 RX L2 Scratch Pad
        3. 6.4.11.3 PRU_ICSSG PA_STATS Module
          1. 6.4.11.3.1 Statistics Page
          2. 6.4.11.3.2 Statistics Collection Modes
            1. 6.4.11.3.2.1 Manual Read Mode
          3. 6.4.11.3.3 Clock Stop
      12. 6.4.12 PRU_ICSSG MII MDIO Module
        1. 6.4.12.1 PRU_ICSSG MII MDIO Overview
        2. 6.4.12.2 PRU_ICSSG MII MDIO Functional Description
          1. 6.4.12.2.1 MDIO Clause 22 Frame Formats
            1. 6.4.12.2.1.1 PRU-ICSSG MDIO Control and Interface Signals
          2. 6.4.12.2.2 MDIO Clause 45 Frame Formats
          3. 6.4.12.2.3 PRU_ICSSG MII MDIO Interractions
          4. 6.4.12.2.4 PRU_ICSSG MII MDIO Interrupts
            1. 6.4.12.2.4.1 Normal Mode ([30]STATECHANGEMODE = 0h)
            2. 6.4.12.2.4.2 State Change Mode ([30]STATECHANGEMODE = 1h)
          5. 6.4.12.2.5 Manual Mode
        3. 6.4.12.3 PRU_ICSSG MII MDIO Receive/Transmit Frame Host Software Interface
      13. 6.4.13 PRU_ICSSG IEP
        1. 6.4.13.1 PRU_ICSSG IEP Overview
        2. 6.4.13.2 PRU_ICSSG IEP Functional Description
          1. 6.4.13.2.1 PRU_ICSSG IEP Clock Generation
          2. 6.4.13.2.2 PRU_ICSSG IEP Timer
            1. 6.4.13.2.2.1 PRU_ICSSG IEP Timer Features
          3. 6.4.13.2.3 32-Bit Shadow Mode
          4. 6.4.13.2.4 PRU_ICSSG IEP Timer Basic Programming Sequence
          5. 6.4.13.2.5 Industrial Ethernet Mapping
          6. 6.4.13.2.6 PRU_ICSSG IEP Sync0/Sync1 Module
            1. 6.4.13.2.6.1 PRU_ICSSG IEP Sync0/Sync1 Features
            2. 6.4.13.2.6.2 PRU_ICSSG IEP Sync0/Sync1 Generation Modes
          7. 6.4.13.2.7 PRU_ICSSG IEP WatchDog
          8. 6.4.13.2.8 PRU_ICSSG IEP DIGIO
            1. 6.4.13.2.8.1 PRU_ICSSG IEP DIGIO Features
            2. 6.4.13.2.8.2 2245
            3. 6.4.13.2.8.3 PRU_ICSSG IEP DIGIO Block Diagrams
            4. 6.4.13.2.8.4 PRU_ICSSG IEP Basic Programming Model
      14. 6.4.14 PRU_ICSSG Registers
        1. 6.4.14.1  PRU_ICSSG PRU_CTRL, RTU_PRU_CTRL, and TX_PRU_CTRL Registers
        2. 6.4.14.2  PRU_ICSSG PRU_DEBUG, RTU_PRU_DEBUG, and TX_PRU_DEBUG Registers
        3. 6.4.14.3  PRU_ICSSG_ECC_AGGR Registers
        4. 6.4.14.4  PRU_ICSSG_DDRAM Registers
        5. 6.4.14.5  PRU_ICSSG_CFG Registers
        6. 6.4.14.6  PRU_ECAP_ECAP0 Registers
        7. 6.4.14.7  PRU_ICSS_INTC_INTC Registers
        8. 6.4.14.8  PRU_UART_UART0 Registers
        9. 6.4.14.9  PRU_IEP_IEP Registers
        10. 6.4.14.10 PRU_MDIO_MDIO Registers
        11. 6.4.14.11 PRU_MII_RT_MII_RT Registers
        12. 6.4.14.12 PRU_MII_G_RT_MII_G_RT Registers
        13. 6.4.14.13 PRU_ICSSG_PA_STAT Registers
        14. 6.4.14.14 PRU_ICSSG_PA_STAT_QSTAT Registers
        15. 6.4.14.15 PRU_ICSSG_PA_STAT_CSTAT Registers
        16. 6.4.14.16 PRU_PROT_PROTECT Registers
        17. 6.4.14.17 PRU_RAT_SLICE_RAT_SLICE Registers
        18. 6.4.14.18 PRU_TASKS_MGR_TASKS_MGR_PRU_RTU_TX Registers
        19. 6.4.14.19 PRU_ICSSG_RAM Registers
  9. 7 Interprocessor Communication (IPC)
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
      5. 7.1.5 Mailbox Registers
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
      5. 7.2.5 Spinlock Registers
  10. 8 Memory Controllers
    1. 8.1 DDR Subsystem (DDRSS)
      1. 8.1.1 DDRSS Overview
        1. 8.1.1.1 DDRSS Not Supported Features
      2. 8.1.2 DDRSS Environment
      3. 8.1.3 DDRSS Integration
        1. 8.1.3.1 DDRSS Integration in MAIN Domain
      4. 8.1.4 DDRSS Functional Description
        1. 8.1.4.1 Class of Service (CoS)
        2. 8.1.4.2 AXI Write Data All-Strobes
        3. 8.1.4.3 Inline ECC for SDRAM Data
          1. 8.1.4.3.1 ECC Cache
          2. 8.1.4.3.2 ECC Cache Flush
          3. 8.1.4.3.3 ECC Statistics
        4. 8.1.4.4 Address Alias Prevention
        5. 8.1.4.5 AXI Bus Timeout
        6. 8.1.4.6 DDRSS Interrupts
        7. 8.1.4.7 DDRSS Memory Regions
        8. 8.1.4.8 DDRSS Dynamic Frequency Change Interface
        9. 8.1.4.9 DDR Controller Functional Description
          1. 8.1.4.9.1 DDR PHY Interface (DFI)
          2. 8.1.4.9.2 Command Queue
            1. 8.1.4.9.2.1 Placement Logic
            2. 8.1.4.9.2.2 Command Selection Logic
          3. 8.1.4.9.3 Transaction Processing
          4. 8.1.4.9.4 Paging Policy
          5. 8.1.4.9.5 DDR Controller Initialization
      5. 8.1.5 DDR16SS Registers
        1. 8.1.5.1    REGS__SS_CFG__SSCFG_DDR16SS_SS_ID_REV_REG Registers
        2. 8.1.5.2    REGS__SS_CFG__SSCFG_DDR16SS_SS_CTL_REG Registers
        3. 8.1.5.3    REGS__SS_CFG__SSCFG_DDR16SS_V2A_CTL_REG Registers
        4. 8.1.5.4    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R1_MAT_REG Registers
        5. 8.1.5.5    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R2_MAT_REG Registers
        6. 8.1.5.6    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R3_MAT_REG Registers
        7. 8.1.5.7    REGS__SS_CFG__SSCFG_DDR16SS_V2A_DEF_PRI_MAP_REG Registers
        8. 8.1.5.8    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R1_PRI_MAP_REG Registers
        9. 8.1.5.9    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R2_PRI_MAP_REG Registers
        10. 8.1.5.10   REGS__SS_CFG__SSCFG_DDR16SS_V2A_R3_PRI_MAP_REG Registers
        11. 8.1.5.11   REGS__SS_CFG__SSCFG_DDR16SS_V2A_AERR_LOG1_REG Registers
        12. 8.1.5.12   REGS__SS_CFG__SSCFG_DDR16SS_V2A_AERR_LOG2_REG Registers
        13. 8.1.5.13   REGS__SS_CFG__SSCFG_DDR16SS_V2A_BUS_TO Registers
        14. 8.1.5.14   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_RAW_REG Registers
        15. 8.1.5.15   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_STAT_REG Registers
        16. 8.1.5.16   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_SET_REG Registers
        17. 8.1.5.17   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_CLR_REG Registers
        18. 8.1.5.18   REGS__SS_CFG__SSCFG_DDR16SS_V2A_EOI_REG Registers
        19. 8.1.5.19   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT_SEL_REG Registers
        20. 8.1.5.20   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT1_REG Registers
        21. 8.1.5.21   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT2_REG Registers
        22. 8.1.5.22   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT3_REG Registers
        23. 8.1.5.23   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT4_REG Registers
        24. 8.1.5.24   REGS__SS_CFG__SSCFG_DDR16SS_ECC_CTRL_REG Registers
        25. 8.1.5.25   REGS__SS_CFG__SSCFG_DDR16SS_ECC_RID_INDX_REG Registers
        26. 8.1.5.26   REGS__SS_CFG__SSCFG_DDR16SS_ECC_RID_VAL_REG Registers
        27. 8.1.5.27   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R0_STR_ADDR_REG Registers
        28. 8.1.5.28   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R0_END_ADDR_REG Registers
        29. 8.1.5.29   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R1_STR_ADDR_REG Registers
        30. 8.1.5.30   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R1_END_ADDR_REG Registers
        31. 8.1.5.31   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R2_STR_ADDR_REG Registers
        32. 8.1.5.32   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R2_END_ADDR_REG Registers
        33. 8.1.5.33   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_CNT_REG Registers
        34. 8.1.5.34   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_THRSH_REG Registers
        35. 8.1.5.35   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_ADR_LOG_REG Registers
        36. 8.1.5.36   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_MSK_LOG_REG Registers
        37. 8.1.5.37   REGS__SS_CFG__SSCFG_DDR16SS_ECC_2B_ERR_ADR_LOG_REG Registers
        38. 8.1.5.38   REGS__SS_CFG__SSCFG_DDR16SS_ECC_2B_ERR_MSK_LOG_REG Registers
        39. 8.1.5.39   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL1_REG Registers
        40. 8.1.5.40   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL2_REG Registers
        41. 8.1.5.41   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL3_REG Registers
        42. 8.1.5.42   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL4_REG Registers
        43. 8.1.5.43   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL5_REG Registers
        44. 8.1.5.44   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL6_REG Registers
        45. 8.1.5.45   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL7_REG Registers
        46. 8.1.5.46   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL8_REG Registers
        47. 8.1.5.47   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL9_REG Registers
        48. 8.1.5.48   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL10_REG Registers
        49. 8.1.5.49   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_STAT1_REG Registers
        50. 8.1.5.50   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_STAT2_REG Registers
        51. 8.1.5.51   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_0 Registers
        52. 8.1.5.52   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_1 Registers
        53. 8.1.5.53   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_2 Registers
        54. 8.1.5.54   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_3 Registers
        55. 8.1.5.55   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_4 Registers
        56. 8.1.5.56   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_5 Registers
        57. 8.1.5.57   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_6 Registers
        58. 8.1.5.58   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_7 Registers
        59. 8.1.5.59   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_8 Registers
        60. 8.1.5.60   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_9 Registers
        61. 8.1.5.61   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_10 Registers
        62. 8.1.5.62   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_11 Registers
        63. 8.1.5.63   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_12 Registers
        64. 8.1.5.64   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_13 Registers
        65. 8.1.5.65   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_14 Registers
        66. 8.1.5.66   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_15 Registers
        67. 8.1.5.67   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_16 Registers
        68. 8.1.5.68   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_17 Registers
        69. 8.1.5.69   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_18 Registers
        70. 8.1.5.70   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_19 Registers
        71. 8.1.5.71   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_20 Registers
        72. 8.1.5.72   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_21 Registers
        73. 8.1.5.73   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_22 Registers
        74. 8.1.5.74   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_23 Registers
        75. 8.1.5.75   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_24 Registers
        76. 8.1.5.76   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_25 Registers
        77. 8.1.5.77   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_26 Registers
        78. 8.1.5.78   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_27 Registers
        79. 8.1.5.79   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_28 Registers
        80. 8.1.5.80   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_29 Registers
        81. 8.1.5.81   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_30 Registers
        82. 8.1.5.82   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_31 Registers
        83. 8.1.5.83   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_32 Registers
        84. 8.1.5.84   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_33 Registers
        85. 8.1.5.85   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_34 Registers
        86. 8.1.5.86   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_35 Registers
        87. 8.1.5.87   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_36 Registers
        88. 8.1.5.88   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_37 Registers
        89. 8.1.5.89   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_38 Registers
        90. 8.1.5.90   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_39 Registers
        91. 8.1.5.91   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_40 Registers
        92. 8.1.5.92   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_41 Registers
        93. 8.1.5.93   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_42 Registers
        94. 8.1.5.94   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_43 Registers
        95. 8.1.5.95   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_44 Registers
        96. 8.1.5.96   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_45 Registers
        97. 8.1.5.97   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_46 Registers
        98. 8.1.5.98   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_47 Registers
        99. 8.1.5.99   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_48 Registers
        100. 8.1.5.100  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_49 Registers
        101. 8.1.5.101  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_50 Registers
        102. 8.1.5.102  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_51 Registers
        103. 8.1.5.103  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_52 Registers
        104. 8.1.5.104  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_53 Registers
        105. 8.1.5.105  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_54 Registers
        106. 8.1.5.106  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_55 Registers
        107. 8.1.5.107  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_56 Registers
        108. 8.1.5.108  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_57 Registers
        109. 8.1.5.109  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_58 Registers
        110. 8.1.5.110  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_59 Registers
        111. 8.1.5.111  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_60 Registers
        112. 8.1.5.112  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_61 Registers
        113. 8.1.5.113  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_62 Registers
        114. 8.1.5.114  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_63 Registers
        115. 8.1.5.115  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_64 Registers
        116. 8.1.5.116  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_65 Registers
        117. 8.1.5.117  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_66 Registers
        118. 8.1.5.118  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_67 Registers
        119. 8.1.5.119  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_68 Registers
        120. 8.1.5.120  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_69 Registers
        121. 8.1.5.121  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_70 Registers
        122. 8.1.5.122  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_71 Registers
        123. 8.1.5.123  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_72 Registers
        124. 8.1.5.124  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_73 Registers
        125. 8.1.5.125  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_74 Registers
        126. 8.1.5.126  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_75 Registers
        127. 8.1.5.127  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_76 Registers
        128. 8.1.5.128  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_77 Registers
        129. 8.1.5.129  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_78 Registers
        130. 8.1.5.130  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_79 Registers
        131. 8.1.5.131  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_80 Registers
        132. 8.1.5.132  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_81 Registers
        133. 8.1.5.133  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_82 Registers
        134. 8.1.5.134  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_83 Registers
        135. 8.1.5.135  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_84 Registers
        136. 8.1.5.136  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_85 Registers
        137. 8.1.5.137  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_86 Registers
        138. 8.1.5.138  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_87 Registers
        139. 8.1.5.139  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_88 Registers
        140. 8.1.5.140  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_89 Registers
        141. 8.1.5.141  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_90 Registers
        142. 8.1.5.142  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_91 Registers
        143. 8.1.5.143  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_92 Registers
        144. 8.1.5.144  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_93 Registers
        145. 8.1.5.145  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_94 Registers
        146. 8.1.5.146  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_95 Registers
        147. 8.1.5.147  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_96 Registers
        148. 8.1.5.148  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_97 Registers
        149. 8.1.5.149  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_98 Registers
        150. 8.1.5.150  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_99 Registers
        151. 8.1.5.151  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_100 Registers
        152. 8.1.5.152  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_101 Registers
        153. 8.1.5.153  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_102 Registers
        154. 8.1.5.154  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_103 Registers
        155. 8.1.5.155  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_104 Registers
        156. 8.1.5.156  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_105 Registers
        157. 8.1.5.157  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_106 Registers
        158. 8.1.5.158  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_107 Registers
        159. 8.1.5.159  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_108 Registers
        160. 8.1.5.160  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_109 Registers
        161. 8.1.5.161  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_110 Registers
        162. 8.1.5.162  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_111 Registers
        163. 8.1.5.163  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_112 Registers
        164. 8.1.5.164  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_113 Registers
        165. 8.1.5.165  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_114 Registers
        166. 8.1.5.166  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_115 Registers
        167. 8.1.5.167  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_116 Registers
        168. 8.1.5.168  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_117 Registers
        169. 8.1.5.169  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_118 Registers
        170. 8.1.5.170  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_119 Registers
        171. 8.1.5.171  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_120 Registers
        172. 8.1.5.172  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_121 Registers
        173. 8.1.5.173  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_122 Registers
        174. 8.1.5.174  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_123 Registers
        175. 8.1.5.175  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_124 Registers
        176. 8.1.5.176  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_125 Registers
        177. 8.1.5.177  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_126 Registers
        178. 8.1.5.178  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_127 Registers
        179. 8.1.5.179  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_128 Registers
        180. 8.1.5.180  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_129 Registers
        181. 8.1.5.181  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_130 Registers
        182. 8.1.5.182  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_131 Registers
        183. 8.1.5.183  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_132 Registers
        184. 8.1.5.184  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_133 Registers
        185. 8.1.5.185  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_134 Registers
        186. 8.1.5.186  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_135 Registers
        187. 8.1.5.187  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_136 Registers
        188. 8.1.5.188  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_137 Registers
        189. 8.1.5.189  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_138 Registers
        190. 8.1.5.190  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_139 Registers
        191. 8.1.5.191  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_140 Registers
        192. 8.1.5.192  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_141 Registers
        193. 8.1.5.193  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_142 Registers
        194. 8.1.5.194  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_143 Registers
        195. 8.1.5.195  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_144 Registers
        196. 8.1.5.196  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_145 Registers
        197. 8.1.5.197  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_146 Registers
        198. 8.1.5.198  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_147 Registers
        199. 8.1.5.199  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_148 Registers
        200. 8.1.5.200  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_149 Registers
        201. 8.1.5.201  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_150 Registers
        202. 8.1.5.202  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_151 Registers
        203. 8.1.5.203  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_152 Registers
        204. 8.1.5.204  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_153 Registers
        205. 8.1.5.205  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_154 Registers
        206. 8.1.5.206  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_155 Registers
        207. 8.1.5.207  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_156 Registers
        208. 8.1.5.208  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_157 Registers
        209. 8.1.5.209  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_158 Registers
        210. 8.1.5.210  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_159 Registers
        211. 8.1.5.211  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_160 Registers
        212. 8.1.5.212  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_161 Registers
        213. 8.1.5.213  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_162 Registers
        214. 8.1.5.214  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_163 Registers
        215. 8.1.5.215  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_164 Registers
        216. 8.1.5.216  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_165 Registers
        217. 8.1.5.217  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_166 Registers
        218. 8.1.5.218  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_167 Registers
        219. 8.1.5.219  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_168 Registers
        220. 8.1.5.220  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_169 Registers
        221. 8.1.5.221  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_170 Registers
        222. 8.1.5.222  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_171 Registers
        223. 8.1.5.223  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_172 Registers
        224. 8.1.5.224  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_173 Registers
        225. 8.1.5.225  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_174 Registers
        226. 8.1.5.226  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_175 Registers
        227. 8.1.5.227  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_176 Registers
        228. 8.1.5.228  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_177 Registers
        229. 8.1.5.229  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_178 Registers
        230. 8.1.5.230  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_179 Registers
        231. 8.1.5.231  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_180 Registers
        232. 8.1.5.232  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_181 Registers
        233. 8.1.5.233  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_182 Registers
        234. 8.1.5.234  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_183 Registers
        235. 8.1.5.235  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_184 Registers
        236. 8.1.5.236  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_185 Registers
        237. 8.1.5.237  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_186 Registers
        238. 8.1.5.238  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_187 Registers
        239. 8.1.5.239  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_188 Registers
        240. 8.1.5.240  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_189 Registers
        241. 8.1.5.241  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_190 Registers
        242. 8.1.5.242  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_191 Registers
        243. 8.1.5.243  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_192 Registers
        244. 8.1.5.244  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_193 Registers
        245. 8.1.5.245  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_194 Registers
        246. 8.1.5.246  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_195 Registers
        247. 8.1.5.247  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_196 Registers
        248. 8.1.5.248  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_197 Registers
        249. 8.1.5.249  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_198 Registers
        250. 8.1.5.250  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_199 Registers
        251. 8.1.5.251  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_200 Registers
        252. 8.1.5.252  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_201 Registers
        253. 8.1.5.253  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_202 Registers
        254. 8.1.5.254  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_203 Registers
        255. 8.1.5.255  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_204 Registers
        256. 8.1.5.256  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_205 Registers
        257. 8.1.5.257  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_206 Registers
        258. 8.1.5.258  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_207 Registers
        259. 8.1.5.259  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_208 Registers
        260. 8.1.5.260  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_209 Registers
        261. 8.1.5.261  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_210 Registers
        262. 8.1.5.262  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_211 Registers
        263. 8.1.5.263  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_212 Registers
        264. 8.1.5.264  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_213 Registers
        265. 8.1.5.265  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_214 Registers
        266. 8.1.5.266  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_215 Registers
        267. 8.1.5.267  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_216 Registers
        268. 8.1.5.268  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_217 Registers
        269. 8.1.5.269  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_218 Registers
        270. 8.1.5.270  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_219 Registers
        271. 8.1.5.271  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_220 Registers
        272. 8.1.5.272  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_221 Registers
        273. 8.1.5.273  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_222 Registers
        274. 8.1.5.274  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_223 Registers
        275. 8.1.5.275  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_224 Registers
        276. 8.1.5.276  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_225 Registers
        277. 8.1.5.277  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_226 Registers
        278. 8.1.5.278  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_227 Registers
        279. 8.1.5.279  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_228 Registers
        280. 8.1.5.280  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_229 Registers
        281. 8.1.5.281  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_230 Registers
        282. 8.1.5.282  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_231 Registers
        283. 8.1.5.283  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_232 Registers
        284. 8.1.5.284  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_233 Registers
        285. 8.1.5.285  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_234 Registers
        286. 8.1.5.286  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_235 Registers
        287. 8.1.5.287  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_236 Registers
        288. 8.1.5.288  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_237 Registers
        289. 8.1.5.289  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_238 Registers
        290. 8.1.5.290  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_239 Registers
        291. 8.1.5.291  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_240 Registers
        292. 8.1.5.292  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_241 Registers
        293. 8.1.5.293  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_242 Registers
        294. 8.1.5.294  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_243 Registers
        295. 8.1.5.295  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_244 Registers
        296. 8.1.5.296  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_245 Registers
        297. 8.1.5.297  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_246 Registers
        298. 8.1.5.298  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_247 Registers
        299. 8.1.5.299  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_248 Registers
        300. 8.1.5.300  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_249 Registers
        301. 8.1.5.301  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_250 Registers
        302. 8.1.5.302  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_251 Registers
        303. 8.1.5.303  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_252 Registers
        304. 8.1.5.304  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_253 Registers
        305. 8.1.5.305  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_254 Registers
        306. 8.1.5.306  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_255 Registers
        307. 8.1.5.307  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_256 Registers
        308. 8.1.5.308  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_257 Registers
        309. 8.1.5.309  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_258 Registers
        310. 8.1.5.310  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_259 Registers
        311. 8.1.5.311  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_260 Registers
        312. 8.1.5.312  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_261 Registers
        313. 8.1.5.313  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_262 Registers
        314. 8.1.5.314  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_263 Registers
        315. 8.1.5.315  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_264 Registers
        316. 8.1.5.316  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_265 Registers
        317. 8.1.5.317  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_266 Registers
        318. 8.1.5.318  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_267 Registers
        319. 8.1.5.319  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_268 Registers
        320. 8.1.5.320  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_269 Registers
        321. 8.1.5.321  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_270 Registers
        322. 8.1.5.322  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_271 Registers
        323. 8.1.5.323  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_272 Registers
        324. 8.1.5.324  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_273 Registers
        325. 8.1.5.325  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_274 Registers
        326. 8.1.5.326  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_275 Registers
        327. 8.1.5.327  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_276 Registers
        328. 8.1.5.328  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_277 Registers
        329. 8.1.5.329  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_278 Registers
        330. 8.1.5.330  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_279 Registers
        331. 8.1.5.331  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_280 Registers
        332. 8.1.5.332  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_281 Registers
        333. 8.1.5.333  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_282 Registers
        334. 8.1.5.334  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_283 Registers
        335. 8.1.5.335  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_284 Registers
        336. 8.1.5.336  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_285 Registers
        337. 8.1.5.337  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_286 Registers
        338. 8.1.5.338  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_287 Registers
        339. 8.1.5.339  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_288 Registers
        340. 8.1.5.340  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_289 Registers
        341. 8.1.5.341  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_290 Registers
        342. 8.1.5.342  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_291 Registers
        343. 8.1.5.343  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_292 Registers
        344. 8.1.5.344  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_293 Registers
        345. 8.1.5.345  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_294 Registers
        346. 8.1.5.346  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_295 Registers
        347. 8.1.5.347  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_296 Registers
        348. 8.1.5.348  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_297 Registers
        349. 8.1.5.349  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_298 Registers
        350. 8.1.5.350  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_299 Registers
        351. 8.1.5.351  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_300 Registers
        352. 8.1.5.352  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_301 Registers
        353. 8.1.5.353  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_302 Registers
        354. 8.1.5.354  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_303 Registers
        355. 8.1.5.355  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_304 Registers
        356. 8.1.5.356  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_305 Registers
        357. 8.1.5.357  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_306 Registers
        358. 8.1.5.358  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_307 Registers
        359. 8.1.5.359  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_308 Registers
        360. 8.1.5.360  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_309 Registers
        361. 8.1.5.361  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_310 Registers
        362. 8.1.5.362  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_311 Registers
        363. 8.1.5.363  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_312 Registers
        364. 8.1.5.364  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_313 Registers
        365. 8.1.5.365  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_314 Registers
        366. 8.1.5.366  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_315 Registers
        367. 8.1.5.367  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_316 Registers
        368. 8.1.5.368  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_317 Registers
        369. 8.1.5.369  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_318 Registers
        370. 8.1.5.370  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_319 Registers
        371. 8.1.5.371  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_320 Registers
        372. 8.1.5.372  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_321 Registers
        373. 8.1.5.373  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_322 Registers
        374. 8.1.5.374  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_323 Registers
        375. 8.1.5.375  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_324 Registers
        376. 8.1.5.376  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_325 Registers
        377. 8.1.5.377  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_326 Registers
        378. 8.1.5.378  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_327 Registers
        379. 8.1.5.379  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_328 Registers
        380. 8.1.5.380  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_329 Registers
        381. 8.1.5.381  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_330 Registers
        382. 8.1.5.382  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_331 Registers
        383. 8.1.5.383  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_332 Registers
        384. 8.1.5.384  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_333 Registers
        385. 8.1.5.385  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_334 Registers
        386. 8.1.5.386  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_335 Registers
        387. 8.1.5.387  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_336 Registers
        388. 8.1.5.388  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_337 Registers
        389. 8.1.5.389  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_338 Registers
        390. 8.1.5.390  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_339 Registers
        391. 8.1.5.391  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_340 Registers
        392. 8.1.5.392  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_341 Registers
        393. 8.1.5.393  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_342 Registers
        394. 8.1.5.394  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_343 Registers
        395. 8.1.5.395  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_344 Registers
        396. 8.1.5.396  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_345 Registers
        397. 8.1.5.397  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_346 Registers
        398. 8.1.5.398  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_347 Registers
        399. 8.1.5.399  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_348 Registers
        400. 8.1.5.400  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_349 Registers
        401. 8.1.5.401  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_350 Registers
        402. 8.1.5.402  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_351 Registers
        403. 8.1.5.403  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_352 Registers
        404. 8.1.5.404  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_353 Registers
        405. 8.1.5.405  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_354 Registers
        406. 8.1.5.406  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_355 Registers
        407. 8.1.5.407  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_356 Registers
        408. 8.1.5.408  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_357 Registers
        409. 8.1.5.409  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_358 Registers
        410. 8.1.5.410  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_359 Registers
        411. 8.1.5.411  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_360 Registers
        412. 8.1.5.412  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_361 Registers
        413. 8.1.5.413  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_362 Registers
        414. 8.1.5.414  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_363 Registers
        415. 8.1.5.415  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_364 Registers
        416. 8.1.5.416  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_365 Registers
        417. 8.1.5.417  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_366 Registers
        418. 8.1.5.418  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_367 Registers
        419. 8.1.5.419  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_368 Registers
        420. 8.1.5.420  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_369 Registers
        421. 8.1.5.421  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_370 Registers
        422. 8.1.5.422  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_371 Registers
        423. 8.1.5.423  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_372 Registers
        424. 8.1.5.424  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_373 Registers
        425. 8.1.5.425  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_374 Registers
        426. 8.1.5.426  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_375 Registers
        427. 8.1.5.427  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_376 Registers
        428. 8.1.5.428  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_377 Registers
        429. 8.1.5.429  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_378 Registers
        430. 8.1.5.430  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_379 Registers
        431. 8.1.5.431  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_380 Registers
        432. 8.1.5.432  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_381 Registers
        433. 8.1.5.433  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_382 Registers
        434. 8.1.5.434  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_383 Registers
        435. 8.1.5.435  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_384 Registers
        436. 8.1.5.436  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_385 Registers
        437. 8.1.5.437  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_386 Registers
        438. 8.1.5.438  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_387 Registers
        439. 8.1.5.439  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_388 Registers
        440. 8.1.5.440  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_389 Registers
        441. 8.1.5.441  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_390 Registers
        442. 8.1.5.442  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_391 Registers
        443. 8.1.5.443  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_392 Registers
        444. 8.1.5.444  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_393 Registers
        445. 8.1.5.445  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_394 Registers
        446. 8.1.5.446  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_395 Registers
        447. 8.1.5.447  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_396 Registers
        448. 8.1.5.448  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_397 Registers
        449. 8.1.5.449  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_398 Registers
        450. 8.1.5.450  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_399 Registers
        451. 8.1.5.451  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_400 Registers
        452. 8.1.5.452  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_401 Registers
        453. 8.1.5.453  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_402 Registers
        454. 8.1.5.454  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_403 Registers
        455. 8.1.5.455  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_404 Registers
        456. 8.1.5.456  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_405 Registers
        457. 8.1.5.457  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_406 Registers
        458. 8.1.5.458  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_407 Registers
        459. 8.1.5.459  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_408 Registers
        460. 8.1.5.460  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_409 Registers
        461. 8.1.5.461  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_410 Registers
        462. 8.1.5.462  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_411 Registers
        463. 8.1.5.463  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_412 Registers
        464. 8.1.5.464  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_413 Registers
        465. 8.1.5.465  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_414 Registers
        466. 8.1.5.466  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_415 Registers
        467. 8.1.5.467  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_416 Registers
        468. 8.1.5.468  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_417 Registers
        469. 8.1.5.469  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_418 Registers
        470. 8.1.5.470  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_419 Registers
        471. 8.1.5.471  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_420 Registers
        472. 8.1.5.472  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_421 Registers
        473. 8.1.5.473  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_422 Registers
        474. 8.1.5.474  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_0 Registers
        475. 8.1.5.475  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_1 Registers
        476. 8.1.5.476  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_2 Registers
        477. 8.1.5.477  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_3 Registers
        478. 8.1.5.478  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_4 Registers
        479. 8.1.5.479  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_5 Registers
        480. 8.1.5.480  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_6 Registers
        481. 8.1.5.481  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_7 Registers
        482. 8.1.5.482  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_8 Registers
        483. 8.1.5.483  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_9 Registers
        484. 8.1.5.484  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_10 Registers
        485. 8.1.5.485  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_11 Registers
        486. 8.1.5.486  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_12 Registers
        487. 8.1.5.487  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_13 Registers
        488. 8.1.5.488  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_14 Registers
        489. 8.1.5.489  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_15 Registers
        490. 8.1.5.490  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_16 Registers
        491. 8.1.5.491  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_17 Registers
        492. 8.1.5.492  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_18 Registers
        493. 8.1.5.493  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_19 Registers
        494. 8.1.5.494  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_20 Registers
        495. 8.1.5.495  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_21 Registers
        496. 8.1.5.496  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_22 Registers
        497. 8.1.5.497  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_23 Registers
        498. 8.1.5.498  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_24 Registers
        499. 8.1.5.499  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_25 Registers
        500. 8.1.5.500  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_26 Registers
        501. 8.1.5.501  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_27 Registers
        502. 8.1.5.502  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_28 Registers
        503. 8.1.5.503  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_29 Registers
        504. 8.1.5.504  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_30 Registers
        505. 8.1.5.505  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_31 Registers
        506. 8.1.5.506  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_32 Registers
        507. 8.1.5.507  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_33 Registers
        508. 8.1.5.508  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_34 Registers
        509. 8.1.5.509  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_35 Registers
        510. 8.1.5.510  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_36 Registers
        511. 8.1.5.511  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_37 Registers
        512. 8.1.5.512  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_38 Registers
        513. 8.1.5.513  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_39 Registers
        514. 8.1.5.514  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_40 Registers
        515. 8.1.5.515  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_41 Registers
        516. 8.1.5.516  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_42 Registers
        517. 8.1.5.517  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_43 Registers
        518. 8.1.5.518  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_44 Registers
        519. 8.1.5.519  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_45 Registers
        520. 8.1.5.520  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_46 Registers
        521. 8.1.5.521  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_47 Registers
        522. 8.1.5.522  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_48 Registers
        523. 8.1.5.523  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_49 Registers
        524. 8.1.5.524  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_50 Registers
        525. 8.1.5.525  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_51 Registers
        526. 8.1.5.526  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_52 Registers
        527. 8.1.5.527  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_53 Registers
        528. 8.1.5.528  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_54 Registers
        529. 8.1.5.529  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_55 Registers
        530. 8.1.5.530  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_56 Registers
        531. 8.1.5.531  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_57 Registers
        532. 8.1.5.532  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_58 Registers
        533. 8.1.5.533  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_59 Registers
        534. 8.1.5.534  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_60 Registers
        535. 8.1.5.535  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_61 Registers
        536. 8.1.5.536  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_62 Registers
        537. 8.1.5.537  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_63 Registers
        538. 8.1.5.538  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_64 Registers
        539. 8.1.5.539  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_65 Registers
        540. 8.1.5.540  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_66 Registers
        541. 8.1.5.541  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_67 Registers
        542. 8.1.5.542  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_68 Registers
        543. 8.1.5.543  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_69 Registers
        544. 8.1.5.544  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_70 Registers
        545. 8.1.5.545  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_71 Registers
        546. 8.1.5.546  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_72 Registers
        547. 8.1.5.547  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_73 Registers
        548. 8.1.5.548  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_74 Registers
        549. 8.1.5.549  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_75 Registers
        550. 8.1.5.550  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_76 Registers
        551. 8.1.5.551  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_77 Registers
        552. 8.1.5.552  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_78 Registers
        553. 8.1.5.553  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_79 Registers
        554. 8.1.5.554  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_80 Registers
        555. 8.1.5.555  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_81 Registers
        556. 8.1.5.556  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_82 Registers
        557. 8.1.5.557  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_83 Registers
        558. 8.1.5.558  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_84 Registers
        559. 8.1.5.559  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_85 Registers
        560. 8.1.5.560  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_86 Registers
        561. 8.1.5.561  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_87 Registers
        562. 8.1.5.562  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_88 Registers
        563. 8.1.5.563  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_89 Registers
        564. 8.1.5.564  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_90 Registers
        565. 8.1.5.565  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_91 Registers
        566. 8.1.5.566  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_92 Registers
        567. 8.1.5.567  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_93 Registers
        568. 8.1.5.568  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_94 Registers
        569. 8.1.5.569  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_95 Registers
        570. 8.1.5.570  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_96 Registers
        571. 8.1.5.571  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_97 Registers
        572. 8.1.5.572  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_98 Registers
        573. 8.1.5.573  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_99 Registers
        574. 8.1.5.574  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_100 Registers
        575. 8.1.5.575  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_101 Registers
        576. 8.1.5.576  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_102 Registers
        577. 8.1.5.577  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_103 Registers
        578. 8.1.5.578  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_104 Registers
        579. 8.1.5.579  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_105 Registers
        580. 8.1.5.580  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_106 Registers
        581. 8.1.5.581  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_107 Registers
        582. 8.1.5.582  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_108 Registers
        583. 8.1.5.583  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_109 Registers
        584. 8.1.5.584  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_110 Registers
        585. 8.1.5.585  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_111 Registers
        586. 8.1.5.586  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_112 Registers
        587. 8.1.5.587  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_113 Registers
        588. 8.1.5.588  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_114 Registers
        589. 8.1.5.589  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_115 Registers
        590. 8.1.5.590  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_116 Registers
        591. 8.1.5.591  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_117 Registers
        592. 8.1.5.592  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_118 Registers
        593. 8.1.5.593  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_119 Registers
        594. 8.1.5.594  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_120 Registers
        595. 8.1.5.595  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_121 Registers
        596. 8.1.5.596  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_122 Registers
        597. 8.1.5.597  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_123 Registers
        598. 8.1.5.598  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_124 Registers
        599. 8.1.5.599  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_125 Registers
        600. 8.1.5.600  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_126 Registers
        601. 8.1.5.601  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_127 Registers
        602. 8.1.5.602  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_128 Registers
        603. 8.1.5.603  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_129 Registers
        604. 8.1.5.604  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_130 Registers
        605. 8.1.5.605  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_131 Registers
        606. 8.1.5.606  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_132 Registers
        607. 8.1.5.607  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_133 Registers
        608. 8.1.5.608  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_134 Registers
        609. 8.1.5.609  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_135 Registers
        610. 8.1.5.610  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_136 Registers
        611. 8.1.5.611  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_137 Registers
        612. 8.1.5.612  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_138 Registers
        613. 8.1.5.613  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_139 Registers
        614. 8.1.5.614  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_140 Registers
        615. 8.1.5.615  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_141 Registers
        616. 8.1.5.616  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_142 Registers
        617. 8.1.5.617  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_143 Registers
        618. 8.1.5.618  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_144 Registers
        619. 8.1.5.619  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_145 Registers
        620. 8.1.5.620  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_146 Registers
        621. 8.1.5.621  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_147 Registers
        622. 8.1.5.622  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_148 Registers
        623. 8.1.5.623  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_149 Registers
        624. 8.1.5.624  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_150 Registers
        625. 8.1.5.625  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_151 Registers
        626. 8.1.5.626  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_152 Registers
        627. 8.1.5.627  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_153 Registers
        628. 8.1.5.628  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_154 Registers
        629. 8.1.5.629  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_155 Registers
        630. 8.1.5.630  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_156 Registers
        631. 8.1.5.631  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_157 Registers
        632. 8.1.5.632  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_158 Registers
        633. 8.1.5.633  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_159 Registers
        634. 8.1.5.634  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_160 Registers
        635. 8.1.5.635  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_161 Registers
        636. 8.1.5.636  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_162 Registers
        637. 8.1.5.637  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_163 Registers
        638. 8.1.5.638  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_164 Registers
        639. 8.1.5.639  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_165 Registers
        640. 8.1.5.640  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_166 Registers
        641. 8.1.5.641  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_167 Registers
        642. 8.1.5.642  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_168 Registers
        643. 8.1.5.643  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_169 Registers
        644. 8.1.5.644  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_170 Registers
        645. 8.1.5.645  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_171 Registers
        646. 8.1.5.646  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_172 Registers
        647. 8.1.5.647  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_173 Registers
        648. 8.1.5.648  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_174 Registers
        649. 8.1.5.649  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_175 Registers
        650. 8.1.5.650  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_176 Registers
        651. 8.1.5.651  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_177 Registers
        652. 8.1.5.652  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_178 Registers
        653. 8.1.5.653  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_179 Registers
        654. 8.1.5.654  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_180 Registers
        655. 8.1.5.655  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_181 Registers
        656. 8.1.5.656  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_182 Registers
        657. 8.1.5.657  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_183 Registers
        658. 8.1.5.658  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_184 Registers
        659. 8.1.5.659  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_185 Registers
        660. 8.1.5.660  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_186 Registers
        661. 8.1.5.661  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_187 Registers
        662. 8.1.5.662  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_188 Registers
        663. 8.1.5.663  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_189 Registers
        664. 8.1.5.664  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_190 Registers
        665. 8.1.5.665  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_191 Registers
        666. 8.1.5.666  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_192 Registers
        667. 8.1.5.667  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_193 Registers
        668. 8.1.5.668  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_194 Registers
        669. 8.1.5.669  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_195 Registers
        670. 8.1.5.670  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_196 Registers
        671. 8.1.5.671  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_197 Registers
        672. 8.1.5.672  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_198 Registers
        673. 8.1.5.673  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_199 Registers
        674. 8.1.5.674  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_200 Registers
        675. 8.1.5.675  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_201 Registers
        676. 8.1.5.676  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_202 Registers
        677. 8.1.5.677  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_203 Registers
        678. 8.1.5.678  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_204 Registers
        679. 8.1.5.679  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_205 Registers
        680. 8.1.5.680  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_206 Registers
        681. 8.1.5.681  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_207 Registers
        682. 8.1.5.682  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_208 Registers
        683. 8.1.5.683  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_209 Registers
        684. 8.1.5.684  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_210 Registers
        685. 8.1.5.685  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_211 Registers
        686. 8.1.5.686  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_212 Registers
        687. 8.1.5.687  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_213 Registers
        688. 8.1.5.688  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_214 Registers
        689. 8.1.5.689  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_215 Registers
        690. 8.1.5.690  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_216 Registers
        691. 8.1.5.691  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_217 Registers
        692. 8.1.5.692  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_218 Registers
        693. 8.1.5.693  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_219 Registers
        694. 8.1.5.694  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_220 Registers
        695. 8.1.5.695  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_221 Registers
        696. 8.1.5.696  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_222 Registers
        697. 8.1.5.697  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_223 Registers
        698. 8.1.5.698  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_224 Registers
        699. 8.1.5.699  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_225 Registers
        700. 8.1.5.700  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_226 Registers
        701. 8.1.5.701  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_227 Registers
        702. 8.1.5.702  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_228 Registers
        703. 8.1.5.703  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_229 Registers
        704. 8.1.5.704  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_230 Registers
        705. 8.1.5.705  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_231 Registers
        706. 8.1.5.706  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_232 Registers
        707. 8.1.5.707  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_233 Registers
        708. 8.1.5.708  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_234 Registers
        709. 8.1.5.709  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_235 Registers
        710. 8.1.5.710  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_236 Registers
        711. 8.1.5.711  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_237 Registers
        712. 8.1.5.712  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_238 Registers
        713. 8.1.5.713  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_239 Registers
        714. 8.1.5.714  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_240 Registers
        715. 8.1.5.715  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_241 Registers
        716. 8.1.5.716  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_242 Registers
        717. 8.1.5.717  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_243 Registers
        718. 8.1.5.718  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_244 Registers
        719. 8.1.5.719  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_245 Registers
        720. 8.1.5.720  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_246 Registers
        721. 8.1.5.721  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_247 Registers
        722. 8.1.5.722  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_248 Registers
        723. 8.1.5.723  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_249 Registers
        724. 8.1.5.724  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_250 Registers
        725. 8.1.5.725  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_251 Registers
        726. 8.1.5.726  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_252 Registers
        727. 8.1.5.727  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_253 Registers
        728. 8.1.5.728  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_254 Registers
        729. 8.1.5.729  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_255 Registers
        730. 8.1.5.730  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_256 Registers
        731. 8.1.5.731  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_257 Registers
        732. 8.1.5.732  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_258 Registers
        733. 8.1.5.733  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_259 Registers
        734. 8.1.5.734  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_260 Registers
        735. 8.1.5.735  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_261 Registers
        736. 8.1.5.736  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_262 Registers
        737. 8.1.5.737  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_263 Registers
        738. 8.1.5.738  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_264 Registers
        739. 8.1.5.739  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_265 Registers
        740. 8.1.5.740  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_266 Registers
        741. 8.1.5.741  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_267 Registers
        742. 8.1.5.742  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_268 Registers
        743. 8.1.5.743  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_269 Registers
        744. 8.1.5.744  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_270 Registers
        745. 8.1.5.745  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_271 Registers
        746. 8.1.5.746  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_272 Registers
        747. 8.1.5.747  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_273 Registers
        748. 8.1.5.748  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_274 Registers
        749. 8.1.5.749  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_275 Registers
        750. 8.1.5.750  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_276 Registers
        751. 8.1.5.751  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_277 Registers
        752. 8.1.5.752  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_278 Registers
        753. 8.1.5.753  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_279 Registers
        754. 8.1.5.754  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_280 Registers
        755. 8.1.5.755  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_281 Registers
        756. 8.1.5.756  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_282 Registers
        757. 8.1.5.757  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_283 Registers
        758. 8.1.5.758  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_284 Registers
        759. 8.1.5.759  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_285 Registers
        760. 8.1.5.760  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_286 Registers
        761. 8.1.5.761  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_287 Registers
        762. 8.1.5.762  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_288 Registers
        763. 8.1.5.763  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_289 Registers
        764. 8.1.5.764  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_290 Registers
        765. 8.1.5.765  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_291 Registers
        766. 8.1.5.766  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_292 Registers
        767. 8.1.5.767  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_293 Registers
        768. 8.1.5.768  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_294 Registers
        769. 8.1.5.769  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_295 Registers
        770. 8.1.5.770  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_296 Registers
        771. 8.1.5.771  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_297 Registers
        772. 8.1.5.772  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_298 Registers
        773. 8.1.5.773  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_299 Registers
        774. 8.1.5.774  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_300 Registers
        775. 8.1.5.775  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_301 Registers
        776. 8.1.5.776  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_302 Registers
        777. 8.1.5.777  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_303 Registers
        778. 8.1.5.778  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_304 Registers
        779. 8.1.5.779  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_305 Registers
        780. 8.1.5.780  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_306 Registers
        781. 8.1.5.781  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_307 Registers
        782. 8.1.5.782  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_308 Registers
        783. 8.1.5.783  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_309 Registers
        784. 8.1.5.784  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_310 Registers
        785. 8.1.5.785  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_311 Registers
        786. 8.1.5.786  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_312 Registers
        787. 8.1.5.787  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_313 Registers
        788. 8.1.5.788  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_314 Registers
        789. 8.1.5.789  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_315 Registers
        790. 8.1.5.790  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_316 Registers
        791. 8.1.5.791  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_317 Registers
        792. 8.1.5.792  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_318 Registers
        793. 8.1.5.793  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_319 Registers
        794. 8.1.5.794  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_320 Registers
        795. 8.1.5.795  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_321 Registers
        796. 8.1.5.796  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_322 Registers
        797. 8.1.5.797  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_323 Registers
        798. 8.1.5.798  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_324 Registers
        799. 8.1.5.799  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_325 Registers
        800. 8.1.5.800  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_326 Registers
        801. 8.1.5.801  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_327 Registers
        802. 8.1.5.802  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_328 Registers
        803. 8.1.5.803  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_329 Registers
        804. 8.1.5.804  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_330 Registers
        805. 8.1.5.805  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_331 Registers
        806. 8.1.5.806  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_332 Registers
        807. 8.1.5.807  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_333 Registers
        808. 8.1.5.808  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_334 Registers
        809. 8.1.5.809  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_335 Registers
        810. 8.1.5.810  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_336 Registers
        811. 8.1.5.811  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_337 Registers
        812. 8.1.5.812  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_338 Registers
        813. 8.1.5.813  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_339 Registers
        814. 8.1.5.814  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_340 Registers
        815. 8.1.5.815  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_341 Registers
        816. 8.1.5.816  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_342 Registers
        817. 8.1.5.817  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_343 Registers
        818. 8.1.5.818  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_344 Registers
        819. 8.1.5.819  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_0 Registers
        820. 8.1.5.820  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1 Registers
        821. 8.1.5.821  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_2 Registers
        822. 8.1.5.822  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_3 Registers
        823. 8.1.5.823  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_4 Registers
        824. 8.1.5.824  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_5 Registers
        825. 8.1.5.825  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_6 Registers
        826. 8.1.5.826  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_7 Registers
        827. 8.1.5.827  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_8 Registers
        828. 8.1.5.828  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_9 Registers
        829. 8.1.5.829  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_10 Registers
        830. 8.1.5.830  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_11 Registers
        831. 8.1.5.831  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_12 Registers
        832. 8.1.5.832  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_13 Registers
        833. 8.1.5.833  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_14 Registers
        834. 8.1.5.834  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_15 Registers
        835. 8.1.5.835  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_16 Registers
        836. 8.1.5.836  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_17 Registers
        837. 8.1.5.837  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_18 Registers
        838. 8.1.5.838  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_19 Registers
        839. 8.1.5.839  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_20 Registers
        840. 8.1.5.840  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_21 Registers
        841. 8.1.5.841  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_22 Registers
        842. 8.1.5.842  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_23 Registers
        843. 8.1.5.843  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_24 Registers
        844. 8.1.5.844  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_25 Registers
        845. 8.1.5.845  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_26 Registers
        846. 8.1.5.846  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_27 Registers
        847. 8.1.5.847  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_28 Registers
        848. 8.1.5.848  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_29 Registers
        849. 8.1.5.849  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_30 Registers
        850. 8.1.5.850  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_31 Registers
        851. 8.1.5.851  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_32 Registers
        852. 8.1.5.852  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_33 Registers
        853. 8.1.5.853  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_34 Registers
        854. 8.1.5.854  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_35 Registers
        855. 8.1.5.855  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_36 Registers
        856. 8.1.5.856  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_37 Registers
        857. 8.1.5.857  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_38 Registers
        858. 8.1.5.858  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_39 Registers
        859. 8.1.5.859  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_40 Registers
        860. 8.1.5.860  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_41 Registers
        861. 8.1.5.861  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_42 Registers
        862. 8.1.5.862  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_43 Registers
        863. 8.1.5.863  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_44 Registers
        864. 8.1.5.864  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_45 Registers
        865. 8.1.5.865  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_46 Registers
        866. 8.1.5.866  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_47 Registers
        867. 8.1.5.867  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_48 Registers
        868. 8.1.5.868  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_49 Registers
        869. 8.1.5.869  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_50 Registers
        870. 8.1.5.870  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_51 Registers
        871. 8.1.5.871  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_52 Registers
        872. 8.1.5.872  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_53 Registers
        873. 8.1.5.873  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_54 Registers
        874. 8.1.5.874  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_55 Registers
        875. 8.1.5.875  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_56 Registers
        876. 8.1.5.876  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_57 Registers
        877. 8.1.5.877  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_58 Registers
        878. 8.1.5.878  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_59 Registers
        879. 8.1.5.879  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_60 Registers
        880. 8.1.5.880  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_61 Registers
        881. 8.1.5.881  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_62 Registers
        882. 8.1.5.882  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_63 Registers
        883. 8.1.5.883  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_64 Registers
        884. 8.1.5.884  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_65 Registers
        885. 8.1.5.885  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_66 Registers
        886. 8.1.5.886  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_67 Registers
        887. 8.1.5.887  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_68 Registers
        888. 8.1.5.888  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_69 Registers
        889. 8.1.5.889  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_70 Registers
        890. 8.1.5.890  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_71 Registers
        891. 8.1.5.891  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_72 Registers
        892. 8.1.5.892  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_73 Registers
        893. 8.1.5.893  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_74 Registers
        894. 8.1.5.894  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_75 Registers
        895. 8.1.5.895  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_76 Registers
        896. 8.1.5.896  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_77 Registers
        897. 8.1.5.897  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_78 Registers
        898. 8.1.5.898  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_79 Registers
        899. 8.1.5.899  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_80 Registers
        900. 8.1.5.900  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_81 Registers
        901. 8.1.5.901  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_82 Registers
        902. 8.1.5.902  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_83 Registers
        903. 8.1.5.903  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_84 Registers
        904. 8.1.5.904  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_85 Registers
        905. 8.1.5.905  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_86 Registers
        906. 8.1.5.906  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_87 Registers
        907. 8.1.5.907  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_88 Registers
        908. 8.1.5.908  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_89 Registers
        909. 8.1.5.909  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_90 Registers
        910. 8.1.5.910  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_91 Registers
        911. 8.1.5.911  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_92 Registers
        912. 8.1.5.912  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_93 Registers
        913. 8.1.5.913  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_94 Registers
        914. 8.1.5.914  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_95 Registers
        915. 8.1.5.915  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_96 Registers
        916. 8.1.5.916  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_97 Registers
        917. 8.1.5.917  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_98 Registers
        918. 8.1.5.918  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_99 Registers
        919. 8.1.5.919  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_100 Registers
        920. 8.1.5.920  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_101 Registers
        921. 8.1.5.921  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_102 Registers
        922. 8.1.5.922  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_103 Registers
        923. 8.1.5.923  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_104 Registers
        924. 8.1.5.924  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_105 Registers
        925. 8.1.5.925  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_106 Registers
        926. 8.1.5.926  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_107 Registers
        927. 8.1.5.927  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_108 Registers
        928. 8.1.5.928  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_109 Registers
        929. 8.1.5.929  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_110 Registers
        930. 8.1.5.930  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_111 Registers
        931. 8.1.5.931  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_112 Registers
        932. 8.1.5.932  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_113 Registers
        933. 8.1.5.933  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_114 Registers
        934. 8.1.5.934  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_115 Registers
        935. 8.1.5.935  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_116 Registers
        936. 8.1.5.936  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_117 Registers
        937. 8.1.5.937  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_118 Registers
        938. 8.1.5.938  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_119 Registers
        939. 8.1.5.939  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_120 Registers
        940. 8.1.5.940  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_121 Registers
        941. 8.1.5.941  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_122 Registers
        942. 8.1.5.942  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_123 Registers
        943. 8.1.5.943  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_124 Registers
        944. 8.1.5.944  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_125 Registers
        945. 8.1.5.945  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_256 Registers
        946. 8.1.5.946  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_257 Registers
        947. 8.1.5.947  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_258 Registers
        948. 8.1.5.948  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_259 Registers
        949. 8.1.5.949  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_260 Registers
        950. 8.1.5.950  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_261 Registers
        951. 8.1.5.951  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_262 Registers
        952. 8.1.5.952  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_263 Registers
        953. 8.1.5.953  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_264 Registers
        954. 8.1.5.954  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_265 Registers
        955. 8.1.5.955  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_266 Registers
        956. 8.1.5.956  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_267 Registers
        957. 8.1.5.957  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_268 Registers
        958. 8.1.5.958  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_269 Registers
        959. 8.1.5.959  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_270 Registers
        960. 8.1.5.960  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_271 Registers
        961. 8.1.5.961  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_272 Registers
        962. 8.1.5.962  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_273 Registers
        963. 8.1.5.963  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_274 Registers
        964. 8.1.5.964  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_275 Registers
        965. 8.1.5.965  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_276 Registers
        966. 8.1.5.966  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_277 Registers
        967. 8.1.5.967  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_278 Registers
        968. 8.1.5.968  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_279 Registers
        969. 8.1.5.969  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_280 Registers
        970. 8.1.5.970  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_281 Registers
        971. 8.1.5.971  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_282 Registers
        972. 8.1.5.972  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_283 Registers
        973. 8.1.5.973  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_284 Registers
        974. 8.1.5.974  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_285 Registers
        975. 8.1.5.975  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_286 Registers
        976. 8.1.5.976  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_287 Registers
        977. 8.1.5.977  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_288 Registers
        978. 8.1.5.978  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_289 Registers
        979. 8.1.5.979  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_290 Registers
        980. 8.1.5.980  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_291 Registers
        981. 8.1.5.981  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_292 Registers
        982. 8.1.5.982  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_293 Registers
        983. 8.1.5.983  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_294 Registers
        984. 8.1.5.984  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_295 Registers
        985. 8.1.5.985  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_296 Registers
        986. 8.1.5.986  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_297 Registers
        987. 8.1.5.987  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_298 Registers
        988. 8.1.5.988  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_299 Registers
        989. 8.1.5.989  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_300 Registers
        990. 8.1.5.990  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_301 Registers
        991. 8.1.5.991  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_302 Registers
        992. 8.1.5.992  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_303 Registers
        993. 8.1.5.993  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_304 Registers
        994. 8.1.5.994  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_305 Registers
        995. 8.1.5.995  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_306 Registers
        996. 8.1.5.996  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_307 Registers
        997. 8.1.5.997  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_308 Registers
        998. 8.1.5.998  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_309 Registers
        999. 8.1.5.999  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_310 Registers
        1000. 8.1.5.1000 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_311 Registers
        1001. 8.1.5.1001 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_312 Registers
        1002. 8.1.5.1002 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_313 Registers
        1003. 8.1.5.1003 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_314 Registers
        1004. 8.1.5.1004 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_315 Registers
        1005. 8.1.5.1005 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_316 Registers
        1006. 8.1.5.1006 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_317 Registers
        1007. 8.1.5.1007 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_318 Registers
        1008. 8.1.5.1008 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_319 Registers
        1009. 8.1.5.1009 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_320 Registers
        1010. 8.1.5.1010 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_321 Registers
        1011. 8.1.5.1011 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_322 Registers
        1012. 8.1.5.1012 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_323 Registers
        1013. 8.1.5.1013 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_324 Registers
        1014. 8.1.5.1014 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_325 Registers
        1015. 8.1.5.1015 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_326 Registers
        1016. 8.1.5.1016 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_327 Registers
        1017. 8.1.5.1017 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_328 Registers
        1018. 8.1.5.1018 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_329 Registers
        1019. 8.1.5.1019 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_330 Registers
        1020. 8.1.5.1020 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_331 Registers
        1021. 8.1.5.1021 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_332 Registers
        1022. 8.1.5.1022 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_333 Registers
        1023. 8.1.5.1023 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_334 Registers
        1024. 8.1.5.1024 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_335 Registers
        1025. 8.1.5.1025 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_336 Registers
        1026. 8.1.5.1026 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_337 Registers
        1027. 8.1.5.1027 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_338 Registers
        1028. 8.1.5.1028 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_339 Registers
        1029. 8.1.5.1029 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_340 Registers
        1030. 8.1.5.1030 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_341 Registers
        1031. 8.1.5.1031 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_342 Registers
        1032. 8.1.5.1032 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_343 Registers
        1033. 8.1.5.1033 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_344 Registers
        1034. 8.1.5.1034 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_345 Registers
        1035. 8.1.5.1035 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_346 Registers
        1036. 8.1.5.1036 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_347 Registers
        1037. 8.1.5.1037 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_348 Registers
        1038. 8.1.5.1038 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_349 Registers
        1039. 8.1.5.1039 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_350 Registers
        1040. 8.1.5.1040 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_351 Registers
        1041. 8.1.5.1041 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_352 Registers
        1042. 8.1.5.1042 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_353 Registers
        1043. 8.1.5.1043 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_354 Registers
        1044. 8.1.5.1044 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_355 Registers
        1045. 8.1.5.1045 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_356 Registers
        1046. 8.1.5.1046 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_357 Registers
        1047. 8.1.5.1047 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_358 Registers
        1048. 8.1.5.1048 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_359 Registers
        1049. 8.1.5.1049 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_360 Registers
        1050. 8.1.5.1050 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_361 Registers
        1051. 8.1.5.1051 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_362 Registers
        1052. 8.1.5.1052 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_363 Registers
        1053. 8.1.5.1053 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_364 Registers
        1054. 8.1.5.1054 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_365 Registers
        1055. 8.1.5.1055 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_366 Registers
        1056. 8.1.5.1056 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_367 Registers
        1057. 8.1.5.1057 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_368 Registers
        1058. 8.1.5.1058 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_369 Registers
        1059. 8.1.5.1059 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_370 Registers
        1060. 8.1.5.1060 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_371 Registers
        1061. 8.1.5.1061 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_372 Registers
        1062. 8.1.5.1062 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_373 Registers
        1063. 8.1.5.1063 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_374 Registers
        1064. 8.1.5.1064 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_375 Registers
        1065. 8.1.5.1065 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_376 Registers
        1066. 8.1.5.1066 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_377 Registers
        1067. 8.1.5.1067 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_378 Registers
        1068. 8.1.5.1068 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_379 Registers
        1069. 8.1.5.1069 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_380 Registers
        1070. 8.1.5.1070 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_381 Registers
        1071. 8.1.5.1071 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_512 Registers
        1072. 8.1.5.1072 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_513 Registers
        1073. 8.1.5.1073 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_514 Registers
        1074. 8.1.5.1074 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_515 Registers
        1075. 8.1.5.1075 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_516 Registers
        1076. 8.1.5.1076 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_517 Registers
        1077. 8.1.5.1077 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_518 Registers
        1078. 8.1.5.1078 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_519 Registers
        1079. 8.1.5.1079 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_520 Registers
        1080. 8.1.5.1080 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_521 Registers
        1081. 8.1.5.1081 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_522 Registers
        1082. 8.1.5.1082 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_523 Registers
        1083. 8.1.5.1083 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_524 Registers
        1084. 8.1.5.1084 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_525 Registers
        1085. 8.1.5.1085 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_526 Registers
        1086. 8.1.5.1086 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_527 Registers
        1087. 8.1.5.1087 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_528 Registers
        1088. 8.1.5.1088 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_529 Registers
        1089. 8.1.5.1089 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_530 Registers
        1090. 8.1.5.1090 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_531 Registers
        1091. 8.1.5.1091 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_532 Registers
        1092. 8.1.5.1092 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_533 Registers
        1093. 8.1.5.1093 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_534 Registers
        1094. 8.1.5.1094 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_535 Registers
        1095. 8.1.5.1095 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_536 Registers
        1096. 8.1.5.1096 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_537 Registers
        1097. 8.1.5.1097 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_538 Registers
        1098. 8.1.5.1098 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_539 Registers
        1099. 8.1.5.1099 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_540 Registers
        1100. 8.1.5.1100 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_541 Registers
        1101. 8.1.5.1101 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_542 Registers
        1102. 8.1.5.1102 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_543 Registers
        1103. 8.1.5.1103 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_544 Registers
        1104. 8.1.5.1104 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_545 Registers
        1105. 8.1.5.1105 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_546 Registers
        1106. 8.1.5.1106 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_547 Registers
        1107. 8.1.5.1107 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_548 Registers
        1108. 8.1.5.1108 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_549 Registers
        1109. 8.1.5.1109 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_550 Registers
        1110. 8.1.5.1110 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_551 Registers
        1111. 8.1.5.1111 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_552 Registers
        1112. 8.1.5.1112 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_553 Registers
        1113. 8.1.5.1113 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_554 Registers
        1114. 8.1.5.1114 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_768 Registers
        1115. 8.1.5.1115 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_769 Registers
        1116. 8.1.5.1116 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_770 Registers
        1117. 8.1.5.1117 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_771 Registers
        1118. 8.1.5.1118 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_772 Registers
        1119. 8.1.5.1119 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_773 Registers
        1120. 8.1.5.1120 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_774 Registers
        1121. 8.1.5.1121 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_775 Registers
        1122. 8.1.5.1122 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_776 Registers
        1123. 8.1.5.1123 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_777 Registers
        1124. 8.1.5.1124 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_778 Registers
        1125. 8.1.5.1125 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_779 Registers
        1126. 8.1.5.1126 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_780 Registers
        1127. 8.1.5.1127 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_781 Registers
        1128. 8.1.5.1128 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_782 Registers
        1129. 8.1.5.1129 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_783 Registers
        1130. 8.1.5.1130 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_784 Registers
        1131. 8.1.5.1131 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_785 Registers
        1132. 8.1.5.1132 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_786 Registers
        1133. 8.1.5.1133 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_787 Registers
        1134. 8.1.5.1134 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_788 Registers
        1135. 8.1.5.1135 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_789 Registers
        1136. 8.1.5.1136 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_790 Registers
        1137. 8.1.5.1137 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_791 Registers
        1138. 8.1.5.1138 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_792 Registers
        1139. 8.1.5.1139 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_793 Registers
        1140. 8.1.5.1140 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_794 Registers
        1141. 8.1.5.1141 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_795 Registers
        1142. 8.1.5.1142 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_796 Registers
        1143. 8.1.5.1143 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_797 Registers
        1144. 8.1.5.1144 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_798 Registers
        1145. 8.1.5.1145 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_799 Registers
        1146. 8.1.5.1146 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_800 Registers
        1147. 8.1.5.1147 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_801 Registers
        1148. 8.1.5.1148 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_802 Registers
        1149. 8.1.5.1149 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_803 Registers
        1150. 8.1.5.1150 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_804 Registers
        1151. 8.1.5.1151 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_805 Registers
        1152. 8.1.5.1152 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_806 Registers
        1153. 8.1.5.1153 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_807 Registers
        1154. 8.1.5.1154 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_808 Registers
        1155. 8.1.5.1155 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_809 Registers
        1156. 8.1.5.1156 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_810 Registers
        1157. 8.1.5.1157 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1024 Registers
        1158. 8.1.5.1158 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1025 Registers
        1159. 8.1.5.1159 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1026 Registers
        1160. 8.1.5.1160 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1027 Registers
        1161. 8.1.5.1161 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1028 Registers
        1162. 8.1.5.1162 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1029 Registers
        1163. 8.1.5.1163 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1030 Registers
        1164. 8.1.5.1164 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1031 Registers
        1165. 8.1.5.1165 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1032 Registers
        1166. 8.1.5.1166 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1033 Registers
        1167. 8.1.5.1167 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1034 Registers
        1168. 8.1.5.1168 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1035 Registers
        1169. 8.1.5.1169 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1036 Registers
        1170. 8.1.5.1170 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1037 Registers
        1171. 8.1.5.1171 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1038 Registers
        1172. 8.1.5.1172 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1039 Registers
        1173. 8.1.5.1173 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1040 Registers
        1174. 8.1.5.1174 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1041 Registers
        1175. 8.1.5.1175 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1042 Registers
        1176. 8.1.5.1176 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1043 Registers
        1177. 8.1.5.1177 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1044 Registers
        1178. 8.1.5.1178 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1045 Registers
        1179. 8.1.5.1179 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1046 Registers
        1180. 8.1.5.1180 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1047 Registers
        1181. 8.1.5.1181 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1048 Registers
        1182. 8.1.5.1182 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1049 Registers
        1183. 8.1.5.1183 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1050 Registers
        1184. 8.1.5.1184 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1051 Registers
        1185. 8.1.5.1185 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1052 Registers
        1186. 8.1.5.1186 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1053 Registers
        1187. 8.1.5.1187 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1054 Registers
        1188. 8.1.5.1188 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1055 Registers
        1189. 8.1.5.1189 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1056 Registers
        1190. 8.1.5.1190 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1057 Registers
        1191. 8.1.5.1191 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1058 Registers
        1192. 8.1.5.1192 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1059 Registers
        1193. 8.1.5.1193 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1060 Registers
        1194. 8.1.5.1194 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1061 Registers
        1195. 8.1.5.1195 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1062 Registers
        1196. 8.1.5.1196 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1063 Registers
        1197. 8.1.5.1197 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1064 Registers
        1198. 8.1.5.1198 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1065 Registers
        1199. 8.1.5.1199 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1066 Registers
        1200. 8.1.5.1200 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1280 Registers
        1201. 8.1.5.1201 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1281 Registers
        1202. 8.1.5.1202 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1282 Registers
        1203. 8.1.5.1203 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1283 Registers
        1204. 8.1.5.1204 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1284 Registers
        1205. 8.1.5.1205 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1285 Registers
        1206. 8.1.5.1206 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1286 Registers
        1207. 8.1.5.1207 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1287 Registers
        1208. 8.1.5.1208 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1288 Registers
        1209. 8.1.5.1209 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1289 Registers
        1210. 8.1.5.1210 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1290 Registers
        1211. 8.1.5.1211 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1291 Registers
        1212. 8.1.5.1212 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1292 Registers
        1213. 8.1.5.1213 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1293 Registers
        1214. 8.1.5.1214 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1294 Registers
        1215. 8.1.5.1215 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1295 Registers
        1216. 8.1.5.1216 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1296 Registers
        1217. 8.1.5.1217 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1297 Registers
        1218. 8.1.5.1218 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1298 Registers
        1219. 8.1.5.1219 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1299 Registers
        1220. 8.1.5.1220 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1300 Registers
        1221. 8.1.5.1221 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1301 Registers
        1222. 8.1.5.1222 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1302 Registers
        1223. 8.1.5.1223 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1303 Registers
        1224. 8.1.5.1224 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1304 Registers
        1225. 8.1.5.1225 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1305 Registers
        1226. 8.1.5.1226 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1306 Registers
        1227. 8.1.5.1227 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1307 Registers
        1228. 8.1.5.1228 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1308 Registers
        1229. 8.1.5.1229 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1309 Registers
        1230. 8.1.5.1230 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1310 Registers
        1231. 8.1.5.1231 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1311 Registers
        1232. 8.1.5.1232 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1312 Registers
        1233. 8.1.5.1233 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1313 Registers
        1234. 8.1.5.1234 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1314 Registers
        1235. 8.1.5.1235 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1315 Registers
        1236. 8.1.5.1236 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1316 Registers
        1237. 8.1.5.1237 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1317 Registers
        1238. 8.1.5.1238 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1318 Registers
        1239. 8.1.5.1239 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1319 Registers
        1240. 8.1.5.1240 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1320 Registers
        1241. 8.1.5.1241 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1321 Registers
        1242. 8.1.5.1242 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1322 Registers
        1243. 8.1.5.1243 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1323 Registers
        1244. 8.1.5.1244 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1324 Registers
        1245. 8.1.5.1245 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1325 Registers
        1246. 8.1.5.1246 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1326 Registers
        1247. 8.1.5.1247 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1327 Registers
        1248. 8.1.5.1248 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1328 Registers
        1249. 8.1.5.1249 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1329 Registers
        1250. 8.1.5.1250 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1330 Registers
        1251. 8.1.5.1251 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1331 Registers
        1252. 8.1.5.1252 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1332 Registers
        1253. 8.1.5.1253 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1333 Registers
        1254. 8.1.5.1254 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1334 Registers
        1255. 8.1.5.1255 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1335 Registers
        1256. 8.1.5.1256 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1336 Registers
        1257. 8.1.5.1257 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1337 Registers
        1258. 8.1.5.1258 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1338 Registers
        1259. 8.1.5.1259 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1339 Registers
        1260. 8.1.5.1260 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1340 Registers
        1261. 8.1.5.1261 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1341 Registers
        1262. 8.1.5.1262 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1342 Registers
        1263. 8.1.5.1263 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1343 Registers
        1264. 8.1.5.1264 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1344 Registers
        1265. 8.1.5.1265 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1345 Registers
        1266. 8.1.5.1266 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1346 Registers
        1267. 8.1.5.1267 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1347 Registers
        1268. 8.1.5.1268 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1348 Registers
        1269. 8.1.5.1269 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1349 Registers
        1270. 8.1.5.1270 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1350 Registers
        1271. 8.1.5.1271 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1351 Registers
        1272. 8.1.5.1272 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1352 Registers
        1273. 8.1.5.1273 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1353 Registers
        1274. 8.1.5.1274 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1354 Registers
        1275. 8.1.5.1275 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1355 Registers
        1276. 8.1.5.1276 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1356 Registers
        1277. 8.1.5.1277 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1357 Registers
        1278. 8.1.5.1278 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1358 Registers
        1279. 8.1.5.1279 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1359 Registers
        1280. 8.1.5.1280 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1360 Registers
        1281. 8.1.5.1281 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1361 Registers
        1282. 8.1.5.1282 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1362 Registers
        1283. 8.1.5.1283 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1363 Registers
        1284. 8.1.5.1284 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1364 Registers
        1285. 8.1.5.1285 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1365 Registers
        1286. 8.1.5.1286 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1366 Registers
        1287. 8.1.5.1287 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1367 Registers
        1288. 8.1.5.1288 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1368 Registers
        1289. 8.1.5.1289 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1369 Registers
        1290. 8.1.5.1290 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1370 Registers
        1291. 8.1.5.1291 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1371 Registers
        1292. 8.1.5.1292 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1372 Registers
        1293. 8.1.5.1293 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1373 Registers
        1294. 8.1.5.1294 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1374 Registers
        1295. 8.1.5.1295 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1375 Registers
        1296. 8.1.5.1296 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1376 Registers
        1297. 8.1.5.1297 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1377 Registers
        1298. 8.1.5.1298 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1378 Registers
        1299. 8.1.5.1299 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1379 Registers
        1300. 8.1.5.1300 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1380 Registers
        1301. 8.1.5.1301 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1381 Registers
        1302. 8.1.5.1302 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1382 Registers
        1303. 8.1.5.1303 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1383 Registers
        1304. 8.1.5.1304 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1384 Registers
        1305. 8.1.5.1305 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1385 Registers
        1306. 8.1.5.1306 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1386 Registers
        1307. 8.1.5.1307 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1387 Registers
        1308. 8.1.5.1308 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1388 Registers
        1309. 8.1.5.1309 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1389 Registers
        1310. 8.1.5.1310 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1390 Registers
        1311. 8.1.5.1311 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1391 Registers
        1312. 8.1.5.1312 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1392 Registers
        1313. 8.1.5.1313 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1393 Registers
        1314. 8.1.5.1314 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1394 Registers
        1315. 8.1.5.1315 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1395 Registers
        1316. 8.1.5.1316 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1396 Registers
        1317. 8.1.5.1317 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1397 Registers
        1318. 8.1.5.1318 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1398 Registers
        1319. 8.1.5.1319 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1399 Registers
        1320. 8.1.5.1320 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1400 Registers
        1321. 8.1.5.1321 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1401 Registers
        1322. 8.1.5.1322 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1402 Registers
        1323. 8.1.5.1323 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1403 Registers
        1324. 8.1.5.1324 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1404 Registers
        1325. 8.1.5.1325 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1405 Registers
        1326. 8.1.5.1326 Access Table
    2. 8.2 Region-based Address Translation (RAT) Module
      1. 8.2.1 RAT Functional Description
        1. 8.2.1.1 RAT Availability
        2. 8.2.1.2 RAT Operation
        3. 8.2.1.3 RAT Error Logging
      2. 8.2.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GICSS)
        1. 9.2.1.1 GICSS Overview
          1. 9.2.1.1.1 GICSS Features
          2. 9.2.1.1.2 GICSS Not Supported Features
        2. 9.2.1.2 GICSS Integration
        3. 9.2.1.3 GICSS Functional Description
          1. 9.2.1.3.1 GICSS Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GICSS Interrupt Types
          4. 9.2.1.3.4 GICSS Interfaces
          5. 9.2.1.3.5 GICSS Interrupt Outputs
          6. 9.2.1.3.6 GICSS ECC Support
          7. 9.2.1.3.7 GICSS AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GICSS Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GICSS0_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 MCU_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 MCU_GPIOMUX_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 MAIN Domain Interrupt Maps
        1. 9.4.1.1 GICSS0 Interrupt Map
          1. 9.4.1.1.1 GICSS0 PPI Interrupt Map
          2. 9.4.1.1.2 GICSS0 SPI Interrupt Map
        2. 9.4.1.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.1.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.1.4 R5FSS1_CORE0 Interrupt Map
        5. 9.4.1.5 R5FSS1_CORE1 Interrupt Map
        6. 9.4.1.6 PRU_ICSSG0 Interrupt Map
        7. 9.4.1.7 PRU_ICSSG1 Interrupt Map
        8. 9.4.1.8 GPIOMUX_INTRTR0 Interrupt Map
        9. 9.4.1.9 ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_M4FSS Interrupt Map
        2. 9.4.2.2 MCU_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
    5. 9.5 Time Sync and Compare Interrupt Events
      1. 9.5.1 CMPEVT_INTRTR0 Interrupt Map
      2. 9.5.2 TIMESYNC_INTRTR0 Interrupt Map
  12. 10Time Sync
    1. 10.1 Time Sync Module (CPTS)
      1. 10.1.1 CPTS Overview
        1. 10.1.1.1 CPTS Features
        2. 10.1.1.2 CPTS Not Supported Features
      2. 10.1.2 CPTS Integration
      3. 10.1.3 CPTS Functional Description
        1. 10.1.3.1  CPTS Architecture
        2. 10.1.3.2  CPTS Initialization
        3. 10.1.3.3  32-bit Time Stamp Value
        4. 10.1.3.4  64-bit Time Stamp Value
          1. 10.1.3.4.1 64-Bit Timestamp Nudge
          2. 10.1.3.4.2 64-bit Timestamp PPM
        5. 10.1.3.5  Event FIFO
        6. 10.1.3.6  Timestamp Compare Output
          1. 10.1.3.6.1 Non-Toggle Mode
          2. 10.1.3.6.2 Toggle Mode
        7. 10.1.3.7  Timestamp Sync Output
        8. 10.1.3.8  Timestamp GENF Output
          1. 10.1.3.8.1 GENFn Nudge
          2. 10.1.3.8.2 GENFn PPM
        9. 10.1.3.9  Time Sync Events
          1. 10.1.3.9.1 Time Stamp Push Event
          2. 10.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 10.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 10.1.3.9.4 Hardware Time Stamp Push Event
        10. 10.1.3.10 Timestamp Compare Event
        11. 10.1.3.11 CPTS Interrupt Handling
      4. 10.1.4 CPTS Registers
    2. 10.2 Timer Manager
      1. 10.2.1 Timer Manager Overview
        1. 10.2.1.1 Timer Manager Features
        2. 10.2.1.2 Timer Manager Not Supported Features
      2. 10.2.2 Timer Manager Integration
      3. 10.2.3 Timer Manager Functional Description
        1. 10.2.3.1 Timer Manager Function Overview
        2. 10.2.3.2 Timer Counter
          1. 10.2.3.2.1 Timer Counter Rollover
        3. 10.2.3.3 Timer Control Module (FSM)
        4. 10.2.3.4 Timer Reprogramming
          1. 10.2.3.4.1 Periodic Hardware Timers
        5. 10.2.3.5 Event FIFO
        6. 10.2.3.6 Timer Manager Unmapped Events mapping
      4. 10.2.4 Timer Manager Programming Guide
        1. 10.2.4.1 Timer Manager Low-level Programming Models
          1. 10.2.4.1.1 Surrounding Modules Global Initialization
          2. 10.2.4.1.2 Initialization Sequence
          3. 10.2.4.1.3 Real-time Operating Requirements
            1. 10.2.4.1.3.1 Timer Touch
            2. 10.2.4.1.3.2 Timer Disable
            3. 10.2.4.1.3.3 Timer Enable
          4. 10.2.4.1.4 Power Up/Power Down Sequence
      5. 10.2.5 Timer Manager Registers
        1. 10.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 10.2.5.2 TIMERMGR_CFG_TIMERS Registers
    3. 10.3 Time Sync and Compare Events
      1. 10.3.1 Time Sync Architecture
        1. 10.3.1.1 Time Sync Architecture Overview
      2. 10.3.2 Time Sync Routers
        1. 10.3.2.1 Time Sync Routers Overview
        2. 10.3.2.2 Time Sync Routers Integration
          1. 10.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 10.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 10.3.2.3 Time Sync Routers Registers
          1. 10.3.2.3.1 TIMESYNC_EVENT_INTROUTER Registers
            1. 10.3.2.3.1.1 INTR_ROUTER_CFG_TIMESYNC_EVENT_INTROUTER_PID Registers
            2. 10.3.2.3.1.2 INTR_ROUTER_CFG_TIMESYNC_EVENT_INTROUTER_MUXCNTL Registers
            3. 10.3.2.3.1.3 Access Table
          2. 10.3.2.3.2 CMP_EVENT_INTROUTER Registers
            1. 10.3.2.3.2.1 INTR_ROUTER_CFG_CMP_EVENT_INTROUTER_PID Registers
            2. 10.3.2.3.2.2 INTR_ROUTER_CFG_CMP_EVENT_INTROUTER_MUXCNTL Registers
            3. 10.3.2.3.2.3 Access Table
      3. 10.3.3 Time Sync Event Sources
  13. 11Data Movement Architecture
    1. 11.1 Data Movement Architecture Overview
      1. 11.1.1 Overview
        1. 11.1.1.1 Ring Accelerator (RINGACC)
        2. 11.1.1.2 Secure Proxy (SEC_PROXY)
        3. 11.1.1.3 Interrupt Aggregator (INTAGGR)
        4. 11.1.1.4 Packet DMA (PKTDMA)
          1. 11.1.1.4.1 PKTDMA Submodule Descriptions
            1. 11.1.1.4.1.1  Bus Interface Unit
            2. 11.1.1.4.1.2  Config CR
            3. 11.1.1.4.1.3  Configuration Registers
              1. 11.1.1.4.1.3.1 RX State Mapping
              2. 11.1.1.4.1.3.2 TX State Mapping
            4. 11.1.1.4.1.4  Tx Packet DMA Unit
            5. 11.1.1.4.1.5  Tx Packet Coherency Unit
            6. 11.1.1.4.1.6  Tx Per Channel Buffers
            7. 11.1.1.4.1.7  Rx Per Channel Buffers
            8. 11.1.1.4.1.8  Rx Packet DMA Unit
            9. 11.1.1.4.1.9  Rx Packet Coherency Unit
            10. 11.1.1.4.1.10 Event Handler
          2. 11.1.1.4.2 Channel Classes
        5. 11.1.1.5 Block Copy DMA (BCDMA)
          1. 11.1.1.5.1 BCDMA Submodule Descriptions
            1. 11.1.1.5.1.1  Bus Interface Unit
            2. 11.1.1.5.1.2  Config CR
            3. 11.1.1.5.1.3  Configuration Registers
              1. 11.1.1.5.1.3.1 BCDMA Mapping Table
            4. 11.1.1.5.1.4  Read Unit(s)
            5. 11.1.1.5.1.5  TR Coherency Unit
            6. 11.1.1.5.1.6  Per-Copy-Channel Buffers
            7. 11.1.1.5.1.7  Tx Per-Split-Channel Buffers
            8. 11.1.1.5.1.8  Rx Per-Split-Channel Buffers
            9. 11.1.1.5.1.9  Write Unit(s)
            10. 11.1.1.5.1.10 Event Coherency Unit
            11. 11.1.1.5.1.11 Event Handler
          2. 11.1.1.5.2 Channel Classes
      2. 11.1.2 Definition of Terms
      3. 11.1.3 DMSS Hardware/Software Interface
        1. 11.1.3.1 Data Buffers
        2. 11.1.3.2 Descriptors
          1. 11.1.3.2.1 Host Packet Descriptor
          2. 11.1.3.2.2 Host Buffer Descriptor
          3. 11.1.3.2.3 Transfer Request Descriptor
        3. 11.1.3.3 Transfer Request Record
          1. 11.1.3.3.1 Overview
          2. 11.1.3.3.2 Addressing Algorithm
            1. 11.1.3.3.2.1 Linear Addressing (Forward)
          3. 11.1.3.3.3 Transfer Request Formats
          4. 11.1.3.3.4 Flags Field Definition
            1. 11.1.3.3.4.1 Type: TR Type Field
            2. 11.1.3.3.4.2 EVENT_SIZE: Event Generation Definition
            3. 11.1.3.3.4.3 TRIGGER_INFO: TR Triggers
            4. 11.1.3.3.4.4 TRIGGERX_TYPE: Trigger Type
            5. 11.1.3.3.4.5 TRIGGERX: Trigger Selection
            6. 11.1.3.3.4.6 Configuration Specific Flags Definition
          5. 11.1.3.3.5 TR Address and Size Attributes
            1. 11.1.3.3.5.1  ICNT0
            2. 11.1.3.3.5.2  ICNT1
            3. 11.1.3.3.5.3  ADDR
            4. 11.1.3.3.5.4  DIM1
            5. 11.1.3.3.5.5  ICNT2
            6. 11.1.3.3.5.6  ICNT3
            7. 11.1.3.3.5.7  DIM2
            8. 11.1.3.3.5.8  DIM3
            9. 11.1.3.3.5.9  DDIM1
            10. 11.1.3.3.5.10 DADDR
            11. 11.1.3.3.5.11 DDIM2
            12. 11.1.3.3.5.12 DDIM3
            13. 11.1.3.3.5.13 DICNT0
            14. 11.1.3.3.5.14 DICNT1
            15. 11.1.3.3.5.15 DICNT2
            16. 11.1.3.3.5.16 DICNT3
        4. 11.1.3.4 Transfer Response Record
          1. 11.1.3.4.1 STATUS Field Definition
            1. 11.1.3.4.1.1 STATUS_TYPE Definitions
              1. 11.1.3.4.1.1.1 Transfer Error
              2. 11.1.3.4.1.1.2 Aborted Error
              3. 11.1.3.4.1.1.3 Submission Error
              4. 11.1.3.4.1.1.4 Unsupported Feature
              5. 11.1.3.4.1.1.5 Transfer Exception
              6. 11.1.3.4.1.1.6 Teardown Flush
        5. 11.1.3.5 Channels
        6. 11.1.3.6 Flows
        7. 11.1.3.7 Queues
          1. 11.1.3.7.1 Queue Types
            1. 11.1.3.7.1.1 Transmit Queues
            2. 11.1.3.7.1.2 Transmit Completion Queues
            3. 11.1.3.7.1.3 Free Descriptor / Buffer Queues
            4. 11.1.3.7.1.4 Receive Queues
            5. 11.1.3.7.1.5 Ring Based Queues Implementation
      4. 11.1.4 Operational Description
        1. 11.1.4.1  Resource Allocation
        2. 11.1.4.2  PKTDMA/BCDMA - Ring Operation
          1. 11.1.4.2.1 Queue Initialization
          2. 11.1.4.2.2 Queueing Entries
          3. 11.1.4.2.3 De-queueing Entries
        3. 11.1.4.3  PKTDMA/BCDMA - Output Event Generation
        4. 11.1.4.4  PKTDMA - Transmit Channel Setup
        5. 11.1.4.5  PKTDMA - Transmit Channel Pause
        6. 11.1.4.6  PKTDMA - Transmit Channel Teardown
        7. 11.1.4.7  PKTDMA - Transmit Operation
        8. 11.1.4.8  PKTDMA - Receive Free Descriptor / Buffer Queue Setup
        9. 11.1.4.9  PKTDMA - Receive Channel Setup
        10. 11.1.4.10 PKTDMA - Receive Channel Teardown
        11. 11.1.4.11 PKTDMA - Receive Channel Pause
        12. 11.1.4.12 PKTDMA - Receive Operation
        13. 11.1.4.13 BCDMA - Block Copy Channel Setup
        14. 11.1.4.14 BCDMA - Block Copy Channel Pause
        15. 11.1.4.15 BCDMA - Block Copy Channel Teardown
        16. 11.1.4.16 BCDMA - Block Copy Operation (TR Packet)
        17. 11.1.4.17 BCDMA - Block Copy Error/Exception Handling
          1. 11.1.4.17.1 Null Icnt0 Error
          2. 11.1.4.17.2 Unsupported TR Type
          3. 11.1.4.17.3 Bus Errors
        18. 11.1.4.18 BCDMA - Split Transmit Channel Setup
        19. 11.1.4.19 BCDMA - Split Transmit Operation Pause
        20. 11.1.4.20 BCDMA - Split Transmit Channel Teardown
        21. 11.1.4.21 BCDMA - Split Transmit Operation (TR Packet)
        22. 11.1.4.22 BCDMA - Split Transmit Error / Exception Handling
          1. 11.1.4.22.1 Null Icnt0 Error
          2. 11.1.4.22.2 Unsupported TR Type
          3. 11.1.4.22.3 Bus Errors
        23. 11.1.4.23 BCDMA - Split Receive Channel Setup
        24. 11.1.4.24 BCDMA - Split Receive Channel Pause
        25. 11.1.4.25 BCDMA - Split Receive Channel Teardown
        26. 11.1.4.26 BCDMA - Split Receive Operation (TR Packet)
        27. 11.1.4.27 BCDMA - Split Receive Error / Exception Handling
          1. 11.1.4.27.1 PKTDMA Exception Conditions
            1. 11.1.4.27.1.1 Descriptor Starvation
            2. 11.1.4.27.1.2 Protocol Errors
            3. 11.1.4.27.1.3 Dropped Packets
            4. 11.1.4.27.1.4 Long Packet
          2. 11.1.4.27.2 BCDMA Exception Conditions
            1. 11.1.4.27.2.1 Reception of EOL Delimiter
            2. 11.1.4.27.2.2 EOP Asserted Prematurely (Short Packet)
            3. 11.1.4.27.2.3 EOP Asserted Late (Long Packets)
            4. 11.1.4.27.2.4 Descriptor Starvation
    2. 11.2 Data Movement Subsystem (DMSS)
      1. 11.2.1 Data Movement Subsystem (DMSS)
        1. 11.2.1.1 DMSS Overview
        2. 11.2.1.2 DMSS Integration
          1. 11.2.1.2.1 DMSS Integration Attributes
          2. 11.2.1.2.2 DMSS Clocks
          3. 11.2.1.2.3 DMSS Resets
          4. 11.2.1.2.4 DMSS Interrupt Requests
          5. 11.2.1.2.5 DMSS L2G Interrupt Inputs
          6. 11.2.1.2.6 DMSS DMA Events
          7. 11.2.1.2.7 Global Event Map
          8. 11.2.1.2.8 PSI-L System Thread Map
        3. 11.2.1.3 DMSS Functional Description
        4. 11.2.1.4 DMSS Interrupt Configuration
          1. 11.2.1.4.1 DMSS Event and Interrupt Flow
            1. 11.2.1.4.1.1 DMSS Interrupt Description
        5. 11.2.1.5 DMSS Top-Level Registers
          1. 11.2.1.5.1 DMASS_PKTDMA_0 Registers
          2. 11.2.1.5.2 DMASS_BCDMA_0 Registers
      2. 11.2.2 Ring Accelerator (RINGACC)
        1. 11.2.2.1 RINGACC Overview
          1. 11.2.2.1.1 RINGACC Features
          2. 11.2.2.1.2 RINGACC Not Supported Features
          3. 11.2.2.1.3 RINGACC Parameters
        2. 11.2.2.2 RINGACC Integration
          1. 11.2.2.2.1 RINGACC Integration Attributes
          2. 11.2.2.2.2 RINGACC Clocks
          3. 11.2.2.2.3 RINGACC Resets
          4. 11.2.2.2.4 RINGACC Interrupt Requests
          5. 11.2.2.2.5 RINGACC Outbound Events
        3. 11.2.2.3 RINGACC Functional Description
          1. 11.2.2.3.1 Block Diagram
            1. 11.2.2.3.1.1  Configuration Registers
            2. 11.2.2.3.1.2  Source Command FIFO
            3. 11.2.2.3.1.3  Source Write Data FIFO
            4. 11.2.2.3.1.4  Source Read Data FIFO
            5. 11.2.2.3.1.5  Source Write Status FIFO
            6. 11.2.2.3.1.6  Main State Machine
            7. 11.2.2.3.1.7  Destination Command FIFO
            8. 11.2.2.3.1.8  Destination Write Data FIFO
            9. 11.2.2.3.1.9  Destination Read Data FIFO
            10. 11.2.2.3.1.10 Destination Write Status FIFO
          2. 11.2.2.3.2 RINGACC Functional Operation
            1. 11.2.2.3.2.1 Queue Modes
              1. 11.2.2.3.2.1.1 Ring Mode
              2. 11.2.2.3.2.1.2 Messaging Mode
              3. 11.2.2.3.2.1.3 Credentials Mode
              4. 11.2.2.3.2.1.4 Peek Support
              5. 11.2.2.3.2.1.5 Index Register Operation
            2. 11.2.2.3.2.2 VBUSM Target Ring Operations
            3. 11.2.2.3.2.3 VBUSM Initiator Interface Command ID Selection
            4. 11.2.2.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 11.2.2.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 11.2.2.3.2.6 Host Doorbell Access
            7. 11.2.2.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 11.2.2.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 11.2.2.3.2.9 Mismatched Element Size Handling
          3. 11.2.2.3.3 Events
          4. 11.2.2.3.4 Bus Error Handling
          5. 11.2.2.3.5 Monitors
            1. 11.2.2.3.5.1 Threshold Monitor
            2. 11.2.2.3.5.2 Watermark Monitor
            3. 11.2.2.3.5.3 Starvation Monitor
            4. 11.2.2.3.5.4 Statistics Monitor
            5. 11.2.2.3.5.5 Overflow
            6. 11.2.2.3.5.6 Ring Update Port
            7. 11.2.2.3.5.7 Tracing
        4. 11.2.2.4 RINGACC Registers
          1. 11.2.2.4.1 DMASS_RINGACC_0 Registers
      3. 11.2.3 Secure Proxy (SEC_PROXY)
        1. 11.2.3.1 Secure Proxy Overview
          1. 11.2.3.1.1 Secure Proxy Features
          2. 11.2.3.1.2 Secure Proxy Parameters
          3. 11.2.3.1.3 Secure Proxy Not Supported Features
        2. 11.2.3.2 Secure Proxy Integration
          1. 11.2.3.2.1 Secure Proxy Integration Attributes
          2. 11.2.3.2.2 Secure Proxy Clocks
          3. 11.2.3.2.3 Secure Proxy Resets
          4. 11.2.3.2.4 Secure Proxy Interrupt Requests
          5. 11.2.3.2.5 Secure Proxy DMA Events
        3. 11.2.3.3 Secure Proxy Functional Description
          1. 11.2.3.3.1  Targets
          2. 11.2.3.3.2  Buffers
          3. 11.2.3.3.3  Proxy Thread Sizes
          4. 11.2.3.3.4  Proxy Thread Interleaving
          5. 11.2.3.3.5  Proxy States
          6. 11.2.3.3.6  Proxy Host Access
          7. 11.2.3.3.7  Permission Inheritance
          8. 11.2.3.3.8  Resource Association
          9. 11.2.3.3.9  Direction
          10. 11.2.3.3.10 Threshold Events
          11. 11.2.3.3.11 Error Events
          12. 11.2.3.3.12 Bus Error and Credits
          13. 11.2.3.3.13 Debug
        4. 11.2.3.4 Secure Proxy Registers
          1. 11.2.3.4.1 DMASS_SEC_PROXY_0 Registers
      4. 11.2.4 Interrupt Aggregator (INTAGGR)
        1. 11.2.4.1 INTAGGR Overview
          1. 11.2.4.1.1 INTAGGR Features
          2. 11.2.4.1.2 INTAGGR Parameters
        2. 11.2.4.2 INTAGGR Integration
          1. 11.2.4.2.1 INTAGGR Integration Attributes
          2. 11.2.4.2.2 INTAGGR Clocks
          3. 11.2.4.2.3 INTAGGR Resets
          4. 11.2.4.2.4 INTAGGR Interrupt Requests
          5. 11.2.4.2.5 INTAGGR DMA Events
        3. 11.2.4.3 INTAGGR Functional Description
          1. 11.2.4.3.1 Submodule Descriptions
          2. 11.2.4.3.2 General Functionality
        4. 11.2.4.4 INTAGGR Registers
          1. 11.2.4.4.1 DMASS_INTAGGR_0 Registers
      5. 11.2.5 Packet Streaming Interface Link (PSI-L)
        1. 11.2.5.1 PSI-L Overview
        2. 11.2.5.2 PSI-L Functional Description
          1. 11.2.5.2.1 PSI-L Introduction
          2. 11.2.5.2.2 PSI-L Operation
        3. 11.2.5.3 PSI-L Configuration Registers
          1. 11.2.5.3.1 DMASS_PSILCFG_0 Registers
          2. 11.2.5.3.2 DMASS_PSILSS_0 Registers
    3. 11.3 Peripheral DMA (PDMA)
      1. 11.3.1 PDMA Controller
        1. 11.3.1.1 PDMA Overview
          1. 11.3.1.1.1 PDMA Features
            1. 11.3.1.1.1.1 PDMA0 Features
            2. 11.3.1.1.1.2 PDMA1 Features
        2. 11.3.1.2 PDMA Integration
          1. 11.3.1.2.1 PDMA Integration in MAIN Domain
        3. 11.3.1.3 PDMA Functional Description
          1. 11.3.1.3.1 PDMA Functional Blocks
            1. 11.3.1.3.1.1 Scheduler
            2. 11.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 11.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 11.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 11.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 11.3.1.3.2 PDMA General Functionality
            1. 11.3.1.3.2.1 Operational States
            2. 11.3.1.3.2.2 Clock Stop
            3. 11.3.1.3.2.3 Emulation Control
          3. 11.3.1.3.3 PDMA Events and Flow Control
            1. 11.3.1.3.3.1 Channel Types
              1. 11.3.1.3.3.1.1 X-Y FIFO Mode
              2. 11.3.1.3.3.1.2 MCAN Mode
            2. 11.3.1.3.3.2 Channel Triggering
            3. 11.3.1.3.3.3 Completion Events
          4. 11.3.1.3.4 PDMA Transmit Operation
            1. 11.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 11.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 11.3.1.3.4.3 Destination Channel Initialization
              1. 11.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 11.3.1.3.4.3.2 Static Transfer Request Setup
              3. 11.3.1.3.4.3.3 PSI-L Destination Thread Enables
            4. 11.3.1.3.4.4 Data Transfer
              1. 11.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 11.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 11.3.1.3.4.4.2 MCAN Mode Channel
                1. 11.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 11.3.1.3.4.4.3 AASRC Mode Channel
            5. 11.3.1.3.4.5 Tx Pause
            6. 11.3.1.3.4.6 Tx Teardown
            7. 11.3.1.3.4.7 Tx Channel Reset
            8. 11.3.1.3.4.8 Tx Debug/State Registers
          5. 11.3.1.3.5 PDMA Receive Operation
            1. 11.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 11.3.1.3.5.2 Source Channel Initialization
              1. 11.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 11.3.1.3.5.2.2 Static Transfer Request Setup
              3. 11.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 11.3.1.3.5.3 Data Transfer
              1. 11.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 11.3.1.3.5.3.2 MCAN Mode Channel
                1. 11.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 11.3.1.3.5.3.3 AASRC Mode Channel
            4. 11.3.1.3.5.4 Rx Pause
            5. 11.3.1.3.5.5 Rx Teardown
            6. 11.3.1.3.5.6 Rx Channel Reset
            7. 11.3.1.3.5.7 Rx Debug/State Register
          6. 11.3.1.3.6 PDMA ECC Support
        4. 11.3.1.4 PDMA Registers
          1. 11.3.1.4.1 PDMA0 ECC Registers
          2. 11.3.1.4.2 PDMA1 ECC Registers
          3. 11.3.1.4.3 PDMA PSI-L TX Configuration Registers
          4. 11.3.1.4.4 PDMA PSI-L RX Configuration Registers
      2. 11.3.2 PDMA Sources
        1. 11.3.2.1 PDMA0 Event Map
        2. 11.3.2.2 PDMA1 Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MAIN Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in MCU Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 4200
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in MCU Domain
          2. 12.1.3.3.2 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.4.1 MCSPI Overview
          1. 12.1.4.1.1 SPI Features
          2. 12.1.4.1.2 SPI Not Supported Features
        2. 12.1.4.2 MCSPI Environment
          1. 12.1.4.2.1 Basic MCSPI Pins for Controller Mode
          2. 12.1.4.2.2 Basic MCSPI Pins for Peripheral Mode
          3. 12.1.4.2.3 MCSPI Protocol and Data Format
            1. 12.1.4.2.3.1 Transfer Format
          4. 12.1.4.2.4 MCSPI in Controller Mode
          5. 12.1.4.2.5 MCSPI in Peripheral Mode
        3. 12.1.4.3 MCSPI Integration
          1. 12.1.4.3.1 MCSPI Integration in MCU Domain
          2. 12.1.4.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.4.4 MCSPI Functional Description
          1. 12.1.4.4.1 SPI Block Diagram
          2. 12.1.4.4.2 MCSPI Reset
          3. 12.1.4.4.3 MCSPI Controller Mode
            1. 12.1.4.4.3.1 Controller Mode Features
            2. 12.1.4.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.4.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.4.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.4.4.3.5 Single-Channel Controller Mode
              1. 12.1.4.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.4.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.4.4.3.5.3 Turbo Mode
            6. 12.1.4.4.3.6 Start-Bit Mode
            7. 12.1.4.4.3.7 Chip-Select Timing Control
            8. 12.1.4.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.4.4.3.8.1 Clock Ratio Granularity
          4. 12.1.4.4.4 MCSPI Peripheral Mode
            1. 12.1.4.4.4.1 Dedicated Resources
            2. 12.1.4.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.4.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.4.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.4.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.4.4.6 MCSPI FIFO Buffer Management
            1. 12.1.4.4.6.1 Buffer Almost Full
            2. 12.1.4.4.6.2 Buffer Almost Empty
            3. 12.1.4.4.6.3 End of Transfer Management
            4. 12.1.4.4.6.4 Multiple MCSPI Word Access
            5. 12.1.4.4.6.5 First MCSPI Word Delay
          7. 12.1.4.4.7 MCSPI Interrupts
            1. 12.1.4.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.4.4.7.1.1 TXx_EMPTY
              2. 12.1.4.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.1.3 RXx_ FULL
              4. 12.1.4.4.7.1.4 End Of Word Count
            2. 12.1.4.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.4.4.7.2.1 TXx_EMPTY
              2. 12.1.4.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.2.3 RXx_FULL
              4. 12.1.4.4.7.2.4 RX0_OVERFLOW
              5. 12.1.4.4.7.2.5 End Of Word Count
            3. 12.1.4.4.7.3 Interrupt-Driven Operation
            4. 12.1.4.4.7.4 Polling
          8. 12.1.4.4.8 MCSPI DMA Requests
          9. 12.1.4.4.9 MCSPI Power Saving Management
            1. 12.1.4.4.9.1 Normal Mode
            2. 12.1.4.4.9.2 Idle Mode
              1. 12.1.4.4.9.2.1 Force-Idle Mode
        5. 12.1.4.5 MCSPI Programming Guide
          1. 12.1.4.5.1 MCSPI Global Initialization
            1. 12.1.4.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.4.5.1.2 MCSPI Global Initialization
              1. 12.1.4.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.4.5.2 MCSPI Operational Mode Configuration
            1. 12.1.4.5.2.1 MCSPI Operational Modes
              1. 12.1.4.5.2.1.1 Common Transfer Sequence
              2. 12.1.4.5.2.1.2 End of Transfer Sequences
              3. 12.1.4.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.4.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.4.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.4.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.4.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.4.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.4.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.4.5.2.1.7 Peripheral Receive-Only
              8. 12.1.4.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.4.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.4.5.2.1.8.5 Transmit-Only
                6. 12.1.4.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.4.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.4.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.4.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.4.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.4.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.4.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.4.6 MCSPI Registers
      5. 12.1.5 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.5.1 UART Overview
          1. 12.1.5.1.1 UART Features
          2. 12.1.5.1.2 IrDA Features
          3. 12.1.5.1.3 CIR Features
          4. 12.1.5.1.4 UART Not Supported Features
        2. 12.1.5.2 UART Environment
          1. 12.1.5.2.1 UART Functional Interfaces
            1. 12.1.5.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.5.2.1.2 UART Interface Description
            3. 12.1.5.2.1.3 UART Protocol and Data Format
            4. 12.1.5.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.5.2.2 RS-485 Functional Interfaces
            1. 12.1.5.2.2.1 System Using RS-485 Communication
            2. 12.1.5.2.2.2 RS-485 Interface Description
          3. 12.1.5.2.3 IrDA Functional Interfaces
            1. 12.1.5.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.5.2.3.2 IrDA Interface Description
            3. 12.1.5.2.3.3 IrDA Protocol and Data Format
              1. 12.1.5.2.3.3.1 SIR Mode
                1. 12.1.5.2.3.3.1.1 Frame Format
                2. 12.1.5.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.5.2.3.3.1.3 Abort Sequence
                4. 12.1.5.2.3.3.1.4 Pulse Shaping
                5. 12.1.5.2.3.3.1.5 Encoder
                6. 12.1.5.2.3.3.1.6 Decoder
                7. 12.1.5.2.3.3.1.7 IR Address Checking
              2. 12.1.5.2.3.3.2 SIR Free-Format Mode
              3. 12.1.5.2.3.3.3 MIR Mode
                1. 12.1.5.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.5.2.3.3.3.2 SIP Generation
              4. 12.1.5.2.3.3.4 FIR Mode
          4. 12.1.5.2.4 CIR Functional Interfaces
            1. 12.1.5.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.5.2.4.2 CIR Interface Description
            3. 12.1.5.2.4.3 CIR Protocol and Data Format
              1. 12.1.5.2.4.3.1 Carrier Modulation
              2. 12.1.5.2.4.3.2 Pulse Duty Cycle
              3. 12.1.5.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.5.3 UART Integration
          1. 12.1.5.3.1 UART Integration in MCU Domain
          2. 12.1.5.3.2 UART Integration in MAIN Domain
        4. 12.1.5.4 UART Functional Description
          1. 12.1.5.4.1 UART Block Diagram
          2. 12.1.5.4.2 UART Clock Configuration
          3. 12.1.5.4.3 UART Software Reset
            1. 12.1.5.4.3.1 Independent TX/RX
          4. 12.1.5.4.4 UART Power Management
            1. 12.1.5.4.4.1 UART Mode Power Management
              1. 12.1.5.4.4.1.1 Module Power Saving
              2. 12.1.5.4.4.1.2 System Power Saving
            2. 12.1.5.4.4.2 IrDA Mode Power Management
              1. 12.1.5.4.4.2.1 Module Power Saving
              2. 12.1.5.4.4.2.2 System Power Saving
            3. 12.1.5.4.4.3 CIR Mode Power Management
              1. 12.1.5.4.4.3.1 Module Power Saving
              2. 12.1.5.4.4.3.2 System Power Saving
            4. 12.1.5.4.4.4 Local Power Management
          5. 12.1.5.4.5 UART Interrupt Requests
            1. 12.1.5.4.5.1 UART Mode Interrupt Management
              1. 12.1.5.4.5.1.1 UART Interrupts
              2. 12.1.5.4.5.1.2 Wake-Up Interrupt
            2. 12.1.5.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.5.4.5.2.1 IrDA Interrupts
              2. 12.1.5.4.5.2.2 Wake-Up Interrupts
            3. 12.1.5.4.5.3 CIR Mode Interrupt Management
              1. 12.1.5.4.5.3.1 CIR Interrupts
              2. 12.1.5.4.5.3.2 Wake-Up Interrupts
          6. 12.1.5.4.6 UART FIFO Management
            1. 12.1.5.4.6.1 FIFO Trigger
              1. 12.1.5.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.5.4.6.1.2 Receive FIFO Trigger
            2. 12.1.5.4.6.2 FIFO Interrupt Mode
            3. 12.1.5.4.6.3 FIFO Polled Mode Operation
            4. 12.1.5.4.6.4 FIFO DMA Mode Operation
              1. 12.1.5.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.5.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.5.4.6.4.3 DMA Transmission
              4. 12.1.5.4.6.4.4 DMA Reception
          7. 12.1.5.4.7 UART Mode Selection
            1. 12.1.5.4.7.1 Register Access Modes
              1. 12.1.5.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.5.4.7.1.2 Register Access Submode
              3. 12.1.5.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.5.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.5.4.7.2.1 Registers Available for the UART Function
              2. 12.1.5.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.5.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.5.4.8 UART Protocol Formatting
            1. 12.1.5.4.8.1 UART Mode
              1. 12.1.5.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.5.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.1.3 UART Data Formatting
                1. 12.1.5.4.8.1.3.1 Frame Formatting
                2. 12.1.5.4.8.1.3.2 Hardware Flow Control
                3. 12.1.5.4.8.1.3.3 Software Flow Control
                  1. 1.5.4.8.1.3.3.1 Receive (RX)
                  2. 1.5.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.5.4.8.1.3.4 Autobauding Modes
                5. 12.1.5.4.8.1.3.5 Error Detection
                6. 12.1.5.4.8.1.3.6 Overrun During Receive
                7. 12.1.5.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.5.4.8.1.3.7.1 Time-Out Counter
                  2. 1.5.4.8.1.3.7.2 Break Condition
            2. 12.1.5.4.8.2 RS-485 Mode
              1. 12.1.5.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.5.4.8.3 IrDA Mode
              1. 12.1.5.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.5.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.3.3 IrDA Data Formatting
                1. 12.1.5.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.5.4.8.3.3.2  IrDA Reception Control
                3. 12.1.5.4.8.3.3.3  IR Address Checking
                4. 12.1.5.4.8.3.3.4  Frame Closing
                5. 12.1.5.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.5.4.8.3.3.6  Error Detection
                7. 12.1.5.4.8.3.3.7  Underrun During Transmission
                8. 12.1.5.4.8.3.3.8  Overrun During Receive
                9. 12.1.5.4.8.3.3.9  Status FIFO
                10. 12.1.5.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.5.4.8.3.3.11 Time-guard
              4. 12.1.5.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.5.4.8.3.4.1 Abort Sequence
                2. 12.1.5.4.8.3.4.2 Pulse Shaping
                3. 12.1.5.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.5.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.5.4.8.4 CIR Mode
              1. 12.1.5.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.5.4.8.4.2 CIR Data Formatting
                1. 12.1.5.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.5.4.8.4.2.2 CIR Transmission
                3. 12.1.5.4.8.4.2.3 CIR Reception
        5. 12.1.5.5 UART Programming Guide
          1. 12.1.5.5.1 UART Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 UART Module Global Initialization
          2. 12.1.5.5.2 UART Mode selection
          3. 12.1.5.5.3 UART Submode selection
          4. 12.1.5.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.5.5.4.1 DMA mode Settings
            2. 12.1.5.5.4.2 FIFO Trigger Settings
          5. 12.1.5.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.5.5.5.1 Baud rate settings
            2. 12.1.5.5.5.2 Interrupt settings
            3. 12.1.5.5.5.3 Protocol settings
            4. 12.1.5.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.5.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.5.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.5.5.6.1 Hardware Flow Control Configuration
            2. 12.1.5.5.6.2 Software Flow Control Configuration
          7. 12.1.5.5.7 IrDA Programming Model
            1. 12.1.5.5.7.1 SIR mode
              1. 12.1.5.5.7.1.1 Receive
              2. 12.1.5.5.7.1.2 Transmit
            2. 12.1.5.5.7.2 MIR mode
              1. 12.1.5.5.7.2.1 Receive
              2. 12.1.5.5.7.2.2 Transmit
            3. 12.1.5.5.7.3 FIR mode
              1. 12.1.5.5.7.3.1 Receive
              2. 12.1.5.5.7.3.2 Transmit
        6. 12.1.5.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet Switch (CPSW3G)
        1. 12.2.1.1 CPSW0 Overview
          1. 12.2.1.1.1 CPSW0 Features
          2. 12.2.1.1.2 CPSW0 Not Supported Features
          3. 12.2.1.1.3 CPSW Terminology
        2. 12.2.1.2 CPSW0 Environment
          1. 12.2.1.2.1 CPSW0 RMII Interface
          2. 12.2.1.2.2 CPSW0 RGMII Interface
        3. 12.2.1.3 CPSW0 Integration
        4. 12.2.1.4 CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_3G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 3-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1  Multicast Address Table Entry
                2. 12.2.1.4.6.1.9.2  OUI Unicast Address Table Entry
                3. 12.2.1.4.6.1.9.3  Unicast Address Table Entry (Bit 40 == 0)
                4. 12.2.1.4.6.1.9.4  Multicast Address Table Entry (Bit 40==1)
                5. 12.2.1.4.6.1.9.5  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                6. 12.2.1.4.6.1.9.6  VLAN/Multicast Address Table Entry (Bit 40==1)
                7. 12.2.1.4.6.1.9.7  Inner VLAN Table Entry
                8. 12.2.1.4.6.1.9.8  Outer VLAN Table Entry
                9. 12.2.1.4.6.1.9.9  EtherType Table Entry
                10. 12.2.1.4.6.1.9.10 IPv4 Table Entry
                11. 12.2.1.4.6.1.9.11 IPv6 Table Entry High
                12. 12.2.1.4.6.1.9.12 IPv6 Table Entry Low
              10. 12.2.1.4.6.1.10 Multicast Address
                1. 12.2.1.4.6.1.10.1 Multicast Ranges
              11. 12.2.1.4.6.1.11 Aging and Auto Aging
              12. 12.2.1.4.6.1.12 ALE Policing and Classification
                1. 12.2.1.4.6.1.12.1 ALE Policing
                2. 12.2.1.4.6.1.12.2 Classifier to Host Thread Mapping
                3. 12.2.1.4.6.1.12.3 ALE Classification
                  1. 2.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping
              13. 12.2.1.4.6.1.13 Mirroring
              14. 12.2.1.4.6.1.14 Trunking
              15. 12.2.1.4.6.1.15 DSCP
              16. 12.2.1.4.6.1.16 Packet Forwarding Processes
                1. 12.2.1.4.6.1.16.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.16.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.16.3 Egress Process
                4. 12.2.1.4.6.1.16.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.16.4.1 Learning Process
                  2. 2.1.4.6.1.16.4.2 Updating Process
                  3. 2.1.4.6.1.16.4.3 Touching Process
              17. 12.2.1.4.6.1.17 VLAN Aware Mode
              18. 12.2.1.4.6.1.18 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 Ethernet MAC Sliver Overview
                1. 12.2.1.4.6.10.1.1 CRC Insertion
                2. 12.2.1.4.6.10.1.2 MTXER
                3. 12.2.1.4.6.10.1.3 Adaptive Performance Optimization (APO)
                4. 12.2.1.4.6.10.1.4 Inter-Packet-Gap Enforcement
                5. 12.2.1.4.6.10.1.5 Back Off
                6. 12.2.1.4.6.10.1.6 Programmable Transmit Inter-Packet Gap
                7. 12.2.1.4.6.10.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A05Ch)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.1.4.6.18.8  Rx Cut Thru with No Delay
              9. 12.2.1.4.6.18.9  Rx Cut Thru with Delay
              10. 12.2.1.4.6.18.10 Rx Cut Thru Store-and-Forward
              11. 12.2.1.4.6.18.11 Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.11.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.1.4.6.18.11.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.1.4.6.18.11.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.1.4.6.18.11.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.1.4.6.18.11.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.1.4.6.18.11.6  Collisions (Offset = 3A048h)
                7. 12.2.1.4.6.18.11.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.1.4.6.18.11.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.1.4.6.18.11.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.1.4.6.18.11.10 Late Collisions (Offset = 3A058h)
                11. 12.2.1.4.6.18.11.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.1.4.6.18.11.12 Tx Octets (Offset = 3A064h)
                13. 12.2.1.4.6.18.11.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.1.4.6.18.11.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8)
                15. 12.2.1.4.6.18.11.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.1.4.6.18.11.16 IET Transmit Merge Hold Count (Offset = 3A150h)
                17. 12.2.1.4.6.18.11.17 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                18. 12.2.1.4.6.18.11.18 Tx CRC Errors
                19. 12.2.1.4.6.18.11.19 Tx Cut Thru
                20. 12.2.1.4.6.18.11.20 Tx Cut Thru Store-and-Forward
              12. 12.2.1.4.6.18.12 Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.12.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.1.4.6.18.12.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.1.4.6.18.12.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.1.4.6.18.12.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.1.4.6.18.12.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.1.4.6.18.12.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.1.4.6.18.12.7 Net Octets (Offset = 3A080h)
              13. 12.2.1.4.6.18.13 4714
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 4742
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_3G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_3G Ingress)
            3. 12.2.1.4.8.3 Cut-Thru
              1. 12.2.1.4.8.3.1 Host Port Cut-Thru Operations
              2. 12.2.1.4.8.3.2 Cut-Thru Error Packets
            4. 12.2.1.4.8.4 Port Speed
            5. 12.2.1.4.8.5 CPPI Checksum Offload
              1. 12.2.1.4.8.5.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.5.1.1 IPV4 UDP
                2. 12.2.1.4.8.5.1.2 IPV4 TCP
                3. 12.2.1.4.8.5.1.3 IPV6 UDP
                4. 12.2.1.4.8.5.1.4 IPV6 TCP
            6. 12.2.1.4.8.6 CPPI Receive Checksum Offload
            7. 12.2.1.4.8.7 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 CPSW0 Registers
          1. 12.2.1.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  CPSW0_MDIO Registers
          3. 12.2.1.6.3  CPSW0_CPTS Registers
          4. 12.2.1.6.4  CPSW0_CONTROL Registers
          5. 12.2.1.6.5  CPSW0_CPINT Registers
          6. 12.2.1.6.6  CPSW0_RAM Registers
          7. 12.2.1.6.7  CPSW0_STAT0 Registers
          8. 12.2.1.6.8  CPSW0_STATN Registers
          9. 12.2.1.6.9  CPSW0_ALE Registers
          10. 12.2.1.6.10 CPSW0_PCSR Registers
          11. 12.2.1.6.11 CPSW0_ECC Registers
      2. 12.2.2 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.2.1 PCIe Subsystem Overview
          1. 12.2.2.1.1 PCIe Subsystem Features
          2. 12.2.2.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.2.2 PCIe Subsystem Environment
        3. 12.2.2.3 PCIe Subsystem Integration
        4. 12.2.2.4 PCIe Subsystem Functional Description
          1. 12.2.2.4.1  PCIe Subsystem Block Diagram
            1. 12.2.2.4.1.1 PCIe PHY Interface
              1. 12.2.2.4.1.1.1 PCIe Core Module
            2. 12.2.2.4.1.2 Custom Logic
          2. 12.2.2.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.2.4.2.1 PCIe Conventional Reset
            2. 12.2.2.4.2.2 PCIe Function Level Reset
            3. 12.2.2.4.2.3 PCIe Reset Isolation
              1. 12.2.2.4.2.3.1 Root Complex Reset with Device Not Reset
              2. 12.2.2.4.2.3.2 Device Reset with Root Complex Not Reset
              3. 12.2.2.4.2.3.3 End Point Device Reset with Root Complex Not Reset
              4. 12.2.2.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.2.4.2.4 PCIe Reset Limitations
            5. 12.2.2.4.2.5 PCIe Reset Requirements
          3. 12.2.2.4.3  PCIe Subsystem Power Management
            1. 12.2.2.4.3.1 CBA Power Management
          4. 12.2.2.4.4  PCIe Subsystem Interrupts
            1. 12.2.2.4.4.1 Interrupts Aggregation
            2. 12.2.2.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.2.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.2.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.2.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.2.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.2.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.2.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.2.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.2.4.4.3.5 PTM Valid Interrupt
            4. 12.2.2.4.4.4 Interrupt Generation in RC Mode
            5. 12.2.2.4.4.5 Interrupt Reception in RC Mode
              1. 12.2.2.4.4.5.1 PCIe Legacy Interrupt Reception in RC Mode
              2. 12.2.2.4.4.5.2 MSI/MSI-X Interrupt Reception in RC Mode
              3. 12.2.2.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.2.4.4.6 Common Interrupt Reception in RC and EP Modes
              1. 12.2.2.4.4.6.1 PCIe Local Interrupt
              2. 12.2.2.4.4.6.2 PHY Interrupt
              3. 12.2.2.4.4.6.3 Link down Interrupt
              4. 12.2.2.4.4.6.4 Transaction Error Interrupts
              5. 12.2.2.4.4.6.5 Power Management Event Interrupt
            7. 12.2.2.4.4.7 ECC Aggregator Interrupts
            8. 12.2.2.4.4.8 CPTS Interrupt
          5. 12.2.2.4.5  PCIe Subsystem DMA Support
            1. 12.2.2.4.5.1 PCIe DMA Support in RC Mode
            2. 12.2.2.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.2.4.6  PCIe Subsystem Transactions
            1. 12.2.2.4.6.1 PCIe Supported Transactions
            2. 12.2.2.4.6.2 PCIe Transaction Limitations
          7. 12.2.2.4.7  PCIe Subsystem Address Translation
            1. 12.2.2.4.7.1 PCIe Inbound Address Translation
              1. 12.2.2.4.7.1.1 Root Complex Inbound PCIe to AXI Address Translation
              2. 12.2.2.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.2.4.7.2 PCIe Outbound Address Translation
              1. 12.2.2.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.2.4.8  PCIe Subsystem Quality-of-Service (QoS)
          9. 12.2.2.4.9  PCIe Subsystem Precision Time Measurement (PTM)
          10. 12.2.2.4.10 PCIe Subsystem Loopback
            1. 12.2.2.4.10.1 PCIe Loopback
              1. 12.2.2.4.10.1.1 PCIe Loopback Initiator Mode
              2. 12.2.2.4.10.1.2 PCIe Loopback Target Mode
          11. 12.2.2.4.11 PCIe Subsystem Error Handling
          12. 12.2.2.4.12 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.2.4.12.1 ECC Aggregators
            2. 12.2.2.4.12.2 RAM ECC Inversion
        5. 12.2.2.5 PCIe Subsystem Registers
          1. 12.2.2.5.1 PCIE Registers
      3. 12.2.3 Serializer/Deserializer (SerDes)
        1. 12.2.3.1 SerDes Overview
          1. 12.2.3.1.1 SerDes Features
          2. 12.2.3.1.2 Not Supported Features
          3. 12.2.3.1.3 Industry Standards Compatibility
        2. 12.2.3.2 SerDes Environment
          1. 12.2.3.2.1 SerDes I/Os
        3. 12.2.3.3 SerDes Integration
          1. 12.2.3.3.1 WIZ Settings
            1. 12.2.3.3.1.1 Interface Selection
            2. 12.2.3.3.1.2 Internal Reference Clock Selection
        4. 12.2.3.4 SerDes Functional Description
          1. 12.2.3.4.1 SerDes Block Diagram
      4. 12.2.4 Universal Serial Bus Subsystem (USBSS)
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
          1. 12.2.4.2.1 USB I/Os
          2. 12.2.4.2.2 USB Subsystem Application
          3. 12.2.4.2.3 VBUS Sense
        3. 12.2.4.3 USB Integration
          1. 12.2.4.3.1 Resets, Interrupts, and Clocks
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Controller Reset
          2. 12.2.4.4.2 Overcurrent Detection
          3. 12.2.4.4.3 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB_RAMS_INJ_CFG Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1.       4890
        2. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        3. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        4. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MAIN Domain
        5. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS Regions
            1. 12.3.1.4.2.1 FSS Regions Boot Size Configuration
          3. 12.3.1.4.3 FSS Memory Regions
        6. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Power Up/Down Sequence
        7. 12.3.1.6 FSS Registers
          1. 12.3.1.6.1 FSS Registers
          2. 12.3.1.6.2 FSS_FSAS_0 Registers
          3. 12.3.1.6.3 FSS_OSPI_0 Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1.       4911
        2. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        3. 12.3.2.2 OSPI Environment
        4. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MAIN Domain
        5. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
              4. 12.3.2.4.2.1.4 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        6. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        7. 12.3.2.6 OSPI Registers
      3. 12.3.3 General-Purpose Memory Controller (GPMC)
        1. 12.3.3.1 GPMC Overview
          1. 12.3.3.1.1 GPMC Features
          2. 12.3.3.1.2 GPMC Not Supported Features
        2. 12.3.3.2 GPMC Environment
          1. 12.3.3.2.1 GPMC Modes
          2. 12.3.3.2.2 GPMC I/O Signals
        3. 12.3.3.3 GPMC Integration
          1. 12.3.3.3.1 GPMC Integration in MAIN Domain
        4. 12.3.3.4 GPMC Functional Description
          1. 12.3.3.4.1  GPMC Block Diagram
          2. 12.3.3.4.2  GPMC Clock Configuration
          3. 12.3.3.4.3  GPMC Power Management
          4. 12.3.3.4.4  GPMC Interrupt Requests
          5. 12.3.3.4.5  GPMC Interconnect Port Interface
          6. 12.3.3.4.6  GPMC Address and Data Bus
            1. 12.3.3.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.3.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.3.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.3.4.7.2 Access Protocol
              1. 12.3.3.4.7.2.1 Supported Devices
              2. 12.3.3.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.3.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.3.4.7.3 External Signals
              1. 12.3.3.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.3.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.3.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.3.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.3.4.7.3.1.5 Wait With NAND Device
                6. 12.3.3.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.3.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.3.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.3.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.3.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.3.4.7.3.2 DIR Pin
              3. 12.3.3.4.7.3.3 Reset
              4. 12.3.3.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.3.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.3.4.7.4 Error Handling
          8. 12.3.3.4.8  GPMC Timing Setting
            1. 12.3.3.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.3.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.3.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.3.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.3.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.3.4.8.6  GPMC_CLKOUT
            7. 12.3.3.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.3.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.3.4.8.8.1 Access Time on Read Access
              2. 12.3.3.4.8.8.2 Access Time on Write Access
            9. 12.3.3.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.3.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.3.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.3.4.8.10 Bus Keeping Support
          9. 12.3.3.4.9  GPMC NOR Access Description
            1. 12.3.3.4.9.1 Asynchronous Access Description
              1. 12.3.3.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.3.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.3.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.3.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.3.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.3.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.3.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.3.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.3.4.9.2 Synchronous Access Description
              1. 12.3.3.4.9.2.1 Synchronous Single Read
              2. 12.3.3.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.3.4.9.2.3 Synchronous Single Write
              4. 12.3.3.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.3.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.3.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.3.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.3.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.3.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.3.4.9.4 Page and Burst Support
            5. 12.3.3.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.3.4.10 GPMC pSRAM Access Specificities
          11. 12.3.3.4.11 GPMC NAND Access Description
            1. 12.3.3.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.3.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.3.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.3.4.11.1.3 Command Latch Cycle
              4. 12.3.3.4.11.1.4 Address Latch Cycle
              5. 12.3.3.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.3.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.3.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.3.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.3.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.3.4.11.2 NAND Device-Ready Pin
              1. 12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.3.4.11.3 ECC Calculator
              1. 12.3.3.4.11.3.1 Hamming Code
                1. 12.3.3.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.3.4.11.3.1.2 ECC Enabling
                3. 12.3.3.4.11.3.1.3 ECC Computation
                4. 12.3.3.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.3.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.3.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.3.4.11.3.2 BCH Code
                1. 12.3.3.4.11.3.2.1 Requirements
                2. 12.3.3.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.3.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.3.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.3.4.11.3.2.2.3 Wrapping Modes
                    1. 3.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 3.4.11.3.2.2.3.2  Mode 0x1
                    3. 3.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 3.4.11.3.2.2.3.4  Mode 0x2
                    5. 3.4.11.3.2.2.3.5  Mode 0x3
                    6. 3.4.11.3.2.2.3.6  Mode 0x7
                    7. 3.4.11.3.2.2.3.7  Mode 0x8
                    8. 3.4.11.3.2.2.3.8  Mode 0x4
                    9. 3.4.11.3.2.2.3.9  Mode 0x9
                    10. 3.4.11.3.2.2.3.10 Mode 0x5
                    11. 3.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 3.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.3.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.3.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.3.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.3.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.3.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.3.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.3.4.11.4.2 Prefetch Mode
              3. 12.3.3.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.3.4.11.4.4 Write-Posting Mode
              5. 12.3.3.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.3.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.3.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.3.4.12 GPMC Memory Regions
          13. 12.3.3.4.13 GPMC Use Cases and Tips
            1. 12.3.3.4.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.3.4.13.1.1 External Memory Attached to the GPMC Module
              2. 12.3.3.4.13.1.2 Typical GPMC Setup
                1. 12.3.3.4.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.3.4.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.3.4.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.3.4.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.3.4.13.2.1 Supported Memories or Devices
                1. 12.3.3.4.13.2.1.1 Memory Pin Multiplexing
                2. 12.3.3.4.13.2.1.2 NAND Interface Protocol
                3. 12.3.3.4.13.2.1.3 NOR Interface Protocol
                4. 12.3.3.4.13.2.1.4 Other Technologies
        5. 12.3.3.5 GPMC Basic Programming Model
          1. 12.3.3.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.3.5.2 GPMC Initialization
          3. 12.3.3.5.3 GPMC Configuration in NOR Mode
          4. 12.3.3.5.4 GPMC Configuration in NAND Mode
          5. 12.3.3.5.5 Set Memory Access
          6. 12.3.3.5.6 GPMC Timing Parameters
            1. 12.3.3.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.3.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.3.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.3.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.3.6 GPMC Registers
      4. 12.3.4 Error Location Module (ELM)
        1. 12.3.4.1 ELM Overview
          1. 12.3.4.1.1 ELM Features
          2. 12.3.4.1.2 ELM Not Supported Features
        2. 12.3.4.2 ELM Integration
          1. 12.3.4.2.1 ELM Integration in MAIN Domain
        3. 12.3.4.3 ELM Functional Description
          1. 12.3.4.3.1 ELM Software Reset
          2. 12.3.4.3.2 ELM Power Management
          3. 12.3.4.3.3 ELM Interrupt Requests
          4. 12.3.4.3.4 ELM Processing Initialization
          5. 12.3.4.3.5 ELM Processing Sequence
          6. 12.3.4.3.6 ELM Processing Completion
        4. 12.3.4.4 ELM Basic Programming Model
          1. 12.3.4.4.1 ELM Low-Level Programming Model
            1. 12.3.4.4.1.1 Processing Initialization
            2. 12.3.4.4.1.2 Read Results
            3. 12.3.4.4.1.3 5138
          2. 12.3.4.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.4.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.4.5 ELM Registers
      5. 12.3.5 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.5.1 MMCSD Overview
          1. 12.3.5.1.1 MMCSD Features
          2. 12.3.5.1.2 MMCSD Not Supported Features
        2. 12.3.5.2 MMCSD Environment
          1. 12.3.5.2.1 Protocol and Data Format
            1. 12.3.5.2.1.1 Protocol
            2. 12.3.5.2.1.2 Data Format
              1. 12.3.5.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.5.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.5.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.5.3 MMCSD Integration
          1. 12.3.5.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.5.4 MMCSD Functional Description
          1. 12.3.5.4.1 Block Diagram
          2. 12.3.5.4.2 Memory Regions
          3. 12.3.5.4.3 Interrupt Requests
          4. 12.3.5.4.4 ECC Support
            1. 12.3.5.4.4.1 ECC Aggregator
          5. 12.3.5.4.5 Advanced DMA
        5. 12.3.5.5 MMCSD Programming Guide
          1. 12.3.5.5.1 Sequences
            1. 12.3.5.5.1.1  SD Card Detection
            2. 12.3.5.5.1.2  SD Clock Control
              1. 12.3.5.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.5.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.5.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.5.5.1.3  SD Bus Power Control
            4. 12.3.5.5.1.4  Changing Bus Width
            5. 12.3.5.5.1.5  Timeout Setting on DAT Line
            6. 12.3.5.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.5.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.5.5.1.7  SD Transaction Generation
              1. 12.3.5.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.5.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.5.5.1.7.1.3 5178
              2. 12.3.5.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.2.1 Not using DMA
                2. 12.3.5.5.1.7.2.2 Using SDMA
                3. 12.3.5.5.1.7.2.3 Using ADMA
            8. 12.3.5.5.1.8  Abort Transaction
              1. 12.3.5.5.1.8.1 Asynchronous Abort
              2. 12.3.5.5.1.8.2 Synchronous Abort
            9. 12.3.5.5.1.9  Changing Bus Speed Mode
            10. 12.3.5.5.1.10 Error Recovery
              1. 12.3.5.5.1.10.1 Error Interrupt Recovery
              2. 12.3.5.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.5.5.1.11 Wakeup Control (Optional)
            12. 12.3.5.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.5.5.1.12.1 Suspend Sequence
              2. 12.3.5.5.1.12.2 Resume Sequence
              3. 12.3.5.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.5.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.5.5.2 Driver Flow Sequence
            1. 12.3.5.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.5.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.5.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.5.5.2.2 Boot Operation
              1. 12.3.5.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.5.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.5.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.5.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.5.5.2.3.1 Sampling Clock Tuning
              2. 12.3.5.5.2.3.2 Tuning Modes
              3. 12.3.5.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.5.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.5.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.5.5.2.4.2 Task Issuance Sequence
              3. 12.3.5.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.5.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.5.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.5.6 MMCSD Registers
          1. 12.3.5.6.1 MMCSD0 Subsystem Registers
          2. 12.3.5.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.5.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.5.6.4 MMCSD0 Host Controller Registers
          5. 12.3.5.6.5 MMCSD1 Subsystem Registers
          6. 12.3.5.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.5.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.5.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Modular Controller Area Network (MCAN)
        1. 12.4.1.1 MCAN Overview
          1. 12.4.1.1.1 MCAN Features
          2. 12.4.1.1.2 MCAN Not Supported Features
        2. 12.4.1.2 MCAN Environment
          1. 12.4.1.2.1 CAN Network Basics
        3. 12.4.1.3 MCAN Integration
          1. 12.4.1.3.1 MCAN Integration in MAIN Domain
        4. 12.4.1.4 MCAN Functional Description
          1. 12.4.1.4.1  Module Clocking Requirements
          2. 12.4.1.4.2  Interrupt and DMA Requests
            1. 12.4.1.4.2.1 Interrupt Requests
            2. 12.4.1.4.2.2 DMA Requests
          3. 12.4.1.4.3  Operating Modes
            1. 12.4.1.4.3.1 Software Initialization
            2. 12.4.1.4.3.2 Normal Operation
            3. 12.4.1.4.3.3 CAN FD Operation
            4. 12.4.1.4.3.4 Transmitter Delay Compensation
              1. 12.4.1.4.3.4.1 Description
              2. 12.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.1.4.3.5 Restricted Operation Mode
            6. 12.4.1.4.3.6 Bus Monitoring Mode
            7. 12.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.1.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.1.4.3.8 Power Down (Sleep Mode)
              1. 12.4.1.4.3.8.1 External Clock Stop Mode
              2. 12.4.1.4.3.8.2 Suspend Mode
              3. 12.4.1.4.3.8.3 Wakeup request
            9. 12.4.1.4.3.9 Test Modes
              1. 12.4.1.4.3.9.1 Internal Loopback Mode
          4. 12.4.1.4.4  Timestamp Generation
            1. 12.4.1.4.4.1 External Timestamp Counter
          5. 12.4.1.4.5  Timeout Counter
          6. 12.4.1.4.6  ECC Support
            1. 12.4.1.4.6.1 ECC Wrapper
            2. 12.4.1.4.6.2 ECC Aggregator
          7. 12.4.1.4.7  Rx Handling
            1. 12.4.1.4.7.1 Acceptance Filtering
              1. 12.4.1.4.7.1.1 Range Filter
              2. 12.4.1.4.7.1.2 Filter for specific IDs
              3. 12.4.1.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.1.4.7.1.4 Standard Message ID Filtering
              5. 12.4.1.4.7.1.5 Extended Message ID Filtering
            2. 12.4.1.4.7.2 Rx FIFOs
              1. 12.4.1.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.1.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.1.4.7.3 Dedicated Rx Buffers
              1. 12.4.1.4.7.3.1 Rx Buffer Handling
            4. 12.4.1.4.7.4 Debug on CAN Support
          8. 12.4.1.4.8  Tx Handling
            1. 12.4.1.4.8.1 Transmit Pause
            2. 12.4.1.4.8.2 Dedicated Tx Buffers
            3. 12.4.1.4.8.3 Tx FIFO
            4. 12.4.1.4.8.4 Tx Queue
            5. 12.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.1.4.8.7 Transmit Cancellation
            8. 12.4.1.4.8.8 Tx Event Handling
          9. 12.4.1.4.9  FIFO Acknowledge Handling
          10. 12.4.1.4.10 Message RAM
            1. 12.4.1.4.10.1 Message RAM Configuration
            2. 12.4.1.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.1.4.10.3 Tx Buffer Element
            4. 12.4.1.4.10.4 Tx Event FIFO Element
            5. 12.4.1.4.10.5 Standard Message ID Filter Element
            6. 12.4.1.4.10.6 Extended Message ID Filter Element
        5. 12.4.1.5 MCAN Registers
          1. 12.4.1.5.1 MCAN Subsystem Registers
          2. 12.4.1.5.2 MCAN Core Registers
          3. 12.4.1.5.3 MCAN ECC Aggregator Registers
      2. 12.4.2 Enhanced Capture (ECAP) Module
        1. 12.4.2.1 ECAP Overview
          1. 12.4.2.1.1 ECAP Features
        2. 12.4.2.2 ECAP Environment
          1. 12.4.2.2.1 ECAP I/O Interface
        3. 12.4.2.3 ECAP Integration
          1. 12.4.2.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.2.4 ECAP Functional Description
          1. 12.4.2.4.1 Capture and APWM Operating Modes
            1. 12.4.2.4.1.1 ECAP Capture Mode Description
              1. 12.4.2.4.1.1.1 ECAP Event Prescaler
              2. 12.4.2.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.2.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.2.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.2.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.2.4.1.1.6 ECAP Interrupt Control
              7. 12.4.2.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.2.4.1.2 ECAP APWM Mode Operation
          2. 12.4.2.4.2 Summary of ECAP Functional Registers
        5. 12.4.2.5 ECAP Use Cases
          1. 12.4.2.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.2.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.2.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.2.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.2.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.2.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.2.5.5 Application of the APWM Mode
            1. 12.4.2.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.2.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.2.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.2.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.2.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.2.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.2.6 ECAP Registers
      3. 12.4.3 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.3.1 EPWM Overview
          1. 12.4.3.1.1 EPWM Features
          2. 12.4.3.1.2 EPWM Not Supported Features
          3. 12.4.3.1.3 Multiple EPWM Module Details
        2. 12.4.3.2 EPWM Environment
        3. 12.4.3.3 EPWM Integration
          1. 12.4.3.3.1 EPWM Additional Integration Details
            1. 12.4.3.3.1.1 EPWM Tripzone Connectivity
            2. 12.4.3.3.1.2 Daisy-Chain Connectivity between EPWM Modules
            3. 12.4.3.3.1.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
            4. 12.4.3.3.1.4 EPWM Modules Time-Base Clock Gating
        4. 12.4.3.4 EPWM Functional Description
          1. 12.4.3.4.1  EPWM Submodule Features
            1. 12.4.3.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.3.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.3.4.2.1 Overview
            2. 12.4.3.4.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.3.4.2.3 Calculating PWM Period and Frequency
              1. 12.4.3.4.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.3.4.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.3.4.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.3.4.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.3.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.3.4.3.1 Overview
            2. 12.4.3.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.3.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.3.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.3.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.3.4.4.1 Overview
            2. 12.4.3.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.3.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.3.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.3.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.3.4.5.1 Overview
            2. 12.4.3.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.3.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.3.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.3.4.6.1 Overview
            2. 12.4.3.4.6.2 5369
            3. 12.4.3.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.3.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.3.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.3.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.3.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.3.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.3.4.7.1 Overview
            2. 12.4.3.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.3.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.3.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.3.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.3.4.8.1 Overview
            2. 12.4.3.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.3.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.3.4.8.4 Operation Overview of the EPWM SOCx Pulse Generator
          9. 12.4.3.4.9  EPWM Functional Register Groups
          10. 12.4.3.4.10 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.3.5 EPWM Registers
      4. 12.4.4 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.4.1 EQEP Overview
          1. 12.4.4.1.1 EQEP Features
          2. 12.4.4.1.2 EQEP Not Supported Features
        2. 12.4.4.2 EQEP Environment
          1. 12.4.4.2.1 EQEP I/O Interface
        3. 12.4.4.3 EQEP Integration
          1. 12.4.4.3.1 Device Specific EQEP Features
        4. 12.4.4.4 EQEP Functional Description
          1. 12.4.4.4.1 EQEP Inputs
          2. 12.4.4.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.4.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.4.4.2.1.1 Quadrature Count Mode
              2. 12.4.4.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.4.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.4.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.4.4.2.2 EQEP Input Polarity Selection
            3. 12.4.4.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.4.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.4.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.4.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.4.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.4.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.4.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.4.4.3.2 EQEP Position Counter Latch
              1. 12.4.4.4.3.2.1 Index Event Latch
              2. 12.4.4.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.4.4.3.3 EQEP Position Counter Initialization
            4. 12.4.4.4.3.4 EQEP Position-Compare Unit
          4. 12.4.4.4.4 EQEP Edge Capture Unit
          5. 12.4.4.4.5 EQEP Watchdog
          6. 12.4.4.4.6 Unit Timer Base
          7. 12.4.4.4.7 EQEP Interrupt Structure
          8. 12.4.4.4.8 Summary of EQEP Functional Registers
        5. 12.4.4.5 EQEP Registers
      5. 12.4.5 Fast Serial Interface (FSI)
        1. 12.4.5.1 FSI Overview
          1. 12.4.5.1.1 FSI Features
          2. 12.4.5.1.2 FSI Not Supported Featurs
        2. 12.4.5.2 FSI Environment
          1. 12.4.5.2.1 Signal Description
        3. 12.4.5.3 FSI Integration
          1. 12.4.5.3.1 FSI Interrupts
            1. 12.4.5.3.1.1 Transmitter Interrupts
            2. 12.4.5.3.1.2 Receiver Interrupts
            3. 12.4.5.3.1.3 Configuring Interrupts
            4. 12.4.5.3.1.4 Handling Interrupts
        4. 12.4.5.4 FSI Functional Description
          1. 12.4.5.4.1 FSI Functional Description
          2. 12.4.5.4.2 FSI Transmitter Module (FSI_TX)
            1. 12.4.5.4.2.1 Initialization
            2. 12.4.5.4.2.2 FSI_TX Clocking
            3. 12.4.5.4.2.3 Transmitting Frames
              1. 12.4.5.4.2.3.1 Software Triggered Frames
              2. 12.4.5.4.2.3.2 Ping Frame Generation
                1. 12.4.5.4.2.3.2.1 Automatic Ping Frames
                2. 12.4.5.4.2.3.2.2 Software Triggered Ping Frame
            4. 12.4.5.4.2.4 Transmit Buffer Management
            5. 12.4.5.4.2.5 CRC Submodule
            6. 12.4.5.4.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
            7. 12.4.5.4.2.7 Reset
          3. 12.4.5.4.3 FSI Receiver Module (FSI_RX)
            1. 12.4.5.4.3.1  Initialization
            2. 12.4.5.4.3.2  FSI_RX Clocking
            3. 12.4.5.4.3.3  Receiving Frames
            4. 12.4.5.4.3.4  Ping Frame Watchdog
            5. 12.4.5.4.3.5  Frame Watchdog
            6. 12.4.5.4.3.6  Delay Line Control
            7. 12.4.5.4.3.7  Buffer Management
            8. 12.4.5.4.3.8  CRC Submodule
            9. 12.4.5.4.3.9  Using the Zero Bits of the Receiver Tag Registers
            10. 12.4.5.4.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
            11. 12.4.5.4.3.11 FSI_RX Reset
          4. 12.4.5.4.4 Frame Format
            1. 12.4.5.4.4.1 FSI Frame Phases
            2. 12.4.5.4.4.2 Frame Types
              1. 12.4.5.4.4.2.1 Ping Frames
              2. 12.4.5.4.4.2.2 Error Frames
              3. 12.4.5.4.4.2.3 Data Frames
            3. 12.4.5.4.4.3 Multi-Lane Transmission
          5. 12.4.5.4.5 Flush Sequence
          6. 12.4.5.4.6 Internal Loopback
          7. 12.4.5.4.7 CRC Generation
          8. 12.4.5.4.8 ECC Module
          9. 12.4.5.4.9 FSI-SPI Compatibility Mode
            1. 12.4.5.4.9.1 Available SPI Modes
              1. 12.4.5.4.9.1.1 FSITX as SPI Controller, Transmit Only
                1. 12.4.5.4.9.1.1.1 Initialization
                2. 12.4.5.4.9.1.1.2 Operation
              2. 12.4.5.4.9.1.2 FSIRX as SPI Peripheral, Receive Only
                1. 12.4.5.4.9.1.2.1 Initialization
                2. 12.4.5.4.9.1.2.2 Operation
              3. 12.4.5.4.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
                1. 12.4.5.4.9.1.3.1 Initialization
                2. 12.4.5.4.9.1.3.2 Operation
        5. 12.4.5.5 FSI Programing Guide
          1. 12.4.5.5.1 Establishing the Communication Link
            1. 12.4.5.5.1.1 Establishing the Communication Link from the Main Device
            2. 12.4.5.5.1.2 Establishing the Communication Link from the Remote Device
          2. 12.4.5.5.2 Register Protection
          3. 12.4.5.5.3 Emulation Mode
        6. 12.4.5.6 FSI Registers
          1. 12.4.5.6.1 FSITX Registers
          2. 12.4.5.6.2 FSIRX Registers
    5. 12.5 Timer Modules
      1. 12.5.1 Global Timebase Counter (GTC)
        1. 12.5.1.1 Global Timebase Counter (GTC)
          1. 12.5.1.1.1 GTC Overview
            1. 12.5.1.1.1.1 GTC Features
            2. 12.5.1.1.1.2 GTC Not Supported Features
          2. 12.5.1.1.2 GTC Integration
        2. 12.5.1.2 GTC Functional Description
          1. 12.5.1.2.1 GTC Block Diagram
          2. 12.5.1.2.2 GTC Counter
          3. 12.5.1.2.3 GTC Register Partitioning
        3. 12.5.1.3 GTC Registers
          1. 12.5.1.3.1  GTC_CFG0_GTC_PID Registers
          2. 12.5.1.3.2  GTC_CFG0_GTC_GTC_PID Registers
          3. 12.5.1.3.3  GTC_CFG0_GTC_PUSHEVT Registers
          4. 12.5.1.3.4  GTC_CFG1_GTC_CNTCR Registers
          5. 12.5.1.3.5  GTC_CFG1_GTC_CNTSR Registers
          6. 12.5.1.3.6  GTC_CFG1_GTC_CNTCV_LO Registers
          7. 12.5.1.3.7  GTC_CFG1_GTC_CNTCV_HI Registers
          8. 12.5.1.3.8  GTC_CFG1_GTC_CNTFID0 Registers
          9. 12.5.1.3.9  GTC_CFG1_GTC_CNTFID1 Registers
          10. 12.5.1.3.10 GTC_CFG2_GTC_CNTCVS_LO Registers
          11. 12.5.1.3.11 GTC_CFG2_GTC_CNTCVS_HI Registers
          12. 12.5.1.3.12 GTC_CFG3_GTC_CNTTIDR Registers
          13. 12.5.1.3.13 Access Table
      2. 12.5.2 RTI-Windowed Watchdog Timer (WWDT)
        1. 12.5.2.1 RTI Overview
          1. 12.5.2.1.1 RTI Features
          2. 12.5.2.1.2 RTI Not Supported Features
        2. 12.5.2.2 RTI Integration
          1. 12.5.2.2.1 RTI Integration in MCU Domain
          2. 12.5.2.2.2 RTI Integration in MAIN Domain
        3. 12.5.2.3 RTI Functional Description
          1. 12.5.2.3.1 RTI Digital Windowed Watchdog
            1. 12.5.2.3.1.1 RTI Debug Mode Behavior
            2. 12.5.2.3.1.2 RTI Low Power Mode Operation
          2. 12.5.2.3.2 RTI Digital Watchdog
          3. 12.5.2.3.3 RTI Counter Operation
        4. 12.5.2.4 RTI Registers
      3. 12.5.3 Timers
        1. 12.5.3.1 Timers Overview
          1. 12.5.3.1.1 Timers Features
          2. 12.5.3.1.2 Timers Not Supported Features
        2. 12.5.3.2 Timers Environment
          1. 12.5.3.2.1 Timer External System Interface
        3. 12.5.3.3 Timers Integration
          1. 12.5.3.3.1 Timers Integration in MCU Domain
          2. 12.5.3.3.2 Timers Integration in MAIN Domain
        4. 12.5.3.4 Timers Functional Description
          1. 12.5.3.4.1  Timer Block Diagram
          2. 12.5.3.4.2  Timer Power Management
            1. 12.5.3.4.2.1 Wake-Up Capability
          3. 12.5.3.4.3  Timer Software Reset
          4. 12.5.3.4.4  Timer Interrupts
          5. 12.5.3.4.5  Timer Mode Functionality
            1. 12.5.3.4.5.1 1-ms Tick Generation
          6. 12.5.3.4.6  Timer Capture Mode Functionality
          7. 12.5.3.4.7  Timer Compare Mode Functionality
          8. 12.5.3.4.8  Timer Prescaler Functionality
          9. 12.5.3.4.9  Timer Pulse-Width Modulation
          10. 12.5.3.4.10 Timer Counting Rate
          11. 12.5.3.4.11 Timer Under Emulation
          12. 12.5.3.4.12 Accessing Timer Registers
            1. 12.5.3.4.12.1 Writing to Timer Registers
              1. 12.5.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.5.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.5.3.4.12.2 Reading From Timer Counter Registers
              1. 12.5.3.4.12.2.1 Read Posted
              2. 12.5.3.4.12.2.2 Read Non-Posted
          13. 12.5.3.4.13 Timer Posted Mode Selection
        5. 12.5.3.5 Timers Low-Level Programming Models
          1. 12.5.3.5.1 Timer Global Initialization
            1. 12.5.3.5.1.1 Main Sequence – Timer Module Global Initialization
          2. 12.5.3.5.2 Timer Operational Mode Configuration
            1. 12.5.3.5.2.1 Timer Mode
              1. 12.5.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.5.3.5.2.2 Timer Compare Mode
              1. 12.5.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.5.3.5.2.3 Timer Capture Mode
              1. 12.5.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.5.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.5.3.5.2.3.3 Subsequence – Detect Event
            4. 12.5.3.5.2.4 Timer PWM Mode
              1. 12.5.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.5.3.6 Timers Registers
    6. 12.6 Internal Diagnostics Modules
      1. 12.6.1 Dual Clock Comparator (DCC)
        1. 12.6.1.1 DCC Overview
          1. 12.6.1.1.1 DCC Features
          2. 12.6.1.1.2 DCC Not Supported Features
        2. 12.6.1.2 DCC Integration
          1. 12.6.1.2.1 DCC Integration in MCU Domain
            1. 12.6.1.2.1.1 MCU DCC Input Source Clock Mapping
          2. 12.6.1.2.2 DCC Integration in MAIN Domain
            1. 12.6.1.2.2.1 DCC Input Source Clock Mapping
        3. 12.6.1.3 DCC Functional Description
          1. 12.6.1.3.1 DCC Counter Operation
          2. 12.6.1.3.2 DCC Low Power Mode Operation
          3. 12.6.1.3.3 DCC Suspend Mode Behavior
          4. 12.6.1.3.4 DCC Single-Shot Mode
          5. 12.6.1.3.5 DCC Continuous mode
            1. 12.6.1.3.5.1 DCC Continue on Error
            2. 12.6.1.3.5.2 DCC Error Count
          6. 12.6.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.6.1.3.7 DCC Error Trajectory record
            1. 12.6.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.6.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.6.1.3.7.3 DCC FIFO Details
            4. 12.6.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.6.1.3.8 DCC Count read registers
        4. 12.6.1.4 DCC Registers
      2. 12.6.2 Error Signaling Module (ESM)
        1. 12.6.2.1 ESM Overview
          1. 12.6.2.1.1 ESM Features
        2. 12.6.2.2 ESM Environment
        3. 12.6.2.3 ESM Integration
          1. 12.6.2.3.1 ESM Integration in MCU Domain
          2. 12.6.2.3.2 ESM Integration in MAIN Domain
        4. 12.6.2.4 ESM Functional Description
          1. 12.6.2.4.1 ESM Interrupt Requests
            1. 12.6.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.6.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.6.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.6.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.6.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.6.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.6.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.6.2.4.2 ESM Error Event Inputs
          3. 12.6.2.4.3 ESM Error Pin Output
          4. 12.6.2.4.4 PWM Mode
          5. 12.6.2.4.5 ESM Minimum Time Interval
          6. 12.6.2.4.6 ESM Protection for Registers
          7. 12.6.2.4.7 ESM Clock Stop
        5. 12.6.2.5 ESM Registers
      3. 12.6.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.6.3.1 MCRC Overview
          1. 12.6.3.1.1 MCRC Features
          2. 12.6.3.1.2 MCRC Not Supported Features
        2. 12.6.3.2 MCRC Integration
        3. 12.6.3.3 MCRC Functional Description
          1. 12.6.3.3.1  MCRC Block Diagram
          2. 12.6.3.3.2  MCRC General Operation
          3. 12.6.3.3.3  MCRC Modes of Operation
            1. 12.6.3.3.3.1 AUTO Mode
            2. 12.6.3.3.3.2 Semi-CPU Mode
            3. 12.6.3.3.3.3 Full-CPU Mode
          4. 12.6.3.3.4  PSA Signature Register
          5. 12.6.3.3.5  PSA Sector Signature Register
          6. 12.6.3.3.6  CRC Value Register
          7. 12.6.3.3.7  Raw Data Register
          8. 12.6.3.3.8  Example DMA Controller Setup
            1. 12.6.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.6.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.6.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.6.3.3.9  Pattern Count Register
          10. 12.6.3.3.10 Sector Count Register/Current Sector Register
          11. 12.6.3.3.11 Interrupts
            1. 12.6.3.3.11.1 Overrun Interrupt
            2. 12.6.3.3.11.2 Timeout Interrupt
            3. 12.6.3.3.11.3 Underrun Interrupt
            4. 12.6.3.3.11.4 Compression Complete Interrupt
            5. 12.6.3.3.11.5 Interrupt Offset Register
            6. 12.6.3.3.11.6 Error Handling
          12. 12.6.3.3.12 Power Down Mode
          13. 12.6.3.3.13 Emulation
        4. 12.6.3.4 MCRC Programming Examples
          1. 12.6.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.6.3.4.1.1 DMA Setup
            2. 12.6.3.4.1.2 Timer Setup
            3. 12.6.3.4.1.3 CRC Setup
          2. 12.6.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.6.3.4.2.1 DMA Setup
            2. 12.6.3.4.2.2 CRC Setup
          3. 12.6.3.4.3 Example: Semi-CPU Mode
            1. 12.6.3.4.3.1 DMA Setup
            2. 12.6.3.4.3.2 Timer Setup
            3. 12.6.3.4.3.3 CRC Setup
          4. 12.6.3.4.4 Example: Full-CPU Mode
            1. 12.6.3.4.4.1 CRC Setup
        5. 12.6.3.5 MCRC Registers
      4. 12.6.4 ECC Aggregator
        1. 12.6.4.1 ECC Aggregator Overview
          1. 12.6.4.1.1 ECC Aggregator Features
        2. 12.6.4.2 ECC Aggregator Integration
        3. 12.6.4.3 ECC Aggregator Functional Description
          1. 12.6.4.3.1 ECC Aggregator Block Diagram
          2. 12.6.4.3.2 ECC Aggregator Register Groups
          3. 12.6.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.6.4.3.4 Serial Write Operation
          5. 12.6.4.3.5 Interrupts
          6. 12.6.4.3.6 Inject Only Mode
        4. 12.6.4.4 ECC Aggregators Interconnect
        5. 12.6.4.5 ECC Aggregator Registers
  15. 13On-Chip Debug
    1. 13.1 On-Chip Debug Overview
    2. 13.2 On-Chip Debug Features
    3.     5688
    4. 13.3 On-Chip Debug Functional Description
      1. 13.3.1  On-Chip Debug Block Diagram
      2. 13.3.2  Device Interfaces
        1. 13.3.2.1 JTAG Interface
        2. 13.3.2.2 Trigger and Debug Boot Mode Interface
        3. 13.3.2.3 Trace Port Interface
      3. 13.3.3  Debug and Boundary Scan Access and Control
      4. 13.3.4  Debug Boot Modes and Boundary Scan Compliance
      5. 13.3.5  Power, Reset, Clock Management
      6. 13.3.6  Debug Cross Triggering
      7. 13.3.7  R5FSS0/R5FSS1 Debug
      8. 13.3.8  DMSC Debug
      9. 13.3.9  A53SS0 Debug
      10. 13.3.10 PRU_ICSSG0/PRU_ICSSG1 Debug
      11. 13.3.11 SoC Debug and Trace
        1. 13.3.11.1 Software messaging trace
        2. 13.3.11.2 Debug-Aware Peripherals
        3. 13.3.11.3 Traffic Monitoring With Bus Probes
        4. 13.3.11.4 Global timestamping for trace
      12. 13.3.12 Trace Traffic
        1. 13.3.12.1 Trace Sources
        2. 13.3.12.2 Trace Infrasctructure
        3. 13.3.12.3 Trace Sinks
      13. 13.3.13 Application Support
  16. 14Revision History

6.4.14.7 PRU_ICSS_INTC_INTC Registers

Table 6-783 lists the memory-mapped registers for the PRU_ICSS_INTC_INTC registers. All register offset addresses not listed in Table 6-783 should be considered as reserved locations and the register contents should not be modified.

Table 6-782 PRU_ICSS_INTC_INTC Instances
InstanceBase Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0000h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0000h
Table 6-783 PRU_ICSS_INTC_INTC Registers
OffsetAcronymRegister NamePRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV Physical AddressPRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV Physical Address
0hICSS_INTC_REVISION_REGRevision Register3002 0000h300A 0000h
4hICSS_INTC_CONTROL_REGControl Register3002 0004h300A 0004h
10hICSS_INTC_GLOBAL_ENABLE_HINT_REGGlobal Host Int Enable Register3002 0010h300A 0010h
1ChICSS_INTC_GLB_NEST_LEVEL_REGGlobal Nesting Level Register3002 001Ch300A 001Ch
20hICSS_INTC_STATUS_SET_INDEX_REGStatus Set Index Register3002 0020h300A 0020h
24hICSS_INTC_STATUS_CLR_INDEX_REGStatus Clear Index Register3002 0024h300A 0024h
28hICSS_INTC_ENABLE_SET_INDEX_REGEnable Set Index Register3002 0028h300A 0028h
2ChICSS_INTC_ENABLE_CLR_INDEX_REGEnable Clear Index Register3002 002Ch300A 002Ch
34hICSS_INTC_HINT_ENABLE_SET_INDEX_REGHost Int Enable Set Index Register3002 0034h300A 0034h
38hICSS_INTC_HINT_ENABLE_CLR_INDEX_REGHost Int Enable Clear Index Register3002 0038h300A 0038h
80hICSS_INTC_GLB_PRI_INTR_REGGlobal Prioritized Interrupt Register3002 0080h300A 0080h
200hICSS_INTC_RAW_STATUS_REG0Raw Status Register 03002 0200h300A 0200h
204hICSS_INTC_RAW_STATUS_REG1Raw Status Register 13002 0204h300A 0204h
208hICSS_INTC_RAW_STATUS_REG2Raw Status Register 23002 0208h300A 0208h
20ChICSS_INTC_RAW_STATUS_REG3Raw Status Register 33002 020Ch300A 020Ch
210hICSS_INTC_RAW_STATUS_REG4Raw Status Register 43002 0210h300A 0210h
280hICSS_INTC_ENA_STATUS_REG0Enabled Status Register 03002 0280h300A 0280h
284hICSS_INTC_ENA_STATUS_REG1Enabled Status Register 13002 0284h300A 0284h
288hICSS_INTC_ENA_STATUS_REG2Enabled Status Register 23002 0288h300A 0288h
28ChICSS_INTC_ENA_STATUS_REG3Enabled Status Register 33002 028Ch300A 028Ch
290hICSS_INTC_ENA_STATUS_REG4Enabled Status Register 43002 0290h300A 0290h
300hICSS_INTC_ENABLE_REG0Enable Register 03002 0300h300A 0300h
304hICSS_INTC_ENABLE_REG1Enable Register 13002 0304h300A 0304h
308hICSS_INTC_ENABLE_REG2Enable Register 23002 0308h300A 0308h
30ChICSS_INTC_ENABLE_REG3Enable Register 33002 030Ch300A 030Ch
310hICSS_INTC_ENABLE_REG4Enable Register 43002 0310h300A 0310h
380hICSS_INTC_ENABLE_CLR_REG0Enable Clear Register 03002 0380h300A 0380h
384hICSS_INTC_ENABLE_CLR_REG1Enable Clear Register 13002 0384h300A 0384h
388hICSS_INTC_ENABLE_CLR_REG2Enable Clear Register 23002 0388h300A 0388h
38ChICSS_INTC_ENABLE_CLR_REG3Enable Clear Register 33002 038Ch300A 038Ch
390hICSS_INTC_ENABLE_CLR_REG4Enable Clear Register 43002 0390h300A 0390h
400hICSS_INTC_CH_MAP_REG0Interrupt Channel Map Register for 0 to 0+33002 0400h300A 0400h
404hICSS_INTC_CH_MAP_REG1Interrupt Channel Map Register for 4 to 4+33002 0404h300A 0404h
408hICSS_INTC_CH_MAP_REG2Interrupt Channel Map Register for 8 to 8+33002 0408h300A 0408h
40ChICSS_INTC_CH_MAP_REG3Interrupt Channel Map Register for 12 to 12+33002 040Ch300A 040Ch
410hICSS_INTC_CH_MAP_REG4Interrupt Channel Map Register for 16 to 16+33002 0410h300A 0410h
414hICSS_INTC_CH_MAP_REG5Interrupt Channel Map Register for 20 to 20+33002 0414h300A 0414h
418hICSS_INTC_CH_MAP_REG6Interrupt Channel Map Register for 24 to 24+33002 0418h300A 0418h
41ChICSS_INTC_CH_MAP_REG7Interrupt Channel Map Register for 28 to 28+33002 041Ch300A 041Ch
420hICSS_INTC_CH_MAP_REG8Interrupt Channel Map Register for 32 to 32+33002 0420h300A 0420h
424hICSS_INTC_CH_MAP_REG9Interrupt Channel Map Register for 36 to 36+33002 0424h300A 0424h
428hICSS_INTC_CH_MAP_REG10Interrupt Channel Map Register for 40 to 40+33002 0428h300A 0428h
42ChICSS_INTC_CH_MAP_REG11Interrupt Channel Map Register for 44 to 44+33002 042Ch300A 042Ch
430hICSS_INTC_CH_MAP_REG12Interrupt Channel Map Register for 48 to 48+33002 0430h300A 0430h
434hICSS_INTC_CH_MAP_REG13Interrupt Channel Map Register for 52 to 52+33002 0434h300A 0434h
438hICSS_INTC_CH_MAP_REG14Interrupt Channel Map Register for 56 to 56+33002 0438h300A 0438h
43ChICSS_INTC_CH_MAP_REG15Interrupt Channel Map Register for 60 to 60+33002 043Ch300A 043Ch
440hICSS_INTC_CH_MAP_REG16Interrupt Channel Map Register for 64 to 64+33002 0440h300A 0440h
444hICSS_INTC_CH_MAP_REG17Interrupt Channel Map Register for 68 to 68+33002 0444h300A 0444h
448hICSS_INTC_CH_MAP_REG18Interrupt Channel Map Register for 72 to 72+33002 0448h300A 0448h
44ChICSS_INTC_CH_MAP_REG19Interrupt Channel Map Register for 76 to 76+33002 044Ch300A 044Ch
450hICSS_INTC_CH_MAP_REG20Interrupt Channel Map Register for 80 to 80+33002 0450h300A 0450h
454hICSS_INTC_CH_MAP_REG21Interrupt Channel Map Register for 84 to 84+33002 0454h300A 0454h
458hICSS_INTC_CH_MAP_REG22Interrupt Channel Map Register for 88 to 88+33002 0458h300A 0458h
45ChICSS_INTC_CH_MAP_REG23Interrupt Channel Map Register for 92 to 92+33002 045Ch300A 045Ch
460hICSS_INTC_CH_MAP_REG24Interrupt Channel Map Register for 96 to 96+33002 0460h300A 0460h
464hICSS_INTC_CH_MAP_REG25Interrupt Channel Map Register for 100 to 100+33002 0464h300A 0464h
468hICSS_INTC_CH_MAP_REG26Interrupt Channel Map Register for 104 to 104+33002 0468h300A 0468h
46ChICSS_INTC_CH_MAP_REG27Interrupt Channel Map Register for 108 to 108+33002 046Ch300A 046Ch
470hICSS_INTC_CH_MAP_REG28Interrupt Channel Map Register for 112 to 112+33002 0470h300A 0470h
474hICSS_INTC_CH_MAP_REG29Interrupt Channel Map Register for 116 to 116+33002 0474h300A 0474h
478hICSS_INTC_CH_MAP_REG30Interrupt Channel Map Register for 120 to 120+33002 0478h300A 0478h
47ChICSS_INTC_CH_MAP_REG31Interrupt Channel Map Register for 124 to 124+33002 047Ch300A 047Ch
480hICSS_INTC_CH_MAP_REG32Interrupt Channel Map Register for 128 to 128+33002 0480h300A 0480h
484hICSS_INTC_CH_MAP_REG33Interrupt Channel Map Register for 132 to 132+33002 0484h300A 0484h
488hICSS_INTC_CH_MAP_REG34Interrupt Channel Map Register for 136 to 136+33002 0488h300A 0488h
48ChICSS_INTC_CH_MAP_REG35Interrupt Channel Map Register for 140 to 140+33002 048Ch300A 048Ch
490hICSS_INTC_CH_MAP_REG36Interrupt Channel Map Register for 144 to 144+33002 0490h300A 0490h
494hICSS_INTC_CH_MAP_REG37Interrupt Channel Map Register for 148 to 148+33002 0494h300A 0494h
498hICSS_INTC_CH_MAP_REG38Interrupt Channel Map Register for 152 to 152+33002 0498h300A 0498h
49ChICSS_INTC_CH_MAP_REG39Interrupt Channel Map Register for 156 to 156+33002 049Ch300A 049Ch
800hICSS_INTC_HINT_MAP_REG0Host Interrupt Map Register for 0 to 0+33002 0800h300A 0800h
804hICSS_INTC_HINT_MAP_REG1Host Interrupt Map Register for 4 to 4+33002 0804h300A 0804h
808hICSS_INTC_HINT_MAP_REG2Host Interrupt Map Register for 8 to 8+33002 0808h300A 0808h
80ChICSS_INTC_HINT_MAP_REG3Host Interrupt Map Register for 12 to 12+33002 080Ch300A 080Ch
810hICSS_INTC_HINT_MAP_REG4Host Interrupt Map Register for 16 to 16+43002 0810h300A 0810h
900hICSS_INTC_PRI_HINT_REG0Host Int 0 Prioritized Interrupt Register3002 0900h300A 0900h
904hICSS_INTC_PRI_HINT_REG1Host Int 1 Prioritized Interrupt Register3002 0904h300A 0904h
908hICSS_INTC_PRI_HINT_REG2Host Int 2 Prioritized Interrupt Register3002 0908h300A 0908h
90ChICSS_INTC_PRI_HINT_REG3Host Int 3 Prioritized Interrupt Register3002 090Ch300A 090Ch
910hICSS_INTC_PRI_HINT_REG4Host Int 4 Prioritized Interrupt Register3002 0910h300A 0910h
914hICSS_INTC_PRI_HINT_REG5Host Int 5 Prioritized Interrupt Register3002 0914h300A 0914h
918hICSS_INTC_PRI_HINT_REG6Host Int 6 Prioritized Interrupt Register3002 0918h300A 0918h
91ChICSS_INTC_PRI_HINT_REG7Host Int 7 Prioritized Interrupt Register3002 091Ch300A 091Ch
920hICSS_INTC_PRI_HINT_REG8Host Int 8 Prioritized Interrupt Register3002 0920h300A 0920h
924hICSS_INTC_PRI_HINT_REG9Host Int 9 Prioritized Interrupt Register3002 0924h300A 0924h
928hICSS_INTC_PRI_HINT_REG10Host Int 10 Prioritized Interrupt Register3002 0928h300A 0928h
92ChICSS_INTC_PRI_HINT_REG11Host Int 11 Prioritized Interrupt Register3002 092Ch300A 092Ch
930hICSS_INTC_PRI_HINT_REG12Host Int 12 Prioritized Interrupt Register3002 0930h300A 0930h
934hICSS_INTC_PRI_HINT_REG13Host Int 13 Prioritized Interrupt Register3002 0934h300A 0934h
938hICSS_INTC_PRI_HINT_REG14Host Int 14 Prioritized Interrupt Register3002 0938h300A 0938h
93ChICSS_INTC_PRI_HINT_REG15Host Int 15 Prioritized Interrupt Register3002 093Ch300A 093Ch
940hICSS_INTC_PRI_HINT_REG16Host Int 16 Prioritized Interrupt Register3002 0940h300A 0940h
944hICSS_INTC_PRI_HINT_REG17Host Int 17 Prioritized Interrupt Register3002 0944h300A 0944h
948hICSS_INTC_PRI_HINT_REG18Host Int 18 Prioritized Interrupt Register3002 0948h300A 0948h
94ChICSS_INTC_PRI_HINT_REG19Host Int 19 Prioritized Interrupt Register3002 094Ch300A 094Ch
D00hICSS_INTC_POLARITY_REG0Polarity Register 03002 0D00h300A 0D00h
D04hICSS_INTC_POLARITY_REG1Polarity Register 13002 0D04h300A 0D04h
D08hICSS_INTC_POLARITY_REG2Polarity Register 23002 0D08h300A 0D08h
D0ChICSS_INTC_POLARITY_REG3Polarity Register 33002 0D0Ch300A 0D0Ch
D10hICSS_INTC_POLARITY_REG4Polarity Register 43002 0D10h300A 0D10h
D80hICSS_INTC_TYPE_REG0Type Register 03002 0D80h300A 0D80h
D84hICSS_INTC_TYPE_REG1Type Register 13002 0D84h300A 0D84h
D88hICSS_INTC_TYPE_REG2Type Register 23002 0D88h300A 0D88h
D8ChICSS_INTC_TYPE_REG3Type Register 33002 0D8Ch300A 0D8Ch
D90hICSS_INTC_TYPE_REG4Type Register 43002 0D90h300A 0D90h
1100hICSS_INTC_NEST_LEVEL_REG0Host Int 0 Nesting Level Register3002 1100h300A 1100h
1104hICSS_INTC_NEST_LEVEL_REG1Host Int 1 Nesting Level Register3002 1104h300A 1104h
1108hICSS_INTC_NEST_LEVEL_REG2Host Int 2 Nesting Level Register3002 1108h300A 1108h
110ChICSS_INTC_NEST_LEVEL_REG3Host Int 3 Nesting Level Register3002 110Ch300A 110Ch
1110hICSS_INTC_NEST_LEVEL_REG4Host Int 4 Nesting Level Register3002 1110h300A 1110h
1114hICSS_INTC_NEST_LEVEL_REG5Host Int 5 Nesting Level Register3002 1114h300A 1114h
1118hICSS_INTC_NEST_LEVEL_REG6Host Int 6 Nesting Level Register3002 1118h300A 1118h
111ChICSS_INTC_NEST_LEVEL_REG7Host Int 7 Nesting Level Register3002 111Ch300A 111Ch
1120hICSS_INTC_NEST_LEVEL_REG8Host Int 8 Nesting Level Register3002 1120h300A 1120h
1124hICSS_INTC_NEST_LEVEL_REG9Host Int 9 Nesting Level Register3002 1124h300A 1124h
1128hICSS_INTC_NEST_LEVEL_REG10Host Int 10 Nesting Level Register3002 1128h300A 1128h
112ChICSS_INTC_NEST_LEVEL_REG11Host Int 11 Nesting Level Register3002 112Ch300A 112Ch
1130hICSS_INTC_NEST_LEVEL_REG12Host Int 12 Nesting Level Register3002 1130h300A 1130h
1134hICSS_INTC_NEST_LEVEL_REG13Host Int 13 Nesting Level Register3002 1134h300A 1134h
1138hICSS_INTC_NEST_LEVEL_REG14Host Int 14 Nesting Level Register3002 1138h300A 1138h
113ChICSS_INTC_NEST_LEVEL_REG15Host Int 15 Nesting Level Register3002 113Ch300A 113Ch
1140hICSS_INTC_NEST_LEVEL_REG16Host Int 16 Nesting Level Register3002 1140h300A 1140h
1144hICSS_INTC_NEST_LEVEL_REG17Host Int 17 Nesting Level Register3002 1144h300A 1144h
1148hICSS_INTC_NEST_LEVEL_REG18Host Int 18 Nesting Level Register3002 1148h300A 1148h
114ChICSS_INTC_NEST_LEVEL_REG19Host Int 19 Nesting Level Register3002 114Ch300A 114Ch
1500hICSS_INTC_ENABLE_HINT_REG0Host Int Enable Register 03002 1500h300A 1500h

4.14.7.1 ICSS_INTC_REVISION_REG Register (Offset = 0h) [reset = X]

ICSS_INTC_REVISION_REG is shown in Figure 6-402 and described in Table 6-785.

Return to Summary Table.

Revision Register

Table 6-784 ICSS_INTC_REVISION_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0000h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0000h
Figure 6-402 ICSS_INTC_REVISION_REG Register
3130292827262524
REV_SCHEMERESERVEDREV_MODULE
R-1hR-XR-E82h
2322212019181716
REV_MODULE
R-E82h
15141312111098
REV_RTLREV_MAJOR
R-15hR-1h
76543210
REV_CUSTOMREV_MINOR
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-785 ICSS_INTC_REVISION_REG Register Field Descriptions
BitFieldTypeResetDescription
31-30REV_SCHEMER1hScheme
29-28RESERVEDRX
27-16REV_MODULERE82hModule ID
15-11REV_RTLR15hRTL revisions
10-8REV_MAJORR1hMajor revision
7-6REV_CUSTOMR0hCustom revision
5-0REV_MINORR0hMinor revision

4.14.7.2 ICSS_INTC_CONTROL_REG Register (Offset = 4h) [reset = X]

ICSS_INTC_CONTROL_REG is shown in Figure 6-403 and described in Table 6-787.

Return to Summary Table.

Control Register

Table 6-786 ICSS_INTC_CONTROL_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0004h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0004h
Figure 6-403 ICSS_INTC_CONTROL_REG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPRIORITY_HOLD_MODENEST_MODEWAKEUP_MODERESERVED
R/W-XR/W-0hR/W-0hR/W-0hR/W-X
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-787 ICSS_INTC_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/WX
4PRIORITY_HOLD_MODER/W0hPriority Holding Mode
3-2NEST_MODER/W0hNesting Mode
1WAKEUP_MODER/W0hWakeup mode enable
0RESERVEDR/WX

4.14.7.3 ICSS_INTC_GLOBAL_ENABLE_HINT_REG Register (Offset = 10h) [reset = X]

ICSS_INTC_GLOBAL_ENABLE_HINT_REG is shown in Figure 6-404 and described in Table 6-789.

Return to Summary Table.

Global Host Int Enable Register

Table 6-788 ICSS_INTC_GLOBAL_ENABLE_HINT_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0010h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0010h
Figure 6-404 ICSS_INTC_GLOBAL_ENABLE_HINT_REG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDENABLE_HINT_ANY
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-789 ICSS_INTC_GLOBAL_ENABLE_HINT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/WX
0ENABLE_HINT_ANYR/W0hGlobal Enable for all Host Interrupts

4.14.7.4 ICSS_INTC_GLB_NEST_LEVEL_REG Register (Offset = 1Ch) [reset = X]

ICSS_INTC_GLB_NEST_LEVEL_REG is shown in Figure 6-405 and described in Table 6-791.

Return to Summary Table.

Global Nesting Level Register

Table 6-790 ICSS_INTC_GLB_NEST_LEVEL_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 001Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 001Ch
Figure 6-405 ICSS_INTC_GLB_NEST_LEVEL_REG Register
3130292827262524
GLB_NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDGLB_NEST_LEVEL
R/W-XR/W-100h
76543210
GLB_NEST_LEVEL
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-791 ICSS_INTC_GLB_NEST_LEVEL_REG Register Field Descriptions
BitFieldTypeResetDescription
31GLB_NEST_AUTO_OVRWXGlobal Nesting Level Override Automatic
30-9RESERVEDR/WX
8-0GLB_NEST_LEVELR/W100hGlobal Nesting Level

4.14.7.5 ICSS_INTC_STATUS_SET_INDEX_REG Register (Offset = 20h) [reset = X]

ICSS_INTC_STATUS_SET_INDEX_REG is shown in Figure 6-406 and described in Table 6-793.

Return to Summary Table.

Status Set Index Register

Table 6-792 ICSS_INTC_STATUS_SET_INDEX_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0020h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0020h
Figure 6-406 ICSS_INTC_STATUS_SET_INDEX_REG Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDSTATUS_SET_INDEX
W-XW-0h
LEGEND: W = Write Only; -n = value after reset
Table 6-793 ICSS_INTC_STATUS_SET_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDWX
9-0STATUS_SET_INDEXW0hStatus Set Index Register (write index to set status)

4.14.7.6 ICSS_INTC_STATUS_CLR_INDEX_REG Register (Offset = 24h) [reset = X]

ICSS_INTC_STATUS_CLR_INDEX_REG is shown in Figure 6-407 and described in Table 6-795.

Return to Summary Table.

Status Clear Index Register

Table 6-794 ICSS_INTC_STATUS_CLR_INDEX_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0024h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0024h
Figure 6-407 ICSS_INTC_STATUS_CLR_INDEX_REG Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDSTATUS_CLR_INDEX
W-XW-0h
LEGEND: W = Write Only; -n = value after reset
Table 6-795 ICSS_INTC_STATUS_CLR_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDWX
9-0STATUS_CLR_INDEXW0hStatus Clear Index Register (write index to clear status of)

4.14.7.7 ICSS_INTC_ENABLE_SET_INDEX_REG Register (Offset = 28h) [reset = X]

ICSS_INTC_ENABLE_SET_INDEX_REG is shown in Figure 6-408 and described in Table 6-797.

Return to Summary Table.

Enable Set Index Register

Table 6-796 ICSS_INTC_ENABLE_SET_INDEX_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0028h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0028h
Figure 6-408 ICSS_INTC_ENABLE_SET_INDEX_REG Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDENABLE_SET_INDEX
W-XW1S-0h
LEGEND: W = Write Only; W1S = Write 1 to Set Bit; -n = value after reset
Table 6-797 ICSS_INTC_ENABLE_SET_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDWX
9-0ENABLE_SET_INDEXW1S0hEnable Set Index Register (write index to set enable of)

4.14.7.8 ICSS_INTC_ENABLE_CLR_INDEX_REG Register (Offset = 2Ch) [reset = X]

ICSS_INTC_ENABLE_CLR_INDEX_REG is shown in Figure 6-409 and described in Table 6-799.

Return to Summary Table.

Enable Clear Index Register

Table 6-798 ICSS_INTC_ENABLE_CLR_INDEX_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 002Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 002Ch
Figure 6-409 ICSS_INTC_ENABLE_CLR_INDEX_REG Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDENABLE_CLR_INDEX
W-XW1C-0h
LEGEND: W = Write Only; W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-799 ICSS_INTC_ENABLE_CLR_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDWX
9-0ENABLE_CLR_INDEXW1C0hEnable Clear Index Register (write index to clear enable of)

4.14.7.9 ICSS_INTC_HINT_ENABLE_SET_INDEX_REG Register (Offset = 34h) [reset = X]

ICSS_INTC_HINT_ENABLE_SET_INDEX_REG is shown in Figure 6-410 and described in Table 6-801.

Return to Summary Table.

Host Int Enable Set Index Register

Table 6-800 ICSS_INTC_HINT_ENABLE_SET_INDEX_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0034h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0034h
Figure 6-410 ICSS_INTC_HINT_ENABLE_SET_INDEX_REG Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDHINT_ENABLE_SET_INDEX
W-XW1S-0h
LEGEND: W = Write Only; W1S = Write 1 to Set Bit; -n = value after reset
Table 6-801 ICSS_INTC_HINT_ENABLE_SET_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDWX
9-0HINT_ENABLE_SET_INDEXW1S0hEnable SET for Host Interrupts

4.14.7.10 ICSS_INTC_HINT_ENABLE_CLR_INDEX_REG Register (Offset = 38h) [reset = X]

ICSS_INTC_HINT_ENABLE_CLR_INDEX_REG is shown in Figure 6-411 and described in Table 6-803.

Return to Summary Table.

Host Int Enable Clear Index Register

Table 6-802 ICSS_INTC_HINT_ENABLE_CLR_INDEX_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0038h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0038h
Figure 6-411 ICSS_INTC_HINT_ENABLE_CLR_INDEX_REG Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDHINT_ENABLE_CLR_INDEX
W-XW1C-0h
LEGEND: W = Write Only; W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-803 ICSS_INTC_HINT_ENABLE_CLR_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDWX
9-0HINT_ENABLE_CLR_INDEXW1C0hEnable CLEAR for Host Interrupts

4.14.7.11 ICSS_INTC_GLB_PRI_INTR_REG Register (Offset = 80h) [reset = X]

ICSS_INTC_GLB_PRI_INTR_REG is shown in Figure 6-412 and described in Table 6-805.

Return to Summary Table.

Global Prioritized Interrupt Register

Table 6-804 ICSS_INTC_GLB_PRI_INTR_REG Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0080h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0080h
Figure 6-412 ICSS_INTC_GLB_PRI_INTR_REG Register
3130292827262524
GLB_NONERESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDGLB_PRI_INTR
R-XR-0h
76543210
GLB_PRI_INTR
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-805 ICSS_INTC_GLB_PRI_INTR_REG Register Field Descriptions
BitFieldTypeResetDescription
31GLB_NONER1hNo interrupt pending flag
30-10RESERVEDRX
9-0GLB_PRI_INTRR0hPrioritized Interrupt

4.14.7.12 ICSS_INTC_RAW_STATUS_REG0 Register (Offset = 200h) [reset = 0h]

ICSS_INTC_RAW_STATUS_REG0 is shown in Figure 6-413 and described in Table 6-807.

Return to Summary Table.

Raw Status Register 0

Table 6-806 ICSS_INTC_RAW_STATUS_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0200h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0200h
Figure 6-413 ICSS_INTC_RAW_STATUS_REG0 Register
3130292827262524
RAW_STATUS_31RAW_STATUS_30RAW_STATUS_29RAW_STATUS_28RAW_STATUS_27RAW_STATUS_26RAW_STATUS_25RAW_STATUS_24
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
RAW_STATUS_23RAW_STATUS_22RAW_STATUS_21RAW_STATUS_20RAW_STATUS_19RAW_STATUS_18RAW_STATUS_17RAW_STATUS_16
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
RAW_STATUS_15RAW_STATUS_14RAW_STATUS_13RAW_STATUS_12RAW_STATUS_11RAW_STATUS_10RAW_STATUS_9RAW_STATUS_8
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
RAW_STATUS_7RAW_STATUS_6RAW_STATUS_5RAW_STATUS_4RAW_STATUS_3RAW_STATUS_2RAW_STATUS_1RAW_STATUS_0
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-807 ICSS_INTC_RAW_STATUS_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31RAW_STATUS_31W1S0hRaw Status (write 1 to set) for intr_in[31]
30RAW_STATUS_30W1S0hRaw Status (write 1 to set) for intr_in[30]
29RAW_STATUS_29W1S0hRaw Status (write 1 to set) for intr_in[29]
28RAW_STATUS_28W1S0hRaw Status (write 1 to set) for intr_in[28]
27RAW_STATUS_27W1S0hRaw Status (write 1 to set) for intr_in[27]
26RAW_STATUS_26W1S0hRaw Status (write 1 to set) for intr_in[26]
25RAW_STATUS_25W1S0hRaw Status (write 1 to set) for intr_in[25]
24RAW_STATUS_24W1S0hRaw Status (write 1 to set) for intr_in[24]
23RAW_STATUS_23W1S0hRaw Status (write 1 to set) for intr_in[23]
22RAW_STATUS_22W1S0hRaw Status (write 1 to set) for intr_in[22]
21RAW_STATUS_21W1S0hRaw Status (write 1 to set) for intr_in[21]
20RAW_STATUS_20W1S0hRaw Status (write 1 to set) for intr_in[20]
19RAW_STATUS_19W1S0hRaw Status (write 1 to set) for intr_in[19]
18RAW_STATUS_18W1S0hRaw Status (write 1 to set) for intr_in[18]
17RAW_STATUS_17W1S0hRaw Status (write 1 to set) for intr_in[17]
16RAW_STATUS_16W1S0hRaw Status (write 1 to set) for intr_in[16]
15RAW_STATUS_15W1S0hRaw Status (write 1 to set) for intr_in[15]
14RAW_STATUS_14W1S0hRaw Status (write 1 to set) for intr_in[14]
13RAW_STATUS_13W1S0hRaw Status (write 1 to set) for intr_in[13]
12RAW_STATUS_12W1S0hRaw Status (write 1 to set) for intr_in[12]
11RAW_STATUS_11W1S0hRaw Status (write 1 to set) for intr_in[11]
10RAW_STATUS_10W1S0hRaw Status (write 1 to set) for intr_in[10]
9RAW_STATUS_9W1S0hRaw Status (write 1 to set) for intr_in[9]
8RAW_STATUS_8W1S0hRaw Status (write 1 to set) for intr_in[8]
7RAW_STATUS_7W1S0hRaw Status (write 1 to set) for intr_in[7]
6RAW_STATUS_6W1S0hRaw Status (write 1 to set) for intr_in[6]
5RAW_STATUS_5W1S0hRaw Status (write 1 to set) for intr_in[5]
4RAW_STATUS_4W1S0hRaw Status (write 1 to set) for intr_in[4]
3RAW_STATUS_3W1S0hRaw Status (write 1 to set) for intr_in[3]
2RAW_STATUS_2W1S0hRaw Status (write 1 to set) for intr_in[2]
1RAW_STATUS_1W1S0hRaw Status (write 1 to set) for intr_in[1]
0RAW_STATUS_0W1S0hRaw Status (write 1 to set) for intr_in[0]

4.14.7.13 ICSS_INTC_RAW_STATUS_REG1 Register (Offset = 204h) [reset = 0h]

ICSS_INTC_RAW_STATUS_REG1 is shown in Figure 6-414 and described in Table 6-809.

Return to Summary Table.

Raw Status Register 1

Table 6-808 ICSS_INTC_RAW_STATUS_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0204h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0204h
Figure 6-414 ICSS_INTC_RAW_STATUS_REG1 Register
3130292827262524
RAW_STATUS_63RAW_STATUS_62RAW_STATUS_61RAW_STATUS_60RAW_STATUS_59RAW_STATUS_58RAW_STATUS_57RAW_STATUS_56
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
RAW_STATUS_55RAW_STATUS_54RAW_STATUS_53RAW_STATUS_52RAW_STATUS_51RAW_STATUS_50RAW_STATUS_49RAW_STATUS_48
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
RAW_STATUS_47RAW_STATUS_46RAW_STATUS_45RAW_STATUS_44RAW_STATUS_43RAW_STATUS_42RAW_STATUS_41RAW_STATUS_40
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
RAW_STATUS_39RAW_STATUS_38RAW_STATUS_37RAW_STATUS_36RAW_STATUS_35RAW_STATUS_34RAW_STATUS_33RAW_STATUS_32
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-809 ICSS_INTC_RAW_STATUS_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31RAW_STATUS_63W1S0hRaw Status (write 1 to set) for intr_in[63]
30RAW_STATUS_62W1S0hRaw Status (write 1 to set) for intr_in[62]
29RAW_STATUS_61W1S0hRaw Status (write 1 to set) for intr_in[61]
28RAW_STATUS_60W1S0hRaw Status (write 1 to set) for intr_in[60]
27RAW_STATUS_59W1S0hRaw Status (write 1 to set) for intr_in[59]
26RAW_STATUS_58W1S0hRaw Status (write 1 to set) for intr_in[58]
25RAW_STATUS_57W1S0hRaw Status (write 1 to set) for intr_in[57]
24RAW_STATUS_56W1S0hRaw Status (write 1 to set) for intr_in[56]
23RAW_STATUS_55W1S0hRaw Status (write 1 to set) for intr_in[55]
22RAW_STATUS_54W1S0hRaw Status (write 1 to set) for intr_in[54]
21RAW_STATUS_53W1S0hRaw Status (write 1 to set) for intr_in[53]
20RAW_STATUS_52W1S0hRaw Status (write 1 to set) for intr_in[52]
19RAW_STATUS_51W1S0hRaw Status (write 1 to set) for intr_in[51]
18RAW_STATUS_50W1S0hRaw Status (write 1 to set) for intr_in[50]
17RAW_STATUS_49W1S0hRaw Status (write 1 to set) for intr_in[49]
16RAW_STATUS_48W1S0hRaw Status (write 1 to set) for intr_in[48]
15RAW_STATUS_47W1S0hRaw Status (write 1 to set) for intr_in[47]
14RAW_STATUS_46W1S0hRaw Status (write 1 to set) for intr_in[46]
13RAW_STATUS_45W1S0hRaw Status (write 1 to set) for intr_in[45]
12RAW_STATUS_44W1S0hRaw Status (write 1 to set) for intr_in[44]
11RAW_STATUS_43W1S0hRaw Status (write 1 to set) for intr_in[43]
10RAW_STATUS_42W1S0hRaw Status (write 1 to set) for intr_in[42]
9RAW_STATUS_41W1S0hRaw Status (write 1 to set) for intr_in[41]
8RAW_STATUS_40W1S0hRaw Status (write 1 to set) for intr_in[40]
7RAW_STATUS_39W1S0hRaw Status (write 1 to set) for intr_in[39]
6RAW_STATUS_38W1S0hRaw Status (write 1 to set) for intr_in[38]
5RAW_STATUS_37W1S0hRaw Status (write 1 to set) for intr_in[37]
4RAW_STATUS_36W1S0hRaw Status (write 1 to set) for intr_in[36]
3RAW_STATUS_35W1S0hRaw Status (write 1 to set) for intr_in[35]
2RAW_STATUS_34W1S0hRaw Status (write 1 to set) for intr_in[34]
1RAW_STATUS_33W1S0hRaw Status (write 1 to set) for intr_in[33]
0RAW_STATUS_32W1S0hRaw Status (write 1 to set) for intr_in[32]

4.14.7.14 ICSS_INTC_RAW_STATUS_REG2 Register (Offset = 208h) [reset = 0h]

ICSS_INTC_RAW_STATUS_REG2 is shown in Figure 6-415 and described in Table 6-811.

Return to Summary Table.

Raw Status Register 2

Table 6-810 ICSS_INTC_RAW_STATUS_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0208h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0208h
Figure 6-415 ICSS_INTC_RAW_STATUS_REG2 Register
3130292827262524
RAW_STATUS_95RAW_STATUS_94RAW_STATUS_93RAW_STATUS_92RAW_STATUS_91RAW_STATUS_90RAW_STATUS_89RAW_STATUS_88
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
RAW_STATUS_87RAW_STATUS_86RAW_STATUS_85RAW_STATUS_84RAW_STATUS_83RAW_STATUS_82RAW_STATUS_81RAW_STATUS_80
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
RAW_STATUS_79RAW_STATUS_78RAW_STATUS_77RAW_STATUS_76RAW_STATUS_75RAW_STATUS_74RAW_STATUS_73RAW_STATUS_72
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
RAW_STATUS_71RAW_STATUS_70RAW_STATUS_69RAW_STATUS_68RAW_STATUS_67RAW_STATUS_66RAW_STATUS_65RAW_STATUS_64
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-811 ICSS_INTC_RAW_STATUS_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31RAW_STATUS_95W1S0hRaw Status (write 1 to set) for slv_events_in[31]
30RAW_STATUS_94W1S0hRaw Status (write 1 to set) for slv_events_in[30]
29RAW_STATUS_93W1S0hRaw Status (write 1 to set) for slv_events_in[29]
28RAW_STATUS_92W1S0hRaw Status (write 1 to set) for slv_events_in[28]
27RAW_STATUS_91W1S0hRaw Status (write 1 to set) for slv_events_in[27]
26RAW_STATUS_90W1S0hRaw Status (write 1 to set) for slv_events_in[26]
25RAW_STATUS_89W1S0hRaw Status (write 1 to set) for slv_events_in[25]
24RAW_STATUS_88W1S0hRaw Status (write 1 to set) for slv_events_in[24]
23RAW_STATUS_87W1S0hRaw Status (write 1 to set) for slv_events_in[23]
22RAW_STATUS_86W1S0hRaw Status (write 1 to set) for slv_events_in[22]
21RAW_STATUS_85W1S0hRaw Status (write 1 to set) for slv_events_in[21]
20RAW_STATUS_84W1S0hRaw Status (write 1 to set) for slv_events_in[20]
19RAW_STATUS_83W1S0hRaw Status (write 1 to set) for slv_events_in[19]
18RAW_STATUS_82W1S0hRaw Status (write 1 to set) for slv_events_in[18]
17RAW_STATUS_81W1S0hRaw Status (write 1 to set) for slv_events_in[17]
16RAW_STATUS_80W1S0hRaw Status (write 1 to set) for slv_events_in[16]
15RAW_STATUS_79W1S0hRaw Status (write 1 to set) for slv_events_in[15]
14RAW_STATUS_78W1S0hRaw Status (write 1 to set) for slv_events_in[14]
13RAW_STATUS_77W1S0hRaw Status (write 1 to set) for slv_events_in[13]
12RAW_STATUS_76W1S0hRaw Status (write 1 to set) for slv_events_in[12]
11RAW_STATUS_75W1S0hRaw Status (write 1 to set) for slv_events_in[11]
10RAW_STATUS_74W1S0hRaw Status (write 1 to set) for slv_events_in[10]
9RAW_STATUS_73W1S0hRaw Status (write 1 to set) for slv_events_in[9]
8RAW_STATUS_72W1S0hRaw Status (write 1 to set) for slv_events_in[8]
7RAW_STATUS_71W1S0hRaw Status (write 1 to set) for slv_events_in[7]
6RAW_STATUS_70W1S0hRaw Status (write 1 to set) for slv_events_in[6]
5RAW_STATUS_69W1S0hRaw Status (write 1 to set) for slv_events_in[5]
4RAW_STATUS_68W1S0hRaw Status (write 1 to set) for slv_events_in[4]
3RAW_STATUS_67W1S0hRaw Status (write 1 to set) for slv_events_in[3]
2RAW_STATUS_66W1S0hRaw Status (write 1 to set) for slv_events_in[2]
1RAW_STATUS_65W1S0hRaw Status (write 1 to set) for slv_events_in[1]
0RAW_STATUS_64W1S0hRaw Status (write 1 to set) for slv_events_in[0]

4.14.7.15 ICSS_INTC_RAW_STATUS_REG3 Register (Offset = 20Ch) [reset = 0h]

ICSS_INTC_RAW_STATUS_REG3 is shown in Figure 6-416 and described in Table 6-813.

Return to Summary Table.

Raw Status Register 3

Table 6-812 ICSS_INTC_RAW_STATUS_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 020Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 020Ch
Figure 6-416 ICSS_INTC_RAW_STATUS_REG3 Register
3130292827262524
RAW_STATUS_127RAW_STATUS_126RAW_STATUS_125RAW_STATUS_124RAW_STATUS_123RAW_STATUS_122RAW_STATUS_121RAW_STATUS_120
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
RAW_STATUS_119RAW_STATUS_118RAW_STATUS_117RAW_STATUS_116RAW_STATUS_115RAW_STATUS_114RAW_STATUS_113RAW_STATUS_112
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
RAW_STATUS_111RAW_STATUS_110RAW_STATUS_109RAW_STATUS_108RAW_STATUS_107RAW_STATUS_106RAW_STATUS_105RAW_STATUS_104
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
RAW_STATUS_103RAW_STATUS_102RAW_STATUS_101RAW_STATUS_100RAW_STATUS_99RAW_STATUS_98RAW_STATUS_97RAW_STATUS_96
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-813 ICSS_INTC_RAW_STATUS_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31RAW_STATUS_127W1S0hRaw Status (write 1 to set) for slv_events_in[63]
30RAW_STATUS_126W1S0hRaw Status (write 1 to set) for slv_events_in[62]
29RAW_STATUS_125W1S0hRaw Status (write 1 to set) for slv_events_in[61]
28RAW_STATUS_124W1S0hRaw Status (write 1 to set) for slv_events_in[60]
27RAW_STATUS_123W1S0hRaw Status (write 1 to set) for slv_events_in[59]
26RAW_STATUS_122W1S0hRaw Status (write 1 to set) for slv_events_in[58]
25RAW_STATUS_121W1S0hRaw Status (write 1 to set) for slv_events_in[57]
24RAW_STATUS_120W1S0hRaw Status (write 1 to set) for slv_events_in[56]
23RAW_STATUS_119W1S0hRaw Status (write 1 to set) for slv_events_in[55]
22RAW_STATUS_118W1S0hRaw Status (write 1 to set) for slv_events_in[54]
21RAW_STATUS_117W1S0hRaw Status (write 1 to set) for slv_events_in[53]
20RAW_STATUS_116W1S0hRaw Status (write 1 to set) for slv_events_in[52]
19RAW_STATUS_115W1S0hRaw Status (write 1 to set) for slv_events_in[51]
18RAW_STATUS_114W1S0hRaw Status (write 1 to set) for slv_events_in[50]
17RAW_STATUS_113W1S0hRaw Status (write 1 to set) for slv_events_in[49]
16RAW_STATUS_112W1S0hRaw Status (write 1 to set) for slv_events_in[48]
15RAW_STATUS_111W1S0hRaw Status (write 1 to set) for slv_events_in[47]
14RAW_STATUS_110W1S0hRaw Status (write 1 to set) for slv_events_in[46]
13RAW_STATUS_109W1S0hRaw Status (write 1 to set) for slv_events_in[45]
12RAW_STATUS_108W1S0hRaw Status (write 1 to set) for slv_events_in[44]
11RAW_STATUS_107W1S0hRaw Status (write 1 to set) for slv_events_in[43]
10RAW_STATUS_106W1S0hRaw Status (write 1 to set) for slv_events_in[42]
9RAW_STATUS_105W1S0hRaw Status (write 1 to set) for slv_events_in[41]
8RAW_STATUS_104W1S0hRaw Status (write 1 to set) for slv_events_in[40]
7RAW_STATUS_103W1S0hRaw Status (write 1 to set) for slv_events_in[39]
6RAW_STATUS_102W1S0hRaw Status (write 1 to set) for slv_events_in[38]
5RAW_STATUS_101W1S0hRaw Status (write 1 to set) for slv_events_in[37]
4RAW_STATUS_100W1S0hRaw Status (write 1 to set) for slv_events_in[36]
3RAW_STATUS_99W1S0hRaw Status (write 1 to set) for slv_events_in[35]
2RAW_STATUS_98W1S0hRaw Status (write 1 to set) for slv_events_in[34]
1RAW_STATUS_97W1S0hRaw Status (write 1 to set) for slv_events_in[33]
0RAW_STATUS_96W1S0hRaw Status (write 1 to set) for slv_events_in[32]

4.14.7.16 ICSS_INTC_RAW_STATUS_REG4 Register (Offset = 210h) [reset = 0h]

ICSS_INTC_RAW_STATUS_REG4 is shown in Figure 6-417 and described in Table 6-815.

Return to Summary Table.

Raw Status Register 4

Table 6-814 ICSS_INTC_RAW_STATUS_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0210h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0210h
Figure 6-417 ICSS_INTC_RAW_STATUS_REG4 Register
3130292827262524
RAW_STATUS_159RAW_STATUS_158RAW_STATUS_157RAW_STATUS_156RAW_STATUS_155RAW_STATUS_154RAW_STATUS_153RAW_STATUS_152
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
RAW_STATUS_151RAW_STATUS_150RAW_STATUS_149RAW_STATUS_148RAW_STATUS_147RAW_STATUS_146RAW_STATUS_145RAW_STATUS_144
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
RAW_STATUS_143RAW_STATUS_142RAW_STATUS_141RAW_STATUS_140RAW_STATUS_139RAW_STATUS_138RAW_STATUS_137RAW_STATUS_136
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
RAW_STATUS_135RAW_STATUS_134RAW_STATUS_133RAW_STATUS_132RAW_STATUS_131RAW_STATUS_130RAW_STATUS_129RAW_STATUS_128
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-815 ICSS_INTC_RAW_STATUS_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31RAW_STATUS_159W1S0hRaw Status (write 1 to set) for slv_events_in[95]
30RAW_STATUS_158W1S0hRaw Status (write 1 to set) for slv_events_in[94]
29RAW_STATUS_157W1S0hRaw Status (write 1 to set) for slv_events_in[93]
28RAW_STATUS_156W1S0hRaw Status (write 1 to set) for slv_events_in[92]
27RAW_STATUS_155W1S0hRaw Status (write 1 to set) for slv_events_in[91]
26RAW_STATUS_154W1S0hRaw Status (write 1 to set) for slv_events_in[90]
25RAW_STATUS_153W1S0hRaw Status (write 1 to set) for slv_events_in[89]
24RAW_STATUS_152W1S0hRaw Status (write 1 to set) for slv_events_in[88]
23RAW_STATUS_151W1S0hRaw Status (write 1 to set) for slv_events_in[87]
22RAW_STATUS_150W1S0hRaw Status (write 1 to set) for slv_events_in[86]
21RAW_STATUS_149W1S0hRaw Status (write 1 to set) for slv_events_in[85]
20RAW_STATUS_148W1S0hRaw Status (write 1 to set) for slv_events_in[84]
19RAW_STATUS_147W1S0hRaw Status (write 1 to set) for slv_events_in[83]
18RAW_STATUS_146W1S0hRaw Status (write 1 to set) for slv_events_in[82]
17RAW_STATUS_145W1S0hRaw Status (write 1 to set) for slv_events_in[81]
16RAW_STATUS_144W1S0hRaw Status (write 1 to set) for slv_events_in[80]
15RAW_STATUS_143W1S0hRaw Status (write 1 to set) for slv_events_in[79]
14RAW_STATUS_142W1S0hRaw Status (write 1 to set) for slv_events_in[78]
13RAW_STATUS_141W1S0hRaw Status (write 1 to set) for slv_events_in[77]
12RAW_STATUS_140W1S0hRaw Status (write 1 to set) for slv_events_in[76]
11RAW_STATUS_139W1S0hRaw Status (write 1 to set) for slv_events_in[75]
10RAW_STATUS_138W1S0hRaw Status (write 1 to set) for slv_events_in[74]
9RAW_STATUS_137W1S0hRaw Status (write 1 to set) for slv_events_in[73]
8RAW_STATUS_136W1S0hRaw Status (write 1 to set) for slv_events_in[72]
7RAW_STATUS_135W1S0hRaw Status (write 1 to set) for slv_events_in[71]
6RAW_STATUS_134W1S0hRaw Status (write 1 to set) for slv_events_in[70]
5RAW_STATUS_133W1S0hRaw Status (write 1 to set) for slv_events_in[69]
4RAW_STATUS_132W1S0hRaw Status (write 1 to set) for slv_events_in[68]
3RAW_STATUS_131W1S0hRaw Status (write 1 to set) for slv_events_in[67]
2RAW_STATUS_130W1S0hRaw Status (write 1 to set) for slv_events_in[66]
1RAW_STATUS_129W1S0hRaw Status (write 1 to set) for slv_events_in[65]
0RAW_STATUS_128W1S0hRaw Status (write 1 to set) for slv_events_in[64]

4.14.7.17 ICSS_INTC_ENA_STATUS_REG0 Register (Offset = 280h) [reset = 0h]

ICSS_INTC_ENA_STATUS_REG0 is shown in Figure 6-418 and described in Table 6-817.

Return to Summary Table.

Enabled Status Register 0

Table 6-816 ICSS_INTC_ENA_STATUS_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0280h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0280h
Figure 6-418 ICSS_INTC_ENA_STATUS_REG0 Register
3130292827262524
ENA_STATUS_31ENA_STATUS_30ENA_STATUS_29ENA_STATUS_28ENA_STATUS_27ENA_STATUS_26ENA_STATUS_25ENA_STATUS_24
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENA_STATUS_23ENA_STATUS_22ENA_STATUS_21ENA_STATUS_20ENA_STATUS_19ENA_STATUS_18ENA_STATUS_17ENA_STATUS_16
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENA_STATUS_15ENA_STATUS_14ENA_STATUS_13ENA_STATUS_12ENA_STATUS_11ENA_STATUS_10ENA_STATUS_9ENA_STATUS_8
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENA_STATUS_7ENA_STATUS_6ENA_STATUS_5ENA_STATUS_4ENA_STATUS_3ENA_STATUS_2ENA_STATUS_1ENA_STATUS_0
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-817 ICSS_INTC_ENA_STATUS_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31ENA_STATUS_31W1C0hEnabled Status for intr_in[31]
30ENA_STATUS_30W1C0hEnabled Status for intr_in[30]
29ENA_STATUS_29W1C0hEnabled Status for intr_in[29]
28ENA_STATUS_28W1C0hEnabled Status for intr_in[28]
27ENA_STATUS_27W1C0hEnabled Status for intr_in[27]
26ENA_STATUS_26W1C0hEnabled Status for intr_in[26]
25ENA_STATUS_25W1C0hEnabled Status for intr_in[25]
24ENA_STATUS_24W1C0hEnabled Status for intr_in[24]
23ENA_STATUS_23W1C0hEnabled Status for intr_in[23]
22ENA_STATUS_22W1C0hEnabled Status for intr_in[22]
21ENA_STATUS_21W1C0hEnabled Status for intr_in[21]
20ENA_STATUS_20W1C0hEnabled Status for intr_in[20]
19ENA_STATUS_19W1C0hEnabled Status for intr_in[19]
18ENA_STATUS_18W1C0hEnabled Status for intr_in[18]
17ENA_STATUS_17W1C0hEnabled Status for intr_in[17]
16ENA_STATUS_16W1C0hEnabled Status for intr_in[16]
15ENA_STATUS_15W1C0hEnabled Status for intr_in[15]
14ENA_STATUS_14W1C0hEnabled Status for intr_in[14]
13ENA_STATUS_13W1C0hEnabled Status for intr_in[13]
12ENA_STATUS_12W1C0hEnabled Status for intr_in[12]
11ENA_STATUS_11W1C0hEnabled Status for intr_in[11]
10ENA_STATUS_10W1C0hEnabled Status for intr_in[10]
9ENA_STATUS_9W1C0hEnabled Status for intr_in[9]
8ENA_STATUS_8W1C0hEnabled Status for intr_in[8]
7ENA_STATUS_7W1C0hEnabled Status for intr_in[7]
6ENA_STATUS_6W1C0hEnabled Status for intr_in[6]
5ENA_STATUS_5W1C0hEnabled Status for intr_in[5]
4ENA_STATUS_4W1C0hEnabled Status for intr_in[4]
3ENA_STATUS_3W1C0hEnabled Status for intr_in[3]
2ENA_STATUS_2W1C0hEnabled Status for intr_in[2]
1ENA_STATUS_1W1C0hEnabled Status for intr_in[1]
0ENA_STATUS_0W1C0hEnabled Status for intr_in[0]

4.14.7.18 ICSS_INTC_ENA_STATUS_REG1 Register (Offset = 284h) [reset = 0h]

ICSS_INTC_ENA_STATUS_REG1 is shown in Figure 6-419 and described in Table 6-819.

Return to Summary Table.

Enabled Status Register 1

Table 6-818 ICSS_INTC_ENA_STATUS_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0284h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0284h
Figure 6-419 ICSS_INTC_ENA_STATUS_REG1 Register
3130292827262524
ENA_STATUS_63ENA_STATUS_62ENA_STATUS_61ENA_STATUS_60ENA_STATUS_59ENA_STATUS_58ENA_STATUS_57ENA_STATUS_56
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENA_STATUS_55ENA_STATUS_54ENA_STATUS_53ENA_STATUS_52ENA_STATUS_51ENA_STATUS_50ENA_STATUS_49ENA_STATUS_48
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENA_STATUS_47ENA_STATUS_46ENA_STATUS_45ENA_STATUS_44ENA_STATUS_43ENA_STATUS_42ENA_STATUS_41ENA_STATUS_40
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENA_STATUS_39ENA_STATUS_38ENA_STATUS_37ENA_STATUS_36ENA_STATUS_35ENA_STATUS_34ENA_STATUS_33ENA_STATUS_32
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-819 ICSS_INTC_ENA_STATUS_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31ENA_STATUS_63W1C0hEnabled Status for intr_in[63]
30ENA_STATUS_62W1C0hEnabled Status for intr_in[62]
29ENA_STATUS_61W1C0hEnabled Status for intr_in[61]
28ENA_STATUS_60W1C0hEnabled Status for intr_in[60]
27ENA_STATUS_59W1C0hEnabled Status for intr_in[59]
26ENA_STATUS_58W1C0hEnabled Status for intr_in[58]
25ENA_STATUS_57W1C0hEnabled Status for intr_in[57]
24ENA_STATUS_56W1C0hEnabled Status for intr_in[56]
23ENA_STATUS_55W1C0hEnabled Status for intr_in[55]
22ENA_STATUS_54W1C0hEnabled Status for intr_in[54]
21ENA_STATUS_53W1C0hEnabled Status for intr_in[53]
20ENA_STATUS_52W1C0hEnabled Status for intr_in[52]
19ENA_STATUS_51W1C0hEnabled Status for intr_in[51]
18ENA_STATUS_50W1C0hEnabled Status for intr_in[50]
17ENA_STATUS_49W1C0hEnabled Status for intr_in[49]
16ENA_STATUS_48W1C0hEnabled Status for intr_in[48]
15ENA_STATUS_47W1C0hEnabled Status for intr_in[47]
14ENA_STATUS_46W1C0hEnabled Status for intr_in[46]
13ENA_STATUS_45W1C0hEnabled Status for intr_in[45]
12ENA_STATUS_44W1C0hEnabled Status for intr_in[44]
11ENA_STATUS_43W1C0hEnabled Status for intr_in[43]
10ENA_STATUS_42W1C0hEnabled Status for intr_in[42]
9ENA_STATUS_41W1C0hEnabled Status for intr_in[41]
8ENA_STATUS_40W1C0hEnabled Status for intr_in[40]
7ENA_STATUS_39W1C0hEnabled Status for intr_in[39]
6ENA_STATUS_38W1C0hEnabled Status for intr_in[38]
5ENA_STATUS_37W1C0hEnabled Status for intr_in[37]
4ENA_STATUS_36W1C0hEnabled Status for intr_in[36]
3ENA_STATUS_35W1C0hEnabled Status for intr_in[35]
2ENA_STATUS_34W1C0hEnabled Status for intr_in[34]
1ENA_STATUS_33W1C0hEnabled Status for intr_in[33]
0ENA_STATUS_32W1C0hEnabled Status for intr_in[32]

4.14.7.19 ICSS_INTC_ENA_STATUS_REG2 Register (Offset = 288h) [reset = 0h]

ICSS_INTC_ENA_STATUS_REG2 is shown in Figure 6-420 and described in Table 6-821.

Return to Summary Table.

Enabled Status Register 2

Table 6-820 ICSS_INTC_ENA_STATUS_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0288h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0288h
Figure 6-420 ICSS_INTC_ENA_STATUS_REG2 Register
3130292827262524
ENA_STATUS_95ENA_STATUS_94ENA_STATUS_93ENA_STATUS_92ENA_STATUS_91ENA_STATUS_90ENA_STATUS_89ENA_STATUS_88
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENA_STATUS_87ENA_STATUS_86ENA_STATUS_85ENA_STATUS_84ENA_STATUS_83ENA_STATUS_82ENA_STATUS_81ENA_STATUS_80
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENA_STATUS_79ENA_STATUS_78ENA_STATUS_77ENA_STATUS_76ENA_STATUS_75ENA_STATUS_74ENA_STATUS_73ENA_STATUS_72
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENA_STATUS_71ENA_STATUS_70ENA_STATUS_69ENA_STATUS_68ENA_STATUS_67ENA_STATUS_66ENA_STATUS_65ENA_STATUS_64
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-821 ICSS_INTC_ENA_STATUS_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31ENA_STATUS_95W1C0hEnabled Status for slv_events_in[31]
30ENA_STATUS_94W1C0hEnabled Status for slv_events_in[30]
29ENA_STATUS_93W1C0hEnabled Status for slv_events_in[29]
28ENA_STATUS_92W1C0hEnabled Status for slv_events_in[28]
27ENA_STATUS_91W1C0hEnabled Status for slv_events_in[27]
26ENA_STATUS_90W1C0hEnabled Status for slv_events_in[26]
25ENA_STATUS_89W1C0hEnabled Status for slv_events_in[25]
24ENA_STATUS_88W1C0hEnabled Status for slv_events_in[24]
23ENA_STATUS_87W1C0hEnabled Status for slv_events_in[23]
22ENA_STATUS_86W1C0hEnabled Status for slv_events_in[22]
21ENA_STATUS_85W1C0hEnabled Status for slv_events_in[21]
20ENA_STATUS_84W1C0hEnabled Status for slv_events_in[20]
19ENA_STATUS_83W1C0hEnabled Status for slv_events_in[19]
18ENA_STATUS_82W1C0hEnabled Status for slv_events_in[18]
17ENA_STATUS_81W1C0hEnabled Status for slv_events_in[17]
16ENA_STATUS_80W1C0hEnabled Status for slv_events_in[16]
15ENA_STATUS_79W1C0hEnabled Status for slv_events_in[15]
14ENA_STATUS_78W1C0hEnabled Status for slv_events_in[14]
13ENA_STATUS_77W1C0hEnabled Status for slv_events_in[13]
12ENA_STATUS_76W1C0hEnabled Status for slv_events_in[12]
11ENA_STATUS_75W1C0hEnabled Status for slv_events_in[11]
10ENA_STATUS_74W1C0hEnabled Status for slv_events_in[10]
9ENA_STATUS_73W1C0hEnabled Status for slv_events_in[9]
8ENA_STATUS_72W1C0hEnabled Status for slv_events_in[8]
7ENA_STATUS_71W1C0hEnabled Status for slv_events_in[7]
6ENA_STATUS_70W1C0hEnabled Status for slv_events_in[6]
5ENA_STATUS_69W1C0hEnabled Status for slv_events_in[5]
4ENA_STATUS_68W1C0hEnabled Status for slv_events_in[4]
3ENA_STATUS_67W1C0hEnabled Status for slv_events_in[3]
2ENA_STATUS_66W1C0hEnabled Status for slv_events_in[2]
1ENA_STATUS_65W1C0hEnabled Status for slv_events_in[1]
0ENA_STATUS_64W1C0hEnabled Status for slv_events_in[0]

4.14.7.20 ICSS_INTC_ENA_STATUS_REG3 Register (Offset = 28Ch) [reset = 0h]

ICSS_INTC_ENA_STATUS_REG3 is shown in Figure 6-421 and described in Table 6-823.

Return to Summary Table.

Enabled Status Register 3

Table 6-822 ICSS_INTC_ENA_STATUS_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 028Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 028Ch
Figure 6-421 ICSS_INTC_ENA_STATUS_REG3 Register
3130292827262524
ENA_STATUS_127ENA_STATUS_126ENA_STATUS_125ENA_STATUS_124ENA_STATUS_123ENA_STATUS_122ENA_STATUS_121ENA_STATUS_120
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENA_STATUS_119ENA_STATUS_118ENA_STATUS_117ENA_STATUS_116ENA_STATUS_115ENA_STATUS_114ENA_STATUS_113ENA_STATUS_112
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENA_STATUS_111ENA_STATUS_110ENA_STATUS_109ENA_STATUS_108ENA_STATUS_107ENA_STATUS_106ENA_STATUS_105ENA_STATUS_104
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENA_STATUS_103ENA_STATUS_102ENA_STATUS_101ENA_STATUS_100ENA_STATUS_99ENA_STATUS_98ENA_STATUS_97ENA_STATUS_96
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-823 ICSS_INTC_ENA_STATUS_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31ENA_STATUS_127W1C0hEnabled Status for slv_events_in[63]
30ENA_STATUS_126W1C0hEnabled Status for slv_events_in[62]
29ENA_STATUS_125W1C0hEnabled Status for slv_events_in[61]
28ENA_STATUS_124W1C0hEnabled Status for slv_events_in[60]
27ENA_STATUS_123W1C0hEnabled Status for slv_events_in[59]
26ENA_STATUS_122W1C0hEnabled Status for slv_events_in[58]
25ENA_STATUS_121W1C0hEnabled Status for slv_events_in[57]
24ENA_STATUS_120W1C0hEnabled Status for slv_events_in[56]
23ENA_STATUS_119W1C0hEnabled Status for slv_events_in[55]
22ENA_STATUS_118W1C0hEnabled Status for slv_events_in[54]
21ENA_STATUS_117W1C0hEnabled Status for slv_events_in[53]
20ENA_STATUS_116W1C0hEnabled Status for slv_events_in[52]
19ENA_STATUS_115W1C0hEnabled Status for slv_events_in[51]
18ENA_STATUS_114W1C0hEnabled Status for slv_events_in[50]
17ENA_STATUS_113W1C0hEnabled Status for slv_events_in[49]
16ENA_STATUS_112W1C0hEnabled Status for slv_events_in[48]
15ENA_STATUS_111W1C0hEnabled Status for slv_events_in[47]
14ENA_STATUS_110W1C0hEnabled Status for slv_events_in[46]
13ENA_STATUS_109W1C0hEnabled Status for slv_events_in[45]
12ENA_STATUS_108W1C0hEnabled Status for slv_events_in[44]
11ENA_STATUS_107W1C0hEnabled Status for slv_events_in[43]
10ENA_STATUS_106W1C0hEnabled Status for slv_events_in[42]
9ENA_STATUS_105W1C0hEnabled Status for slv_events_in[41]
8ENA_STATUS_104W1C0hEnabled Status for slv_events_in[40]
7ENA_STATUS_103W1C0hEnabled Status for slv_events_in[39]
6ENA_STATUS_102W1C0hEnabled Status for slv_events_in[38]
5ENA_STATUS_101W1C0hEnabled Status for slv_events_in[37]
4ENA_STATUS_100W1C0hEnabled Status for slv_events_in[36]
3ENA_STATUS_99W1C0hEnabled Status for slv_events_in[35]
2ENA_STATUS_98W1C0hEnabled Status for slv_events_in[34]
1ENA_STATUS_97W1C0hEnabled Status for slv_events_in[33]
0ENA_STATUS_96W1C0hEnabled Status for slv_events_in[32]

4.14.7.21 ICSS_INTC_ENA_STATUS_REG4 Register (Offset = 290h) [reset = 0h]

ICSS_INTC_ENA_STATUS_REG4 is shown in Figure 6-422 and described in Table 6-825.

Return to Summary Table.

Enabled Status Register 4

Table 6-824 ICSS_INTC_ENA_STATUS_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0290h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0290h
Figure 6-422 ICSS_INTC_ENA_STATUS_REG4 Register
3130292827262524
ENA_STATUS_159ENA_STATUS_158ENA_STATUS_157ENA_STATUS_156ENA_STATUS_155ENA_STATUS_154ENA_STATUS_153ENA_STATUS_152
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENA_STATUS_151ENA_STATUS_150ENA_STATUS_149ENA_STATUS_148ENA_STATUS_147ENA_STATUS_146ENA_STATUS_145ENA_STATUS_144
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENA_STATUS_143ENA_STATUS_142ENA_STATUS_141ENA_STATUS_140ENA_STATUS_139ENA_STATUS_138ENA_STATUS_137ENA_STATUS_136
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENA_STATUS_135ENA_STATUS_134ENA_STATUS_133ENA_STATUS_132ENA_STATUS_131ENA_STATUS_130ENA_STATUS_129ENA_STATUS_128
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-825 ICSS_INTC_ENA_STATUS_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31ENA_STATUS_159W1C0hEnabled Status for slv_events_in[95]
30ENA_STATUS_158W1C0hEnabled Status for slv_events_in[94]
29ENA_STATUS_157W1C0hEnabled Status for slv_events_in[93]
28ENA_STATUS_156W1C0hEnabled Status for slv_events_in[92]
27ENA_STATUS_155W1C0hEnabled Status for slv_events_in[91]
26ENA_STATUS_154W1C0hEnabled Status for slv_events_in[90]
25ENA_STATUS_153W1C0hEnabled Status for slv_events_in[89]
24ENA_STATUS_152W1C0hEnabled Status for slv_events_in[88]
23ENA_STATUS_151W1C0hEnabled Status for slv_events_in[87]
22ENA_STATUS_150W1C0hEnabled Status for slv_events_in[86]
21ENA_STATUS_149W1C0hEnabled Status for slv_events_in[85]
20ENA_STATUS_148W1C0hEnabled Status for slv_events_in[84]
19ENA_STATUS_147W1C0hEnabled Status for slv_events_in[83]
18ENA_STATUS_146W1C0hEnabled Status for slv_events_in[82]
17ENA_STATUS_145W1C0hEnabled Status for slv_events_in[81]
16ENA_STATUS_144W1C0hEnabled Status for slv_events_in[80]
15ENA_STATUS_143W1C0hEnabled Status for slv_events_in[79]
14ENA_STATUS_142W1C0hEnabled Status for slv_events_in[78]
13ENA_STATUS_141W1C0hEnabled Status for slv_events_in[77]
12ENA_STATUS_140W1C0hEnabled Status for slv_events_in[76]
11ENA_STATUS_139W1C0hEnabled Status for slv_events_in[75]
10ENA_STATUS_138W1C0hEnabled Status for slv_events_in[74]
9ENA_STATUS_137W1C0hEnabled Status for slv_events_in[73]
8ENA_STATUS_136W1C0hEnabled Status for slv_events_in[72]
7ENA_STATUS_135W1C0hEnabled Status for slv_events_in[71]
6ENA_STATUS_134W1C0hEnabled Status for slv_events_in[70]
5ENA_STATUS_133W1C0hEnabled Status for slv_events_in[69]
4ENA_STATUS_132W1C0hEnabled Status for slv_events_in[68]
3ENA_STATUS_131W1C0hEnabled Status for slv_events_in[67]
2ENA_STATUS_130W1C0hEnabled Status for slv_events_in[66]
1ENA_STATUS_129W1C0hEnabled Status for slv_events_in[65]
0ENA_STATUS_128W1C0hEnabled Status for slv_events_in[64]

4.14.7.22 ICSS_INTC_ENABLE_REG0 Register (Offset = 300h) [reset = 0h]

ICSS_INTC_ENABLE_REG0 is shown in Figure 6-423 and described in Table 6-827.

Return to Summary Table.

Enable Register 0

Table 6-826 ICSS_INTC_ENABLE_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0300h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0300h
Figure 6-423 ICSS_INTC_ENABLE_REG0 Register
3130292827262524
ENABLE_31ENABLE_30ENABLE_29ENABLE_28ENABLE_27ENABLE_26ENABLE_25ENABLE_24
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
ENABLE_23ENABLE_22ENABLE_21ENABLE_20ENABLE_19ENABLE_18ENABLE_17ENABLE_16
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
ENABLE_15ENABLE_14ENABLE_13ENABLE_12ENABLE_11ENABLE_10ENABLE_9ENABLE_8
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
ENABLE_7ENABLE_6ENABLE_5ENABLE_4ENABLE_3ENABLE_2ENABLE_1ENABLE_0
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-827 ICSS_INTC_ENABLE_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_31W1S0hEnable (set) for intr_in[31]
30ENABLE_30W1S0hEnable (set) for intr_in[30]
29ENABLE_29W1S0hEnable (set) for intr_in[29]
28ENABLE_28W1S0hEnable (set) for intr_in[28]
27ENABLE_27W1S0hEnable (set) for intr_in[27]
26ENABLE_26W1S0hEnable (set) for intr_in[26]
25ENABLE_25W1S0hEnable (set) for intr_in[25]
24ENABLE_24W1S0hEnable (set) for intr_in[24]
23ENABLE_23W1S0hEnable (set) for intr_in[23]
22ENABLE_22W1S0hEnable (set) for intr_in[22]
21ENABLE_21W1S0hEnable (set) for intr_in[21]
20ENABLE_20W1S0hEnable (set) for intr_in[20]
19ENABLE_19W1S0hEnable (set) for intr_in[19]
18ENABLE_18W1S0hEnable (set) for intr_in[18]
17ENABLE_17W1S0hEnable (set) for intr_in[17]
16ENABLE_16W1S0hEnable (set) for intr_in[16]
15ENABLE_15W1S0hEnable (set) for intr_in[15]
14ENABLE_14W1S0hEnable (set) for intr_in[14]
13ENABLE_13W1S0hEnable (set) for intr_in[13]
12ENABLE_12W1S0hEnable (set) for intr_in[12]
11ENABLE_11W1S0hEnable (set) for intr_in[11]
10ENABLE_10W1S0hEnable (set) for intr_in[10]
9ENABLE_9W1S0hEnable (set) for intr_in[9]
8ENABLE_8W1S0hEnable (set) for intr_in[8]
7ENABLE_7W1S0hEnable (set) for intr_in[7]
6ENABLE_6W1S0hEnable (set) for intr_in[6]
5ENABLE_5W1S0hEnable (set) for intr_in[5]
4ENABLE_4W1S0hEnable (set) for intr_in[4]
3ENABLE_3W1S0hEnable (set) for intr_in[3]
2ENABLE_2W1S0hEnable (set) for intr_in[2]
1ENABLE_1W1S0hEnable (set) for intr_in[1]
0ENABLE_0W1S0hEnable (set) for intr_in[0]

4.14.7.23 ICSS_INTC_ENABLE_REG1 Register (Offset = 304h) [reset = 0h]

ICSS_INTC_ENABLE_REG1 is shown in Figure 6-424 and described in Table 6-829.

Return to Summary Table.

Enable Register 1

Table 6-828 ICSS_INTC_ENABLE_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0304h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0304h
Figure 6-424 ICSS_INTC_ENABLE_REG1 Register
3130292827262524
ENABLE_63ENABLE_62ENABLE_61ENABLE_60ENABLE_59ENABLE_58ENABLE_57ENABLE_56
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
ENABLE_55ENABLE_54ENABLE_53ENABLE_52ENABLE_51ENABLE_50ENABLE_49ENABLE_48
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
ENABLE_47ENABLE_46ENABLE_45ENABLE_44ENABLE_43ENABLE_42ENABLE_41ENABLE_40
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
ENABLE_39ENABLE_38ENABLE_37ENABLE_36ENABLE_35ENABLE_34ENABLE_33ENABLE_32
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-829 ICSS_INTC_ENABLE_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_63W1S0hEnable (set) for intr_in[63]
30ENABLE_62W1S0hEnable (set) for intr_in[62]
29ENABLE_61W1S0hEnable (set) for intr_in[61]
28ENABLE_60W1S0hEnable (set) for intr_in[60]
27ENABLE_59W1S0hEnable (set) for intr_in[59]
26ENABLE_58W1S0hEnable (set) for intr_in[58]
25ENABLE_57W1S0hEnable (set) for intr_in[57]
24ENABLE_56W1S0hEnable (set) for intr_in[56]
23ENABLE_55W1S0hEnable (set) for intr_in[55]
22ENABLE_54W1S0hEnable (set) for intr_in[54]
21ENABLE_53W1S0hEnable (set) for intr_in[53]
20ENABLE_52W1S0hEnable (set) for intr_in[52]
19ENABLE_51W1S0hEnable (set) for intr_in[51]
18ENABLE_50W1S0hEnable (set) for intr_in[50]
17ENABLE_49W1S0hEnable (set) for intr_in[49]
16ENABLE_48W1S0hEnable (set) for intr_in[48]
15ENABLE_47W1S0hEnable (set) for intr_in[47]
14ENABLE_46W1S0hEnable (set) for intr_in[46]
13ENABLE_45W1S0hEnable (set) for intr_in[45]
12ENABLE_44W1S0hEnable (set) for intr_in[44]
11ENABLE_43W1S0hEnable (set) for intr_in[43]
10ENABLE_42W1S0hEnable (set) for intr_in[42]
9ENABLE_41W1S0hEnable (set) for intr_in[41]
8ENABLE_40W1S0hEnable (set) for intr_in[40]
7ENABLE_39W1S0hEnable (set) for intr_in[39]
6ENABLE_38W1S0hEnable (set) for intr_in[38]
5ENABLE_37W1S0hEnable (set) for intr_in[37]
4ENABLE_36W1S0hEnable (set) for intr_in[36]
3ENABLE_35W1S0hEnable (set) for intr_in[35]
2ENABLE_34W1S0hEnable (set) for intr_in[34]
1ENABLE_33W1S0hEnable (set) for intr_in[33]
0ENABLE_32W1S0hEnable (set) for intr_in[32]

4.14.7.24 ICSS_INTC_ENABLE_REG2 Register (Offset = 308h) [reset = 0h]

ICSS_INTC_ENABLE_REG2 is shown in Figure 6-425 and described in Table 6-831.

Return to Summary Table.

Enable Register 2

Table 6-830 ICSS_INTC_ENABLE_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0308h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0308h
Figure 6-425 ICSS_INTC_ENABLE_REG2 Register
3130292827262524
ENABLE_95ENABLE_94ENABLE_93ENABLE_92ENABLE_91ENABLE_90ENABLE_89ENABLE_88
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
ENABLE_87ENABLE_86ENABLE_85ENABLE_84ENABLE_83ENABLE_82ENABLE_81ENABLE_80
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
ENABLE_79ENABLE_78ENABLE_77ENABLE_76ENABLE_75ENABLE_74ENABLE_73ENABLE_72
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
ENABLE_71ENABLE_70ENABLE_69ENABLE_68ENABLE_67ENABLE_66ENABLE_65ENABLE_64
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-831 ICSS_INTC_ENABLE_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_95W1S0hEnable (set) for slv_events_in[31]
30ENABLE_94W1S0hEnable (set) for slv_events_in[30]
29ENABLE_93W1S0hEnable (set) for slv_events_in[29]
28ENABLE_92W1S0hEnable (set) for slv_events_in[28]
27ENABLE_91W1S0hEnable (set) for slv_events_in[27]
26ENABLE_90W1S0hEnable (set) for slv_events_in[26]
25ENABLE_89W1S0hEnable (set) for slv_events_in[25]
24ENABLE_88W1S0hEnable (set) for slv_events_in[24]
23ENABLE_87W1S0hEnable (set) for slv_events_in[23]
22ENABLE_86W1S0hEnable (set) for slv_events_in[22]
21ENABLE_85W1S0hEnable (set) for slv_events_in[21]
20ENABLE_84W1S0hEnable (set) for slv_events_in[20]
19ENABLE_83W1S0hEnable (set) for slv_events_in[19]
18ENABLE_82W1S0hEnable (set) for slv_events_in[18]
17ENABLE_81W1S0hEnable (set) for slv_events_in[17]
16ENABLE_80W1S0hEnable (set) for slv_events_in[16]
15ENABLE_79W1S0hEnable (set) for slv_events_in[15]
14ENABLE_78W1S0hEnable (set) for slv_events_in[14]
13ENABLE_77W1S0hEnable (set) for slv_events_in[13]
12ENABLE_76W1S0hEnable (set) for slv_events_in[12]
11ENABLE_75W1S0hEnable (set) for slv_events_in[11]
10ENABLE_74W1S0hEnable (set) for slv_events_in[10]
9ENABLE_73W1S0hEnable (set) for slv_events_in[9]
8ENABLE_72W1S0hEnable (set) for slv_events_in[8]
7ENABLE_71W1S0hEnable (set) for slv_events_in[7]
6ENABLE_70W1S0hEnable (set) for slv_events_in[6]
5ENABLE_69W1S0hEnable (set) for slv_events_in[5]
4ENABLE_68W1S0hEnable (set) for slv_events_in[4]
3ENABLE_67W1S0hEnable (set) for slv_events_in[3]
2ENABLE_66W1S0hEnable (set) for slv_events_in[2]
1ENABLE_65W1S0hEnable (set) for slv_events_in[1]
0ENABLE_64W1S0hEnable (set) for slv_events_in[0]

4.14.7.25 ICSS_INTC_ENABLE_REG3 Register (Offset = 30Ch) [reset = 0h]

ICSS_INTC_ENABLE_REG3 is shown in Figure 6-426 and described in Table 6-833.

Return to Summary Table.

Enable Register 3

Table 6-832 ICSS_INTC_ENABLE_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 030Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 030Ch
Figure 6-426 ICSS_INTC_ENABLE_REG3 Register
3130292827262524
ENABLE_127ENABLE_126ENABLE_125ENABLE_124ENABLE_123ENABLE_122ENABLE_121ENABLE_120
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
ENABLE_119ENABLE_118ENABLE_117ENABLE_116ENABLE_115ENABLE_114ENABLE_113ENABLE_112
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
ENABLE_111ENABLE_110ENABLE_109ENABLE_108ENABLE_107ENABLE_106ENABLE_105ENABLE_104
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
ENABLE_103ENABLE_102ENABLE_101ENABLE_100ENABLE_99ENABLE_98ENABLE_97ENABLE_96
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-833 ICSS_INTC_ENABLE_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_127W1S0hEnable (set) for slv_events_in[63]
30ENABLE_126W1S0hEnable (set) for slv_events_in[62]
29ENABLE_125W1S0hEnable (set) for slv_events_in[61]
28ENABLE_124W1S0hEnable (set) for slv_events_in[60]
27ENABLE_123W1S0hEnable (set) for slv_events_in[59]
26ENABLE_122W1S0hEnable (set) for slv_events_in[58]
25ENABLE_121W1S0hEnable (set) for slv_events_in[57]
24ENABLE_120W1S0hEnable (set) for slv_events_in[56]
23ENABLE_119W1S0hEnable (set) for slv_events_in[55]
22ENABLE_118W1S0hEnable (set) for slv_events_in[54]
21ENABLE_117W1S0hEnable (set) for slv_events_in[53]
20ENABLE_116W1S0hEnable (set) for slv_events_in[52]
19ENABLE_115W1S0hEnable (set) for slv_events_in[51]
18ENABLE_114W1S0hEnable (set) for slv_events_in[50]
17ENABLE_113W1S0hEnable (set) for slv_events_in[49]
16ENABLE_112W1S0hEnable (set) for slv_events_in[48]
15ENABLE_111W1S0hEnable (set) for slv_events_in[47]
14ENABLE_110W1S0hEnable (set) for slv_events_in[46]
13ENABLE_109W1S0hEnable (set) for slv_events_in[45]
12ENABLE_108W1S0hEnable (set) for slv_events_in[44]
11ENABLE_107W1S0hEnable (set) for slv_events_in[43]
10ENABLE_106W1S0hEnable (set) for slv_events_in[42]
9ENABLE_105W1S0hEnable (set) for slv_events_in[41]
8ENABLE_104W1S0hEnable (set) for slv_events_in[40]
7ENABLE_103W1S0hEnable (set) for slv_events_in[39]
6ENABLE_102W1S0hEnable (set) for slv_events_in[38]
5ENABLE_101W1S0hEnable (set) for slv_events_in[37]
4ENABLE_100W1S0hEnable (set) for slv_events_in[36]
3ENABLE_99W1S0hEnable (set) for slv_events_in[35]
2ENABLE_98W1S0hEnable (set) for slv_events_in[34]
1ENABLE_97W1S0hEnable (set) for slv_events_in[33]
0ENABLE_96W1S0hEnable (set) for slv_events_in[32]

4.14.7.26 ICSS_INTC_ENABLE_REG4 Register (Offset = 310h) [reset = 0h]

ICSS_INTC_ENABLE_REG4 is shown in Figure 6-427 and described in Table 6-835.

Return to Summary Table.

Enable Register 4

Table 6-834 ICSS_INTC_ENABLE_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0310h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0310h
Figure 6-427 ICSS_INTC_ENABLE_REG4 Register
3130292827262524
ENABLE_159ENABLE_158ENABLE_157ENABLE_156ENABLE_155ENABLE_154ENABLE_153ENABLE_152
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
2322212019181716
ENABLE_151ENABLE_150ENABLE_149ENABLE_148ENABLE_147ENABLE_146ENABLE_145ENABLE_144
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
15141312111098
ENABLE_143ENABLE_142ENABLE_141ENABLE_140ENABLE_139ENABLE_138ENABLE_137ENABLE_136
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
76543210
ENABLE_135ENABLE_134ENABLE_133ENABLE_132ENABLE_131ENABLE_130ENABLE_129ENABLE_128
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 6-835 ICSS_INTC_ENABLE_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_159W1S0hEnable (set) for slv_events_in[95]
30ENABLE_158W1S0hEnable (set) for slv_events_in[94]
29ENABLE_157W1S0hEnable (set) for slv_events_in[93]
28ENABLE_156W1S0hEnable (set) for slv_events_in[92]
27ENABLE_155W1S0hEnable (set) for slv_events_in[91]
26ENABLE_154W1S0hEnable (set) for slv_events_in[90]
25ENABLE_153W1S0hEnable (set) for slv_events_in[89]
24ENABLE_152W1S0hEnable (set) for slv_events_in[88]
23ENABLE_151W1S0hEnable (set) for slv_events_in[87]
22ENABLE_150W1S0hEnable (set) for slv_events_in[86]
21ENABLE_149W1S0hEnable (set) for slv_events_in[85]
20ENABLE_148W1S0hEnable (set) for slv_events_in[84]
19ENABLE_147W1S0hEnable (set) for slv_events_in[83]
18ENABLE_146W1S0hEnable (set) for slv_events_in[82]
17ENABLE_145W1S0hEnable (set) for slv_events_in[81]
16ENABLE_144W1S0hEnable (set) for slv_events_in[80]
15ENABLE_143W1S0hEnable (set) for slv_events_in[79]
14ENABLE_142W1S0hEnable (set) for slv_events_in[78]
13ENABLE_141W1S0hEnable (set) for slv_events_in[77]
12ENABLE_140W1S0hEnable (set) for slv_events_in[76]
11ENABLE_139W1S0hEnable (set) for slv_events_in[75]
10ENABLE_138W1S0hEnable (set) for slv_events_in[74]
9ENABLE_137W1S0hEnable (set) for slv_events_in[73]
8ENABLE_136W1S0hEnable (set) for slv_events_in[72]
7ENABLE_135W1S0hEnable (set) for slv_events_in[71]
6ENABLE_134W1S0hEnable (set) for slv_events_in[70]
5ENABLE_133W1S0hEnable (set) for slv_events_in[69]
4ENABLE_132W1S0hEnable (set) for slv_events_in[68]
3ENABLE_131W1S0hEnable (set) for slv_events_in[67]
2ENABLE_130W1S0hEnable (set) for slv_events_in[66]
1ENABLE_129W1S0hEnable (set) for slv_events_in[65]
0ENABLE_128W1S0hEnable (set) for slv_events_in[64]

4.14.7.27 ICSS_INTC_ENABLE_CLR_REG0 Register (Offset = 380h) [reset = 0h]

ICSS_INTC_ENABLE_CLR_REG0 is shown in Figure 6-428 and described in Table 6-837.

Return to Summary Table.

Enable Clear Register 0

Table 6-836 ICSS_INTC_ENABLE_CLR_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0380h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0380h
Figure 6-428 ICSS_INTC_ENABLE_CLR_REG0 Register
3130292827262524
ENABLE_31_CLRENABLE_30_CLRENABLE_29_CLRENABLE_28_CLRENABLE_27_CLRENABLE_26_CLRENABLE_25_CLRENABLE_24_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENABLE_23_CLRENABLE_22_CLRENABLE_21_CLRENABLE_20_CLRENABLE_19_CLRENABLE_18_CLRENABLE_17_CLRENABLE_16_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENABLE_15_CLRENABLE_14_CLRENABLE_13_CLRENABLE_12_CLRENABLE_11_CLRENABLE_10_CLRENABLE_9_CLRENABLE_8_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENABLE_7_CLRENABLE_6_CLRENABLE_5_CLRENABLE_4_CLRENABLE_3_CLRENABLE_2_CLRENABLE_1_CLRENABLE_0_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-837 ICSS_INTC_ENABLE_CLR_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_31_CLRW1C0hEnable clear for intr_in[31]
30ENABLE_30_CLRW1C0hEnable clear for intr_in[30]
29ENABLE_29_CLRW1C0hEnable clear for intr_in[29]
28ENABLE_28_CLRW1C0hEnable clear for intr_in[28]
27ENABLE_27_CLRW1C0hEnable clear for intr_in[27]
26ENABLE_26_CLRW1C0hEnable clear for intr_in[26]
25ENABLE_25_CLRW1C0hEnable clear for intr_in[25]
24ENABLE_24_CLRW1C0hEnable clear for intr_in[24]
23ENABLE_23_CLRW1C0hEnable clear for intr_in[23]
22ENABLE_22_CLRW1C0hEnable clear for intr_in[22]
21ENABLE_21_CLRW1C0hEnable clear for intr_in[21]
20ENABLE_20_CLRW1C0hEnable clear for intr_in[20]
19ENABLE_19_CLRW1C0hEnable clear for intr_in[19]
18ENABLE_18_CLRW1C0hEnable clear for intr_in[18]
17ENABLE_17_CLRW1C0hEnable clear for intr_in[17]
16ENABLE_16_CLRW1C0hEnable clear for intr_in[16]
15ENABLE_15_CLRW1C0hEnable clear for intr_in[15]
14ENABLE_14_CLRW1C0hEnable clear for intr_in[14]
13ENABLE_13_CLRW1C0hEnable clear for intr_in[13]
12ENABLE_12_CLRW1C0hEnable clear for intr_in[12]
11ENABLE_11_CLRW1C0hEnable clear for intr_in[11]
10ENABLE_10_CLRW1C0hEnable clear for intr_in[10]
9ENABLE_9_CLRW1C0hEnable clear for intr_in[9]
8ENABLE_8_CLRW1C0hEnable clear for intr_in[8]
7ENABLE_7_CLRW1C0hEnable clear for intr_in[7]
6ENABLE_6_CLRW1C0hEnable clear for intr_in[6]
5ENABLE_5_CLRW1C0hEnable clear for intr_in[5]
4ENABLE_4_CLRW1C0hEnable clear for intr_in[4]
3ENABLE_3_CLRW1C0hEnable clear for intr_in[3]
2ENABLE_2_CLRW1C0hEnable clear for intr_in[2]
1ENABLE_1_CLRW1C0hEnable clear for intr_in[1]
0ENABLE_0_CLRW1C0hEnable clear for intr_in[0]

4.14.7.28 ICSS_INTC_ENABLE_CLR_REG1 Register (Offset = 384h) [reset = 0h]

ICSS_INTC_ENABLE_CLR_REG1 is shown in Figure 6-429 and described in Table 6-839.

Return to Summary Table.

Enable Clear Register 1

Table 6-838 ICSS_INTC_ENABLE_CLR_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0384h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0384h
Figure 6-429 ICSS_INTC_ENABLE_CLR_REG1 Register
3130292827262524
ENABLE_63_CLRENABLE_62_CLRENABLE_61_CLRENABLE_60_CLRENABLE_59_CLRENABLE_58_CLRENABLE_57_CLRENABLE_56_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENABLE_55_CLRENABLE_54_CLRENABLE_53_CLRENABLE_52_CLRENABLE_51_CLRENABLE_50_CLRENABLE_49_CLRENABLE_48_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENABLE_47_CLRENABLE_46_CLRENABLE_45_CLRENABLE_44_CLRENABLE_43_CLRENABLE_42_CLRENABLE_41_CLRENABLE_40_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENABLE_39_CLRENABLE_38_CLRENABLE_37_CLRENABLE_36_CLRENABLE_35_CLRENABLE_34_CLRENABLE_33_CLRENABLE_32_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-839 ICSS_INTC_ENABLE_CLR_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_63_CLRW1C0hEnable clear for intr_in[63]
30ENABLE_62_CLRW1C0hEnable clear for intr_in[62]
29ENABLE_61_CLRW1C0hEnable clear for intr_in[61]
28ENABLE_60_CLRW1C0hEnable clear for intr_in[60]
27ENABLE_59_CLRW1C0hEnable clear for intr_in[59]
26ENABLE_58_CLRW1C0hEnable clear for intr_in[58]
25ENABLE_57_CLRW1C0hEnable clear for intr_in[57]
24ENABLE_56_CLRW1C0hEnable clear for intr_in[56]
23ENABLE_55_CLRW1C0hEnable clear for intr_in[55]
22ENABLE_54_CLRW1C0hEnable clear for intr_in[54]
21ENABLE_53_CLRW1C0hEnable clear for intr_in[53]
20ENABLE_52_CLRW1C0hEnable clear for intr_in[52]
19ENABLE_51_CLRW1C0hEnable clear for intr_in[51]
18ENABLE_50_CLRW1C0hEnable clear for intr_in[50]
17ENABLE_49_CLRW1C0hEnable clear for intr_in[49]
16ENABLE_48_CLRW1C0hEnable clear for intr_in[48]
15ENABLE_47_CLRW1C0hEnable clear for intr_in[47]
14ENABLE_46_CLRW1C0hEnable clear for intr_in[46]
13ENABLE_45_CLRW1C0hEnable clear for intr_in[45]
12ENABLE_44_CLRW1C0hEnable clear for intr_in[44]
11ENABLE_43_CLRW1C0hEnable clear for intr_in[43]
10ENABLE_42_CLRW1C0hEnable clear for intr_in[42]
9ENABLE_41_CLRW1C0hEnable clear for intr_in[41]
8ENABLE_40_CLRW1C0hEnable clear for intr_in[40]
7ENABLE_39_CLRW1C0hEnable clear for intr_in[39]
6ENABLE_38_CLRW1C0hEnable clear for intr_in[38]
5ENABLE_37_CLRW1C0hEnable clear for intr_in[37]
4ENABLE_36_CLRW1C0hEnable clear for intr_in[36]
3ENABLE_35_CLRW1C0hEnable clear for intr_in[35]
2ENABLE_34_CLRW1C0hEnable clear for intr_in[34]
1ENABLE_33_CLRW1C0hEnable clear for intr_in[33]
0ENABLE_32_CLRW1C0hEnable clear for intr_in[32]

4.14.7.29 ICSS_INTC_ENABLE_CLR_REG2 Register (Offset = 388h) [reset = 0h]

ICSS_INTC_ENABLE_CLR_REG2 is shown in Figure 6-430 and described in Table 6-841.

Return to Summary Table.

Enable Clear Register 2

Table 6-840 ICSS_INTC_ENABLE_CLR_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0388h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0388h
Figure 6-430 ICSS_INTC_ENABLE_CLR_REG2 Register
3130292827262524
ENABLE_95_CLRENABLE_94_CLRENABLE_93_CLRENABLE_92_CLRENABLE_91_CLRENABLE_90_CLRENABLE_89_CLRENABLE_88_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENABLE_87_CLRENABLE_86_CLRENABLE_85_CLRENABLE_84_CLRENABLE_83_CLRENABLE_82_CLRENABLE_81_CLRENABLE_80_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENABLE_79_CLRENABLE_78_CLRENABLE_77_CLRENABLE_76_CLRENABLE_75_CLRENABLE_74_CLRENABLE_73_CLRENABLE_72_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENABLE_71_CLRENABLE_70_CLRENABLE_69_CLRENABLE_68_CLRENABLE_67_CLRENABLE_66_CLRENABLE_65_CLRENABLE_64_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-841 ICSS_INTC_ENABLE_CLR_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_95_CLRW1C0hEnable clear for slv_events_in[31]
30ENABLE_94_CLRW1C0hEnable clear for slv_events_in[30]
29ENABLE_93_CLRW1C0hEnable clear for slv_events_in[29]
28ENABLE_92_CLRW1C0hEnable clear for slv_events_in[28]
27ENABLE_91_CLRW1C0hEnable clear for slv_events_in[27]
26ENABLE_90_CLRW1C0hEnable clear for slv_events_in[26]
25ENABLE_89_CLRW1C0hEnable clear for slv_events_in[25]
24ENABLE_88_CLRW1C0hEnable clear for slv_events_in[24]
23ENABLE_87_CLRW1C0hEnable clear for slv_events_in[23]
22ENABLE_86_CLRW1C0hEnable clear for slv_events_in[22]
21ENABLE_85_CLRW1C0hEnable clear for slv_events_in[21]
20ENABLE_84_CLRW1C0hEnable clear for slv_events_in[20]
19ENABLE_83_CLRW1C0hEnable clear for slv_events_in[19]
18ENABLE_82_CLRW1C0hEnable clear for slv_events_in[18]
17ENABLE_81_CLRW1C0hEnable clear for slv_events_in[17]
16ENABLE_80_CLRW1C0hEnable clear for slv_events_in[16]
15ENABLE_79_CLRW1C0hEnable clear for slv_events_in[15]
14ENABLE_78_CLRW1C0hEnable clear for slv_events_in[14]
13ENABLE_77_CLRW1C0hEnable clear for slv_events_in[13]
12ENABLE_76_CLRW1C0hEnable clear for slv_events_in[12]
11ENABLE_75_CLRW1C0hEnable clear for slv_events_in[11]
10ENABLE_74_CLRW1C0hEnable clear for slv_events_in[10]
9ENABLE_73_CLRW1C0hEnable clear for slv_events_in[9]
8ENABLE_72_CLRW1C0hEnable clear for slv_events_in[8]
7ENABLE_71_CLRW1C0hEnable clear for slv_events_in[7]
6ENABLE_70_CLRW1C0hEnable clear for slv_events_in[6]
5ENABLE_69_CLRW1C0hEnable clear for slv_events_in[5]
4ENABLE_68_CLRW1C0hEnable clear for slv_events_in[4]
3ENABLE_67_CLRW1C0hEnable clear for slv_events_in[3]
2ENABLE_66_CLRW1C0hEnable clear for slv_events_in[2]
1ENABLE_65_CLRW1C0hEnable clear for slv_events_in[1]
0ENABLE_64_CLRW1C0hEnable clear for slv_events_in[0]

4.14.7.30 ICSS_INTC_ENABLE_CLR_REG3 Register (Offset = 38Ch) [reset = 0h]

ICSS_INTC_ENABLE_CLR_REG3 is shown in Figure 6-431 and described in Table 6-843.

Return to Summary Table.

Enable Clear Register 3

Table 6-842 ICSS_INTC_ENABLE_CLR_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 038Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 038Ch
Figure 6-431 ICSS_INTC_ENABLE_CLR_REG3 Register
3130292827262524
ENABLE_127_CLRENABLE_126_CLRENABLE_125_CLRENABLE_124_CLRENABLE_123_CLRENABLE_122_CLRENABLE_121_CLRENABLE_120_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENABLE_119_CLRENABLE_118_CLRENABLE_117_CLRENABLE_116_CLRENABLE_115_CLRENABLE_114_CLRENABLE_113_CLRENABLE_112_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENABLE_111_CLRENABLE_110_CLRENABLE_109_CLRENABLE_108_CLRENABLE_107_CLRENABLE_106_CLRENABLE_105_CLRENABLE_104_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENABLE_103_CLRENABLE_102_CLRENABLE_101_CLRENABLE_100_CLRENABLE_99_CLRENABLE_98_CLRENABLE_97_CLRENABLE_96_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-843 ICSS_INTC_ENABLE_CLR_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_127_CLRW1C0hEnable clear for slv_events_in[63]
30ENABLE_126_CLRW1C0hEnable clear for slv_events_in[62]
29ENABLE_125_CLRW1C0hEnable clear for slv_events_in[61]
28ENABLE_124_CLRW1C0hEnable clear for slv_events_in[60]
27ENABLE_123_CLRW1C0hEnable clear for slv_events_in[59]
26ENABLE_122_CLRW1C0hEnable clear for slv_events_in[58]
25ENABLE_121_CLRW1C0hEnable clear for slv_events_in[57]
24ENABLE_120_CLRW1C0hEnable clear for slv_events_in[56]
23ENABLE_119_CLRW1C0hEnable clear for slv_events_in[55]
22ENABLE_118_CLRW1C0hEnable clear for slv_events_in[54]
21ENABLE_117_CLRW1C0hEnable clear for slv_events_in[53]
20ENABLE_116_CLRW1C0hEnable clear for slv_events_in[52]
19ENABLE_115_CLRW1C0hEnable clear for slv_events_in[51]
18ENABLE_114_CLRW1C0hEnable clear for slv_events_in[50]
17ENABLE_113_CLRW1C0hEnable clear for slv_events_in[49]
16ENABLE_112_CLRW1C0hEnable clear for slv_events_in[48]
15ENABLE_111_CLRW1C0hEnable clear for slv_events_in[47]
14ENABLE_110_CLRW1C0hEnable clear for slv_events_in[46]
13ENABLE_109_CLRW1C0hEnable clear for slv_events_in[45]
12ENABLE_108_CLRW1C0hEnable clear for slv_events_in[44]
11ENABLE_107_CLRW1C0hEnable clear for slv_events_in[43]
10ENABLE_106_CLRW1C0hEnable clear for slv_events_in[42]
9ENABLE_105_CLRW1C0hEnable clear for slv_events_in[41]
8ENABLE_104_CLRW1C0hEnable clear for slv_events_in[40]
7ENABLE_103_CLRW1C0hEnable clear for slv_events_in[39]
6ENABLE_102_CLRW1C0hEnable clear for slv_events_in[38]
5ENABLE_101_CLRW1C0hEnable clear for slv_events_in[37]
4ENABLE_100_CLRW1C0hEnable clear for slv_events_in[36]
3ENABLE_99_CLRW1C0hEnable clear for slv_events_in[35]
2ENABLE_98_CLRW1C0hEnable clear for slv_events_in[34]
1ENABLE_97_CLRW1C0hEnable clear for slv_events_in[33]
0ENABLE_96_CLRW1C0hEnable clear for slv_events_in[32]

4.14.7.31 ICSS_INTC_ENABLE_CLR_REG4 Register (Offset = 390h) [reset = 0h]

ICSS_INTC_ENABLE_CLR_REG4 is shown in Figure 6-432 and described in Table 6-845.

Return to Summary Table.

Enable Clear Register 4

Table 6-844 ICSS_INTC_ENABLE_CLR_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0390h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0390h
Figure 6-432 ICSS_INTC_ENABLE_CLR_REG4 Register
3130292827262524
ENABLE_159_CLRENABLE_158_CLRENABLE_157_CLRENABLE_156_CLRENABLE_155_CLRENABLE_154_CLRENABLE_153_CLRENABLE_152_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
2322212019181716
ENABLE_151_CLRENABLE_150_CLRENABLE_149_CLRENABLE_148_CLRENABLE_147_CLRENABLE_146_CLRENABLE_145_CLRENABLE_144_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
15141312111098
ENABLE_143_CLRENABLE_142_CLRENABLE_141_CLRENABLE_140_CLRENABLE_139_CLRENABLE_138_CLRENABLE_137_CLRENABLE_136_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
ENABLE_135_CLRENABLE_134_CLRENABLE_133_CLRENABLE_132_CLRENABLE_131_CLRENABLE_130_CLRENABLE_129_CLRENABLE_128_CLR
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: W1C = Write 1 to Clear Bit; -n = value after reset
Table 6-845 ICSS_INTC_ENABLE_CLR_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31ENABLE_159_CLRW1C0hEnable clear for slv_events_in[95]
30ENABLE_158_CLRW1C0hEnable clear for slv_events_in[94]
29ENABLE_157_CLRW1C0hEnable clear for slv_events_in[93]
28ENABLE_156_CLRW1C0hEnable clear for slv_events_in[92]
27ENABLE_155_CLRW1C0hEnable clear for slv_events_in[91]
26ENABLE_154_CLRW1C0hEnable clear for slv_events_in[90]
25ENABLE_153_CLRW1C0hEnable clear for slv_events_in[89]
24ENABLE_152_CLRW1C0hEnable clear for slv_events_in[88]
23ENABLE_151_CLRW1C0hEnable clear for slv_events_in[87]
22ENABLE_150_CLRW1C0hEnable clear for slv_events_in[86]
21ENABLE_149_CLRW1C0hEnable clear for slv_events_in[85]
20ENABLE_148_CLRW1C0hEnable clear for slv_events_in[84]
19ENABLE_147_CLRW1C0hEnable clear for slv_events_in[83]
18ENABLE_146_CLRW1C0hEnable clear for slv_events_in[82]
17ENABLE_145_CLRW1C0hEnable clear for slv_events_in[81]
16ENABLE_144_CLRW1C0hEnable clear for slv_events_in[80]
15ENABLE_143_CLRW1C0hEnable clear for slv_events_in[79]
14ENABLE_142_CLRW1C0hEnable clear for slv_events_in[78]
13ENABLE_141_CLRW1C0hEnable clear for slv_events_in[77]
12ENABLE_140_CLRW1C0hEnable clear for slv_events_in[76]
11ENABLE_139_CLRW1C0hEnable clear for slv_events_in[75]
10ENABLE_138_CLRW1C0hEnable clear for slv_events_in[74]
9ENABLE_137_CLRW1C0hEnable clear for slv_events_in[73]
8ENABLE_136_CLRW1C0hEnable clear for slv_events_in[72]
7ENABLE_135_CLRW1C0hEnable clear for slv_events_in[71]
6ENABLE_134_CLRW1C0hEnable clear for slv_events_in[70]
5ENABLE_133_CLRW1C0hEnable clear for slv_events_in[69]
4ENABLE_132_CLRW1C0hEnable clear for slv_events_in[68]
3ENABLE_131_CLRW1C0hEnable clear for slv_events_in[67]
2ENABLE_130_CLRW1C0hEnable clear for slv_events_in[66]
1ENABLE_129_CLRW1C0hEnable clear for slv_events_in[65]
0ENABLE_128_CLRW1C0hEnable clear for slv_events_in[64]

4.14.7.32 ICSS_INTC_CH_MAP_REG0 Register (Offset = 400h) [reset = X]

ICSS_INTC_CH_MAP_REG0 is shown in Figure 6-433 and described in Table 6-847.

Return to Summary Table.

Interrupt Channel Map Register for 0 to 0+3

Table 6-846 ICSS_INTC_CH_MAP_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0400h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0400h
Figure 6-433 ICSS_INTC_CH_MAP_REG0 Register
31302928272625242322212019181716
RESERVEDCH_MAP_3RESERVEDCH_MAP_2
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_1RESERVEDCH_MAP_0
R/W-XR/W-0hR/W-XW-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-847 ICSS_INTC_CH_MAP_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_3R/W0hInterrupt Channel Map for intr_in[3]
23-21RESERVEDR/WX
20-16CH_MAP_2R/W0hInterrupt Channel Map for intr_in[2]
15-13RESERVEDR/WX
12-8CH_MAP_1R/W0hInterrupt Channel Map for intr_in[1]
7-5RESERVEDR/WX
4-0CH_MAP_0W0hInterrupt Channel Map for intr_in[0]

4.14.7.33 ICSS_INTC_CH_MAP_REG1 Register (Offset = 404h) [reset = X]

ICSS_INTC_CH_MAP_REG1 is shown in Figure 6-434 and described in Table 6-849.

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Interrupt Channel Map Register for 4 to 4+3

Table 6-848 ICSS_INTC_CH_MAP_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0404h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0404h
Figure 6-434 ICSS_INTC_CH_MAP_REG1 Register
31302928272625242322212019181716
RESERVEDCH_MAP_7RESERVEDCH_MAP_6
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_5RESERVEDCH_MAP_4
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-849 ICSS_INTC_CH_MAP_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_7R/W0hInterrupt Channel Map for intr_in[7]
23-21RESERVEDR/WX
20-16CH_MAP_6R/W0hInterrupt Channel Map for intr_in[6]
15-13RESERVEDR/WX
12-8CH_MAP_5R/W0hInterrupt Channel Map for intr_in[5]
7-5RESERVEDR/WX
4-0CH_MAP_4R/W0hInterrupt Channel Map for intr_in[4]

4.14.7.34 ICSS_INTC_CH_MAP_REG2 Register (Offset = 408h) [reset = X]

ICSS_INTC_CH_MAP_REG2 is shown in Figure 6-435 and described in Table 6-851.

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Interrupt Channel Map Register for 8 to 8+3

Table 6-850 ICSS_INTC_CH_MAP_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0408h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0408h
Figure 6-435 ICSS_INTC_CH_MAP_REG2 Register
31302928272625242322212019181716
RESERVEDCH_MAP_11RESERVEDCH_MAP_10
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_9RESERVEDCH_MAP_8
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-851 ICSS_INTC_CH_MAP_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_11R/W0hInterrupt Channel Map for intr_in[11]
23-21RESERVEDR/WX
20-16CH_MAP_10R/W0hInterrupt Channel Map for intr_in[10]
15-13RESERVEDR/WX
12-8CH_MAP_9R/W0hInterrupt Channel Map for intr_in[9]
7-5RESERVEDR/WX
4-0CH_MAP_8R/W0hInterrupt Channel Map for intr_in[8]

4.14.7.35 ICSS_INTC_CH_MAP_REG3 Register (Offset = 40Ch) [reset = X]

ICSS_INTC_CH_MAP_REG3 is shown in Figure 6-436 and described in Table 6-853.

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Interrupt Channel Map Register for 12 to 12+3

Table 6-852 ICSS_INTC_CH_MAP_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 040Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 040Ch
Figure 6-436 ICSS_INTC_CH_MAP_REG3 Register
31302928272625242322212019181716
RESERVEDCH_MAP_15RESERVEDCH_MAP_14
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_13RESERVEDCH_MAP_12
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-853 ICSS_INTC_CH_MAP_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_15R/W0hInterrupt Channel Map for intr_in[15]
23-21RESERVEDR/WX
20-16CH_MAP_14R/W0hInterrupt Channel Map for intr_in[14]
15-13RESERVEDR/WX
12-8CH_MAP_13R/W0hInterrupt Channel Map for intr_in[13]
7-5RESERVEDR/WX
4-0CH_MAP_12R/W0hInterrupt Channel Map for intr_in[12]

4.14.7.36 ICSS_INTC_CH_MAP_REG4 Register (Offset = 410h) [reset = X]

ICSS_INTC_CH_MAP_REG4 is shown in Figure 6-437 and described in Table 6-855.

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Interrupt Channel Map Register for 16 to 16+3

Table 6-854 ICSS_INTC_CH_MAP_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0410h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0410h
Figure 6-437 ICSS_INTC_CH_MAP_REG4 Register
31302928272625242322212019181716
RESERVEDCH_MAP_19RESERVEDCH_MAP_18
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_17RESERVEDCH_MAP_16
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-855 ICSS_INTC_CH_MAP_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_19R/W0hInterrupt Channel Map for intr_in[19]
23-21RESERVEDR/WX
20-16CH_MAP_18R/W0hInterrupt Channel Map for intr_in[18]
15-13RESERVEDR/WX
12-8CH_MAP_17R/W0hInterrupt Channel Map for intr_in[17]
7-5RESERVEDR/WX
4-0CH_MAP_16R/W0hInterrupt Channel Map for intr_in[16]

4.14.7.37 ICSS_INTC_CH_MAP_REG5 Register (Offset = 414h) [reset = X]

ICSS_INTC_CH_MAP_REG5 is shown in Figure 6-438 and described in Table 6-857.

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Interrupt Channel Map Register for 20 to 20+3

Table 6-856 ICSS_INTC_CH_MAP_REG5 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0414h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0414h
Figure 6-438 ICSS_INTC_CH_MAP_REG5 Register
31302928272625242322212019181716
RESERVEDCH_MAP_23RESERVEDCH_MAP_22
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_21RESERVEDCH_MAP_20
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-857 ICSS_INTC_CH_MAP_REG5 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_23R/W0hInterrupt Channel Map for intr_in[23]
23-21RESERVEDR/WX
20-16CH_MAP_22R/W0hInterrupt Channel Map for intr_in[22]
15-13RESERVEDR/WX
12-8CH_MAP_21R/W0hInterrupt Channel Map for intr_in[21]
7-5RESERVEDR/WX
4-0CH_MAP_20R/W0hInterrupt Channel Map for intr_in[20]

4.14.7.38 ICSS_INTC_CH_MAP_REG6 Register (Offset = 418h) [reset = X]

ICSS_INTC_CH_MAP_REG6 is shown in Figure 6-439 and described in Table 6-859.

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Interrupt Channel Map Register for 24 to 24+3

Table 6-858 ICSS_INTC_CH_MAP_REG6 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0418h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0418h
Figure 6-439 ICSS_INTC_CH_MAP_REG6 Register
31302928272625242322212019181716
RESERVEDCH_MAP_27RESERVEDCH_MAP_26
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_25RESERVEDCH_MAP_24
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-859 ICSS_INTC_CH_MAP_REG6 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_27R/W0hInterrupt Channel Map for intr_in[27]
23-21RESERVEDR/WX
20-16CH_MAP_26R/W0hInterrupt Channel Map for intr_in[26]
15-13RESERVEDR/WX
12-8CH_MAP_25R/W0hInterrupt Channel Map for intr_in[25]
7-5RESERVEDR/WX
4-0CH_MAP_24R/W0hInterrupt Channel Map for intr_in[24]

4.14.7.39 ICSS_INTC_CH_MAP_REG7 Register (Offset = 41Ch) [reset = X]

ICSS_INTC_CH_MAP_REG7 is shown in Figure 6-440 and described in Table 6-861.

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Interrupt Channel Map Register for 28 to 28+3

Table 6-860 ICSS_INTC_CH_MAP_REG7 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 041Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 041Ch
Figure 6-440 ICSS_INTC_CH_MAP_REG7 Register
31302928272625242322212019181716
RESERVEDCH_MAP_31RESERVEDCH_MAP_30
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_29RESERVEDCH_MAP_28
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-861 ICSS_INTC_CH_MAP_REG7 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_31R/W0hInterrupt Channel Map for intr_in[31]
23-21RESERVEDR/WX
20-16CH_MAP_30R/W0hInterrupt Channel Map for intr_in[30]
15-13RESERVEDR/WX
12-8CH_MAP_29R/W0hInterrupt Channel Map for intr_in[29]
7-5RESERVEDR/WX
4-0CH_MAP_28R/W0hInterrupt Channel Map for intr_in[28]

4.14.7.40 ICSS_INTC_CH_MAP_REG8 Register (Offset = 420h) [reset = X]

ICSS_INTC_CH_MAP_REG8 is shown in Figure 6-441 and described in Table 6-863.

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Interrupt Channel Map Register for 32 to 32+3

Table 6-862 ICSS_INTC_CH_MAP_REG8 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0420h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0420h
Figure 6-441 ICSS_INTC_CH_MAP_REG8 Register
31302928272625242322212019181716
RESERVEDCH_MAP_35RESERVEDCH_MAP_34
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_33RESERVEDCH_MAP_32
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-863 ICSS_INTC_CH_MAP_REG8 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_35R/W0hInterrupt Channel Map for intr_in[35]
23-21RESERVEDR/WX
20-16CH_MAP_34R/W0hInterrupt Channel Map for intr_in[34]
15-13RESERVEDR/WX
12-8CH_MAP_33R/W0hInterrupt Channel Map for intr_in[33]
7-5RESERVEDR/WX
4-0CH_MAP_32R/W0hInterrupt Channel Map for intr_in[32]

4.14.7.41 ICSS_INTC_CH_MAP_REG9 Register (Offset = 424h) [reset = X]

ICSS_INTC_CH_MAP_REG9 is shown in Figure 6-442 and described in Table 6-865.

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Interrupt Channel Map Register for 36 to 36+3

Table 6-864 ICSS_INTC_CH_MAP_REG9 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0424h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0424h
Figure 6-442 ICSS_INTC_CH_MAP_REG9 Register
31302928272625242322212019181716
RESERVEDCH_MAP_39RESERVEDCH_MAP_38
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_37RESERVEDCH_MAP_36
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-865 ICSS_INTC_CH_MAP_REG9 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_39R/W0hInterrupt Channel Map for intr_in[39]
23-21RESERVEDR/WX
20-16CH_MAP_38R/W0hInterrupt Channel Map for intr_in[38]
15-13RESERVEDR/WX
12-8CH_MAP_37R/W0hInterrupt Channel Map for intr_in[37]
7-5RESERVEDR/WX
4-0CH_MAP_36R/W0hInterrupt Channel Map for intr_in[36]

4.14.7.42 ICSS_INTC_CH_MAP_REG10 Register (Offset = 428h) [reset = X]

ICSS_INTC_CH_MAP_REG10 is shown in Figure 6-443 and described in Table 6-867.

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Interrupt Channel Map Register for 40 to 40+3

Table 6-866 ICSS_INTC_CH_MAP_REG10 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0428h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0428h
Figure 6-443 ICSS_INTC_CH_MAP_REG10 Register
31302928272625242322212019181716
RESERVEDCH_MAP_43RESERVEDCH_MAP_42
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_41RESERVEDCH_MAP_40
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-867 ICSS_INTC_CH_MAP_REG10 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_43R/W0hInterrupt Channel Map for intr_in[43]
23-21RESERVEDR/WX
20-16CH_MAP_42R/W0hInterrupt Channel Map for intr_in[42]
15-13RESERVEDR/WX
12-8CH_MAP_41R/W0hInterrupt Channel Map for intr_in[41]
7-5RESERVEDR/WX
4-0CH_MAP_40R/W0hInterrupt Channel Map for intr_in[40]

4.14.7.43 ICSS_INTC_CH_MAP_REG11 Register (Offset = 42Ch) [reset = X]

ICSS_INTC_CH_MAP_REG11 is shown in Figure 6-444 and described in Table 6-869.

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Interrupt Channel Map Register for 44 to 44+3

Table 6-868 ICSS_INTC_CH_MAP_REG11 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 042Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 042Ch
Figure 6-444 ICSS_INTC_CH_MAP_REG11 Register
31302928272625242322212019181716
RESERVEDCH_MAP_47RESERVEDCH_MAP_46
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_45RESERVEDCH_MAP_44
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-869 ICSS_INTC_CH_MAP_REG11 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_47R/W0hInterrupt Channel Map for intr_in[47]
23-21RESERVEDR/WX
20-16CH_MAP_46R/W0hInterrupt Channel Map for intr_in[46]
15-13RESERVEDR/WX
12-8CH_MAP_45R/W0hInterrupt Channel Map for intr_in[45]
7-5RESERVEDR/WX
4-0CH_MAP_44R/W0hInterrupt Channel Map for intr_in[44]

4.14.7.44 ICSS_INTC_CH_MAP_REG12 Register (Offset = 430h) [reset = X]

ICSS_INTC_CH_MAP_REG12 is shown in Figure 6-445 and described in Table 6-871.

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Interrupt Channel Map Register for 48 to 48+3

Table 6-870 ICSS_INTC_CH_MAP_REG12 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0430h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0430h
Figure 6-445 ICSS_INTC_CH_MAP_REG12 Register
31302928272625242322212019181716
RESERVEDCH_MAP_51RESERVEDCH_MAP_50
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_49RESERVEDCH_MAP_48
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-871 ICSS_INTC_CH_MAP_REG12 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_51R/W0hInterrupt Channel Map for intr_in[51]
23-21RESERVEDR/WX
20-16CH_MAP_50R/W0hInterrupt Channel Map for intr_in[50]
15-13RESERVEDR/WX
12-8CH_MAP_49R/W0hInterrupt Channel Map for intr_in[49]
7-5RESERVEDR/WX
4-0CH_MAP_48R/W0hInterrupt Channel Map for intr_in[48]

4.14.7.45 ICSS_INTC_CH_MAP_REG13 Register (Offset = 434h) [reset = X]

ICSS_INTC_CH_MAP_REG13 is shown in Figure 6-446 and described in Table 6-873.

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Interrupt Channel Map Register for 52 to 52+3

Table 6-872 ICSS_INTC_CH_MAP_REG13 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0434h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0434h
Figure 6-446 ICSS_INTC_CH_MAP_REG13 Register
31302928272625242322212019181716
RESERVEDCH_MAP_55RESERVEDCH_MAP_54
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_53RESERVEDCH_MAP_52
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-873 ICSS_INTC_CH_MAP_REG13 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_55R/W0hInterrupt Channel Map for intr_in[55]
23-21RESERVEDR/WX
20-16CH_MAP_54R/W0hInterrupt Channel Map for intr_in[54]
15-13RESERVEDR/WX
12-8CH_MAP_53R/W0hInterrupt Channel Map for intr_in[53]
7-5RESERVEDR/WX
4-0CH_MAP_52R/W0hInterrupt Channel Map for intr_in[52]

4.14.7.46 ICSS_INTC_CH_MAP_REG14 Register (Offset = 438h) [reset = X]

ICSS_INTC_CH_MAP_REG14 is shown in Figure 6-447 and described in Table 6-875.

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Interrupt Channel Map Register for 56 to 56+3

Table 6-874 ICSS_INTC_CH_MAP_REG14 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0438h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0438h
Figure 6-447 ICSS_INTC_CH_MAP_REG14 Register
31302928272625242322212019181716
RESERVEDCH_MAP_59RESERVEDCH_MAP_58
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_57RESERVEDCH_MAP_56
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-875 ICSS_INTC_CH_MAP_REG14 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_59R/W0hInterrupt Channel Map for intr_in[59]
23-21RESERVEDR/WX
20-16CH_MAP_58R/W0hInterrupt Channel Map for intr_in[58]
15-13RESERVEDR/WX
12-8CH_MAP_57R/W0hInterrupt Channel Map for intr_in[57]
7-5RESERVEDR/WX
4-0CH_MAP_56R/W0hInterrupt Channel Map for intr_in[56]

4.14.7.47 ICSS_INTC_CH_MAP_REG15 Register (Offset = 43Ch) [reset = X]

ICSS_INTC_CH_MAP_REG15 is shown in Figure 6-448 and described in Table 6-877.

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Interrupt Channel Map Register for 60 to 60+3

Table 6-876 ICSS_INTC_CH_MAP_REG15 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 043Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 043Ch
Figure 6-448 ICSS_INTC_CH_MAP_REG15 Register
31302928272625242322212019181716
RESERVEDCH_MAP_63RESERVEDCH_MAP_62
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_61RESERVEDCH_MAP_60
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-877 ICSS_INTC_CH_MAP_REG15 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_63R/W0hInterrupt Channel Map for intr_in[63]
23-21RESERVEDR/WX
20-16CH_MAP_62R/W0hInterrupt Channel Map for intr_in[62]
15-13RESERVEDR/WX
12-8CH_MAP_61R/W0hInterrupt Channel Map for intr_in[61]
7-5RESERVEDR/WX
4-0CH_MAP_60R/W0hInterrupt Channel Map for intr_in[60]

4.14.7.48 ICSS_INTC_CH_MAP_REG16 Register (Offset = 440h) [reset = X]

ICSS_INTC_CH_MAP_REG16 is shown in Figure 6-449 and described in Table 6-879.

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Interrupt Channel Map Register for 64 to 64+3

Table 6-878 ICSS_INTC_CH_MAP_REG16 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0440h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0440h
Figure 6-449 ICSS_INTC_CH_MAP_REG16 Register
31302928272625242322212019181716
RESERVEDCH_MAP_67RESERVEDCH_MAP_66
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_65RESERVEDCH_MAP_64
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-879 ICSS_INTC_CH_MAP_REG16 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_67R/W0hInterrupt Channel Map for slv_events_in[3]
23-21RESERVEDR/WX
20-16CH_MAP_66R/W0hInterrupt Channel Map for slv_events_in[2]
15-13RESERVEDR/WX
12-8CH_MAP_65R/W0hInterrupt Channel Map for slv_events_in[1]
7-5RESERVEDR/WX
4-0CH_MAP_64R/W0hInterrupt Channel Map for slv_events_in[0]

4.14.7.49 ICSS_INTC_CH_MAP_REG17 Register (Offset = 444h) [reset = X]

ICSS_INTC_CH_MAP_REG17 is shown in Figure 6-450 and described in Table 6-881.

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Interrupt Channel Map Register for 68 to 68+3

Table 6-880 ICSS_INTC_CH_MAP_REG17 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0444h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0444h
Figure 6-450 ICSS_INTC_CH_MAP_REG17 Register
31302928272625242322212019181716
RESERVEDCH_MAP_71RESERVEDCH_MAP_70
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_69RESERVEDCH_MAP_68
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-881 ICSS_INTC_CH_MAP_REG17 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_71R/W0hInterrupt Channel Map for slv_events_in[7]
23-21RESERVEDR/WX
20-16CH_MAP_70R/W0hInterrupt Channel Map for slv_events_in[6]
15-13RESERVEDR/WX
12-8CH_MAP_69R/W0hInterrupt Channel Map for slv_events_in[5]
7-5RESERVEDR/WX
4-0CH_MAP_68R/W0hInterrupt Channel Map for slv_events_in[4]

4.14.7.50 ICSS_INTC_CH_MAP_REG18 Register (Offset = 448h) [reset = X]

ICSS_INTC_CH_MAP_REG18 is shown in Figure 6-451 and described in Table 6-883.

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Interrupt Channel Map Register for 72 to 72+3

Table 6-882 ICSS_INTC_CH_MAP_REG18 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0448h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0448h
Figure 6-451 ICSS_INTC_CH_MAP_REG18 Register
31302928272625242322212019181716
RESERVEDCH_MAP_75RESERVEDCH_MAP_74
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_73RESERVEDCH_MAP_72
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-883 ICSS_INTC_CH_MAP_REG18 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_75R/W0hInterrupt Channel Map for slv_events_in[11]
23-21RESERVEDR/WX
20-16CH_MAP_74R/W0hInterrupt Channel Map for slv_events_in[10]
15-13RESERVEDR/WX
12-8CH_MAP_73R/W0hInterrupt Channel Map for slv_events_in[9]
7-5RESERVEDR/WX
4-0CH_MAP_72R/W0hInterrupt Channel Map for slv_events_in[8]

4.14.7.51 ICSS_INTC_CH_MAP_REG19 Register (Offset = 44Ch) [reset = X]

ICSS_INTC_CH_MAP_REG19 is shown in Figure 6-452 and described in Table 6-885.

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Interrupt Channel Map Register for 76 to 76+3

Table 6-884 ICSS_INTC_CH_MAP_REG19 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 044Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 044Ch
Figure 6-452 ICSS_INTC_CH_MAP_REG19 Register
31302928272625242322212019181716
RESERVEDCH_MAP_79RESERVEDCH_MAP_78
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_77RESERVEDCH_MAP_76
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-885 ICSS_INTC_CH_MAP_REG19 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_79R/W0hInterrupt Channel Map for slv_events_in[15]
23-21RESERVEDR/WX
20-16CH_MAP_78R/W0hInterrupt Channel Map for slv_events_in[14]
15-13RESERVEDR/WX
12-8CH_MAP_77R/W0hInterrupt Channel Map for slv_events_in[13]
7-5RESERVEDR/WX
4-0CH_MAP_76R/W0hInterrupt Channel Map for slv_events_in[12]

4.14.7.52 ICSS_INTC_CH_MAP_REG20 Register (Offset = 450h) [reset = X]

ICSS_INTC_CH_MAP_REG20 is shown in Figure 6-453 and described in Table 6-887.

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Interrupt Channel Map Register for 80 to 80+3

Table 6-886 ICSS_INTC_CH_MAP_REG20 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0450h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0450h
Figure 6-453 ICSS_INTC_CH_MAP_REG20 Register
31302928272625242322212019181716
RESERVEDCH_MAP_83RESERVEDCH_MAP_82
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_81RESERVEDCH_MAP_80
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-887 ICSS_INTC_CH_MAP_REG20 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_83R/W0hInterrupt Channel Map for slv_events_in[19]
23-21RESERVEDR/WX
20-16CH_MAP_82R/W0hInterrupt Channel Map for slv_events_in[18]
15-13RESERVEDR/WX
12-8CH_MAP_81R/W0hInterrupt Channel Map for slv_events_in[17]
7-5RESERVEDR/WX
4-0CH_MAP_80R/W0hInterrupt Channel Map for slv_events_in[16]

4.14.7.53 ICSS_INTC_CH_MAP_REG21 Register (Offset = 454h) [reset = X]

ICSS_INTC_CH_MAP_REG21 is shown in Figure 6-454 and described in Table 6-889.

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Interrupt Channel Map Register for 84 to 84+3

Table 6-888 ICSS_INTC_CH_MAP_REG21 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0454h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0454h
Figure 6-454 ICSS_INTC_CH_MAP_REG21 Register
31302928272625242322212019181716
RESERVEDCH_MAP_87RESERVEDCH_MAP_86
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_85RESERVEDCH_MAP_84
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-889 ICSS_INTC_CH_MAP_REG21 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_87R/W0hInterrupt Channel Map for slv_events_in[23]
23-21RESERVEDR/WX
20-16CH_MAP_86R/W0hInterrupt Channel Map for slv_events_in[22]
15-13RESERVEDR/WX
12-8CH_MAP_85R/W0hInterrupt Channel Map for slv_events_in[21]
7-5RESERVEDR/WX
4-0CH_MAP_84R/W0hInterrupt Channel Map for slv_events_in[20]

4.14.7.54 ICSS_INTC_CH_MAP_REG22 Register (Offset = 458h) [reset = X]

ICSS_INTC_CH_MAP_REG22 is shown in Figure 6-455 and described in Table 6-891.

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Interrupt Channel Map Register for 88 to 88+3

Table 6-890 ICSS_INTC_CH_MAP_REG22 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0458h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0458h
Figure 6-455 ICSS_INTC_CH_MAP_REG22 Register
31302928272625242322212019181716
RESERVEDCH_MAP_91RESERVEDCH_MAP_90
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_89RESERVEDCH_MAP_88
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-891 ICSS_INTC_CH_MAP_REG22 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_91R/W0hInterrupt Channel Map for slv_events_in[27]
23-21RESERVEDR/WX
20-16CH_MAP_90R/W0hInterrupt Channel Map for slv_events_in[26]
15-13RESERVEDR/WX
12-8CH_MAP_89R/W0hInterrupt Channel Map for slv_events_in[25]
7-5RESERVEDR/WX
4-0CH_MAP_88R/W0hInterrupt Channel Map for slv_events_in[24]

4.14.7.55 ICSS_INTC_CH_MAP_REG23 Register (Offset = 45Ch) [reset = X]

ICSS_INTC_CH_MAP_REG23 is shown in Figure 6-456 and described in Table 6-893.

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Interrupt Channel Map Register for 92 to 92+3

Table 6-892 ICSS_INTC_CH_MAP_REG23 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 045Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 045Ch
Figure 6-456 ICSS_INTC_CH_MAP_REG23 Register
31302928272625242322212019181716
RESERVEDCH_MAP_95RESERVEDCH_MAP_94
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_93RESERVEDCH_MAP_92
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-893 ICSS_INTC_CH_MAP_REG23 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_95R/W0hInterrupt Channel Map for slv_events_in[31]
23-21RESERVEDR/WX
20-16CH_MAP_94R/W0hInterrupt Channel Map for slv_events_in[30]
15-13RESERVEDR/WX
12-8CH_MAP_93R/W0hInterrupt Channel Map for slv_events_in[29]
7-5RESERVEDR/WX
4-0CH_MAP_92R/W0hInterrupt Channel Map for slv_events_in[28]

4.14.7.56 ICSS_INTC_CH_MAP_REG24 Register (Offset = 460h) [reset = X]

ICSS_INTC_CH_MAP_REG24 is shown in Figure 6-457 and described in Table 6-895.

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Interrupt Channel Map Register for 96 to 96+3

Table 6-894 ICSS_INTC_CH_MAP_REG24 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0460h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0460h
Figure 6-457 ICSS_INTC_CH_MAP_REG24 Register
31302928272625242322212019181716
RESERVEDCH_MAP_99RESERVEDCH_MAP_98
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_97RESERVEDCH_MAP_96
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-895 ICSS_INTC_CH_MAP_REG24 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_99R/W0hInterrupt Channel Map for slv_events_in[35]
23-21RESERVEDR/WX
20-16CH_MAP_98R/W0hInterrupt Channel Map for slv_events_in[34]
15-13RESERVEDR/WX
12-8CH_MAP_97R/W0hInterrupt Channel Map for slv_events_in[33]
7-5RESERVEDR/WX
4-0CH_MAP_96R/W0hInterrupt Channel Map for slv_events_in[32]

4.14.7.57 ICSS_INTC_CH_MAP_REG25 Register (Offset = 464h) [reset = X]

ICSS_INTC_CH_MAP_REG25 is shown in Figure 6-458 and described in Table 6-897.

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Interrupt Channel Map Register for 100 to 100+3

Table 6-896 ICSS_INTC_CH_MAP_REG25 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0464h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0464h
Figure 6-458 ICSS_INTC_CH_MAP_REG25 Register
31302928272625242322212019181716
RESERVEDCH_MAP_103RESERVEDCH_MAP_102
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_101RESERVEDCH_MAP_100
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-897 ICSS_INTC_CH_MAP_REG25 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_103R/W0hInterrupt Channel Map for slv_events_in[39]
23-21RESERVEDR/WX
20-16CH_MAP_102R/W0hInterrupt Channel Map for slv_events_in[38]
15-13RESERVEDR/WX
12-8CH_MAP_101R/W0hInterrupt Channel Map for slv_events_in[37]
7-5RESERVEDR/WX
4-0CH_MAP_100R/W0hInterrupt Channel Map for slv_events_in[36]

4.14.7.58 ICSS_INTC_CH_MAP_REG26 Register (Offset = 468h) [reset = X]

ICSS_INTC_CH_MAP_REG26 is shown in Figure 6-459 and described in Table 6-899.

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Interrupt Channel Map Register for 104 to 104+3

Table 6-898 ICSS_INTC_CH_MAP_REG26 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0468h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0468h
Figure 6-459 ICSS_INTC_CH_MAP_REG26 Register
31302928272625242322212019181716
RESERVEDCH_MAP_107RESERVEDCH_MAP_106
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_105RESERVEDCH_MAP_104
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-899 ICSS_INTC_CH_MAP_REG26 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_107R/W0hInterrupt Channel Map for slv_events_in[43]
23-21RESERVEDR/WX
20-16CH_MAP_106R/W0hInterrupt Channel Map for slv_events_in[42]
15-13RESERVEDR/WX
12-8CH_MAP_105R/W0hInterrupt Channel Map for slv_events_in[41]
7-5RESERVEDR/WX
4-0CH_MAP_104R/W0hInterrupt Channel Map for slv_events_in[40]

4.14.7.59 ICSS_INTC_CH_MAP_REG27 Register (Offset = 46Ch) [reset = X]

ICSS_INTC_CH_MAP_REG27 is shown in Figure 6-460 and described in Table 6-901.

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Interrupt Channel Map Register for 108 to 108+3

Table 6-900 ICSS_INTC_CH_MAP_REG27 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 046Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 046Ch
Figure 6-460 ICSS_INTC_CH_MAP_REG27 Register
31302928272625242322212019181716
RESERVEDCH_MAP_111RESERVEDCH_MAP_110
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_109RESERVEDCH_MAP_108
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-901 ICSS_INTC_CH_MAP_REG27 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_111R/W0hInterrupt Channel Map for slv_events_in[47]
23-21RESERVEDR/WX
20-16CH_MAP_110R/W0hInterrupt Channel Map for slv_events_in[46]
15-13RESERVEDR/WX
12-8CH_MAP_109R/W0hInterrupt Channel Map for slv_events_in[45]
7-5RESERVEDR/WX
4-0CH_MAP_108R/W0hInterrupt Channel Map for slv_events_in[44]

4.14.7.60 ICSS_INTC_CH_MAP_REG28 Register (Offset = 470h) [reset = X]

ICSS_INTC_CH_MAP_REG28 is shown in Figure 6-461 and described in Table 6-903.

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Interrupt Channel Map Register for 112 to 112+3

Table 6-902 ICSS_INTC_CH_MAP_REG28 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0470h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0470h
Figure 6-461 ICSS_INTC_CH_MAP_REG28 Register
31302928272625242322212019181716
RESERVEDCH_MAP_115RESERVEDCH_MAP_114
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_113RESERVEDCH_MAP_112
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-903 ICSS_INTC_CH_MAP_REG28 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_115R/W0hInterrupt Channel Map for slv_events_in[51]
23-21RESERVEDR/WX
20-16CH_MAP_114R/W0hInterrupt Channel Map for slv_events_in[50]
15-13RESERVEDR/WX
12-8CH_MAP_113R/W0hInterrupt Channel Map for slv_events_in[49]
7-5RESERVEDR/WX
4-0CH_MAP_112R/W0hInterrupt Channel Map for slv_events_in[48]

4.14.7.61 ICSS_INTC_CH_MAP_REG29 Register (Offset = 474h) [reset = X]

ICSS_INTC_CH_MAP_REG29 is shown in Figure 6-462 and described in Table 6-905.

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Interrupt Channel Map Register for 116 to 116+3

Table 6-904 ICSS_INTC_CH_MAP_REG29 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0474h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0474h
Figure 6-462 ICSS_INTC_CH_MAP_REG29 Register
31302928272625242322212019181716
RESERVEDCH_MAP_119RESERVEDCH_MAP_118
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_117RESERVEDCH_MAP_116
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-905 ICSS_INTC_CH_MAP_REG29 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_119R/W0hInterrupt Channel Map for slv_events_in[55]
23-21RESERVEDR/WX
20-16CH_MAP_118R/W0hInterrupt Channel Map for slv_events_in[54]
15-13RESERVEDR/WX
12-8CH_MAP_117R/W0hInterrupt Channel Map for slv_events_in[53]
7-5RESERVEDR/WX
4-0CH_MAP_116R/W0hInterrupt Channel Map for slv_events_in[52]

4.14.7.62 ICSS_INTC_CH_MAP_REG30 Register (Offset = 478h) [reset = X]

ICSS_INTC_CH_MAP_REG30 is shown in Figure 6-463 and described in Table 6-907.

Return to Summary Table.

Interrupt Channel Map Register for 120 to 120+3

Table 6-906 ICSS_INTC_CH_MAP_REG30 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0478h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0478h
Figure 6-463 ICSS_INTC_CH_MAP_REG30 Register
31302928272625242322212019181716
RESERVEDCH_MAP_123RESERVEDCH_MAP_122
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_121RESERVEDCH_MAP_120
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-907 ICSS_INTC_CH_MAP_REG30 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_123R/W0hInterrupt Channel Map for slv_events_in[59]
23-21RESERVEDR/WX
20-16CH_MAP_122R/W0hInterrupt Channel Map for slv_events_in[58]
15-13RESERVEDR/WX
12-8CH_MAP_121R/W0hInterrupt Channel Map for slv_events_in[57]
7-5RESERVEDR/WX
4-0CH_MAP_120R/W0hInterrupt Channel Map for slv_events_in[56]

4.14.7.63 ICSS_INTC_CH_MAP_REG31 Register (Offset = 47Ch) [reset = X]

ICSS_INTC_CH_MAP_REG31 is shown in Figure 6-464 and described in Table 6-909.

Return to Summary Table.

Interrupt Channel Map Register for 124 to 124+3

Table 6-908 ICSS_INTC_CH_MAP_REG31 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 047Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 047Ch
Figure 6-464 ICSS_INTC_CH_MAP_REG31 Register
31302928272625242322212019181716
RESERVEDCH_MAP_127RESERVEDCH_MAP_126
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_125RESERVEDCH_MAP_124
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-909 ICSS_INTC_CH_MAP_REG31 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_127R/W0hInterrupt Channel Map for slv_events_in[63]
23-21RESERVEDR/WX
20-16CH_MAP_126R/W0hInterrupt Channel Map for slv_events_in[62]
15-13RESERVEDR/WX
12-8CH_MAP_125R/W0hInterrupt Channel Map for slv_events_in[61]
7-5RESERVEDR/WX
4-0CH_MAP_124R/W0hInterrupt Channel Map for slv_events_in[60]

4.14.7.64 ICSS_INTC_CH_MAP_REG32 Register (Offset = 480h) [reset = X]

ICSS_INTC_CH_MAP_REG32 is shown in Figure 6-465 and described in Table 6-911.

Return to Summary Table.

Interrupt Channel Map Register for 128 to 128+3

Table 6-910 ICSS_INTC_CH_MAP_REG32 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0480h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0480h
Figure 6-465 ICSS_INTC_CH_MAP_REG32 Register
31302928272625242322212019181716
RESERVEDCH_MAP_131RESERVEDCH_MAP_130
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_129RESERVEDCH_MAP_128
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-911 ICSS_INTC_CH_MAP_REG32 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_131R/W0hInterrupt Channel Map for slv_events_in[67]
23-21RESERVEDR/WX
20-16CH_MAP_130R/W0hInterrupt Channel Map for slv_events_in[66]
15-13RESERVEDR/WX
12-8CH_MAP_129R/W0hInterrupt Channel Map for slv_events_in[65]
7-5RESERVEDR/WX
4-0CH_MAP_128R/W0hInterrupt Channel Map for slv_events_in[64]

4.14.7.65 ICSS_INTC_CH_MAP_REG33 Register (Offset = 484h) [reset = X]

ICSS_INTC_CH_MAP_REG33 is shown in Figure 6-466 and described in Table 6-913.

Return to Summary Table.

Interrupt Channel Map Register for 132 to 132+3

Table 6-912 ICSS_INTC_CH_MAP_REG33 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0484h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0484h
Figure 6-466 ICSS_INTC_CH_MAP_REG33 Register
31302928272625242322212019181716
RESERVEDCH_MAP_135RESERVEDCH_MAP_134
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_133RESERVEDCH_MAP_132
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-913 ICSS_INTC_CH_MAP_REG33 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_135R/W0hInterrupt Channel Map for slv_events_in[71]
23-21RESERVEDR/WX
20-16CH_MAP_134R/W0hInterrupt Channel Map for slv_events_in[70]
15-13RESERVEDR/WX
12-8CH_MAP_133R/W0hInterrupt Channel Map for slv_events_in[69]
7-5RESERVEDR/WX
4-0CH_MAP_132R/W0hInterrupt Channel Map for slv_events_in[68]

4.14.7.66 ICSS_INTC_CH_MAP_REG34 Register (Offset = 488h) [reset = X]

ICSS_INTC_CH_MAP_REG34 is shown in Figure 6-467 and described in Table 6-915.

Return to Summary Table.

Interrupt Channel Map Register for 136 to 136+3

Table 6-914 ICSS_INTC_CH_MAP_REG34 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0488h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0488h
Figure 6-467 ICSS_INTC_CH_MAP_REG34 Register
31302928272625242322212019181716
RESERVEDCH_MAP_139RESERVEDCH_MAP_138
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_137RESERVEDCH_MAP_136
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-915 ICSS_INTC_CH_MAP_REG34 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_139R/W0hInterrupt Channel Map for slv_events_in[75]
23-21RESERVEDR/WX
20-16CH_MAP_138R/W0hInterrupt Channel Map for slv_events_in[74]
15-13RESERVEDR/WX
12-8CH_MAP_137R/W0hInterrupt Channel Map for slv_events_in[73]
7-5RESERVEDR/WX
4-0CH_MAP_136R/W0hInterrupt Channel Map for slv_events_in[72]

4.14.7.67 ICSS_INTC_CH_MAP_REG35 Register (Offset = 48Ch) [reset = X]

ICSS_INTC_CH_MAP_REG35 is shown in Figure 6-468 and described in Table 6-917.

Return to Summary Table.

Interrupt Channel Map Register for 140 to 140+3

Table 6-916 ICSS_INTC_CH_MAP_REG35 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 048Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 048Ch
Figure 6-468 ICSS_INTC_CH_MAP_REG35 Register
31302928272625242322212019181716
RESERVEDCH_MAP_143RESERVEDCH_MAP_142
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_141RESERVEDCH_MAP_140
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-917 ICSS_INTC_CH_MAP_REG35 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_143R/W0hInterrupt Channel Map for slv_events_in[79]
23-21RESERVEDR/WX
20-16CH_MAP_142R/W0hInterrupt Channel Map for slv_events_in[78]
15-13RESERVEDR/WX
12-8CH_MAP_141R/W0hInterrupt Channel Map for slv_events_in[77]
7-5RESERVEDR/WX
4-0CH_MAP_140R/W0hInterrupt Channel Map for slv_events_in[76]

4.14.7.68 ICSS_INTC_CH_MAP_REG36 Register (Offset = 490h) [reset = X]

ICSS_INTC_CH_MAP_REG36 is shown in Figure 6-469 and described in Table 6-919.

Return to Summary Table.

Interrupt Channel Map Register for 144 to 144+3

Table 6-918 ICSS_INTC_CH_MAP_REG36 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0490h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0490h
Figure 6-469 ICSS_INTC_CH_MAP_REG36 Register
31302928272625242322212019181716
RESERVEDCH_MAP_147RESERVEDCH_MAP_146
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_145RESERVEDCH_MAP_144
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-919 ICSS_INTC_CH_MAP_REG36 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_147R/W0hInterrupt Channel Map for slv_events_in[83]
23-21RESERVEDR/WX
20-16CH_MAP_146R/W0hInterrupt Channel Map for slv_events_in[82]
15-13RESERVEDR/WX
12-8CH_MAP_145R/W0hInterrupt Channel Map for slv_events_in[81]
7-5RESERVEDR/WX
4-0CH_MAP_144R/W0hInterrupt Channel Map for slv_events_in[80]

4.14.7.69 ICSS_INTC_CH_MAP_REG37 Register (Offset = 494h) [reset = X]

ICSS_INTC_CH_MAP_REG37 is shown in Figure 6-470 and described in Table 6-921.

Return to Summary Table.

Interrupt Channel Map Register for 148 to 148+3

Table 6-920 ICSS_INTC_CH_MAP_REG37 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0494h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0494h
Figure 6-470 ICSS_INTC_CH_MAP_REG37 Register
31302928272625242322212019181716
RESERVEDCH_MAP_151RESERVEDCH_MAP_150
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_149RESERVEDCH_MAP_148
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-921 ICSS_INTC_CH_MAP_REG37 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_151R/W0hInterrupt Channel Map for slv_events_in[87]
23-21RESERVEDR/WX
20-16CH_MAP_150R/W0hInterrupt Channel Map for slv_events_in[86]
15-13RESERVEDR/WX
12-8CH_MAP_149R/W0hInterrupt Channel Map for slv_events_in[85]
7-5RESERVEDR/WX
4-0CH_MAP_148R/W0hInterrupt Channel Map for slv_events_in[84]

4.14.7.70 ICSS_INTC_CH_MAP_REG38 Register (Offset = 498h) [reset = X]

ICSS_INTC_CH_MAP_REG38 is shown in Figure 6-471 and described in Table 6-923.

Return to Summary Table.

Interrupt Channel Map Register for 152 to 152+3

Table 6-922 ICSS_INTC_CH_MAP_REG38 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0498h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0498h
Figure 6-471 ICSS_INTC_CH_MAP_REG38 Register
31302928272625242322212019181716
RESERVEDCH_MAP_155RESERVEDCH_MAP_154
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_153RESERVEDCH_MAP_152
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-923 ICSS_INTC_CH_MAP_REG38 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_155R/W0hInterrupt Channel Map for slv_events_in[91]
23-21RESERVEDR/WX
20-16CH_MAP_154R/W0hInterrupt Channel Map for slv_events_in[90]
15-13RESERVEDR/WX
12-8CH_MAP_153R/W0hInterrupt Channel Map for slv_events_in[89]
7-5RESERVEDR/WX
4-0CH_MAP_152R/W0hInterrupt Channel Map for slv_events_in[88]

4.14.7.71 ICSS_INTC_CH_MAP_REG39 Register (Offset = 49Ch) [reset = X]

ICSS_INTC_CH_MAP_REG39 is shown in Figure 6-472 and described in Table 6-925.

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Interrupt Channel Map Register for 156 to 156+3

Table 6-924 ICSS_INTC_CH_MAP_REG39 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 049Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 049Ch
Figure 6-472 ICSS_INTC_CH_MAP_REG39 Register
31302928272625242322212019181716
RESERVEDCH_MAP_159RESERVEDCH_MAP_158
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDCH_MAP_157RESERVEDCH_MAP_156
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-925 ICSS_INTC_CH_MAP_REG39 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24CH_MAP_159R/W0hInterrupt Channel Map for slv_events_in[95]
23-21RESERVEDR/WX
20-16CH_MAP_158R/W0hInterrupt Channel Map for slv_events_in[94]
15-13RESERVEDR/WX
12-8CH_MAP_157R/W0hInterrupt Channel Map for slv_events_in[93]
7-5RESERVEDR/WX
4-0CH_MAP_156R/W0hInterrupt Channel Map for slv_events_in[92]

4.14.7.72 ICSS_INTC_HINT_MAP_REG0 Register (Offset = 800h) [reset = X]

ICSS_INTC_HINT_MAP_REG0 is shown in Figure 6-473 and described in Table 6-927.

Return to Summary Table.

Host Interrupt Map Register for 0 to 0+3

Table 6-926 ICSS_INTC_HINT_MAP_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0800h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0800h
Figure 6-473 ICSS_INTC_HINT_MAP_REG0 Register
31302928272625242322212019181716
RESERVEDHINT_MAP_3RESERVEDHINT_MAP_2
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDHINT_MAP_1RESERVEDHINT_MAP_0
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-927 ICSS_INTC_HINT_MAP_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24HINT_MAP_3R/W0hHost Interrupt Map for Channel 3
23-21RESERVEDR/WX
20-16HINT_MAP_2R/W0hHost Interrupt Map for Channel 2
15-13RESERVEDR/WX
12-8HINT_MAP_1R/W0hHost Interrupt Map for Channel 1
7-5RESERVEDR/WX
4-0HINT_MAP_0R/W0hHost Interrupt Map for Channel 0

4.14.7.73 ICSS_INTC_HINT_MAP_REG1 Register (Offset = 804h) [reset = X]

ICSS_INTC_HINT_MAP_REG1 is shown in Figure 6-474 and described in Table 6-929.

Return to Summary Table.

Host Interrupt Map Register for 4 to 4+3

Table 6-928 ICSS_INTC_HINT_MAP_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0804h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0804h
Figure 6-474 ICSS_INTC_HINT_MAP_REG1 Register
31302928272625242322212019181716
RESERVEDHINT_MAP_7RESERVEDHINT_MAP_6
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDHINT_MAP_5RESERVEDHINT_MAP_4
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-929 ICSS_INTC_HINT_MAP_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24HINT_MAP_7R/W0hHost Interrupt Map for Channel 7
23-21RESERVEDR/WX
20-16HINT_MAP_6R/W0hHost Interrupt Map for Channel 6
15-13RESERVEDR/WX
12-8HINT_MAP_5R/W0hHost Interrupt Map for Channel 5
7-5RESERVEDR/WX
4-0HINT_MAP_4R/W0hHost Interrupt Map for Channel 4

4.14.7.74 ICSS_INTC_HINT_MAP_REG2 Register (Offset = 808h) [reset = X]

ICSS_INTC_HINT_MAP_REG2 is shown in Figure 6-475 and described in Table 6-931.

Return to Summary Table.

Host Interrupt Map Register for 8 to 8+3

Table 6-930 ICSS_INTC_HINT_MAP_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0808h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0808h
Figure 6-475 ICSS_INTC_HINT_MAP_REG2 Register
31302928272625242322212019181716
RESERVEDHINT_MAP_11RESERVEDHINT_MAP_10
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDHINT_MAP_9RESERVEDHINT_MAP_8
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-931 ICSS_INTC_HINT_MAP_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24HINT_MAP_11R/W0hHost Interrupt Map for Channel 11
23-21RESERVEDR/WX
20-16HINT_MAP_10R/W0hHost Interrupt Map for Channel 10
15-13RESERVEDR/WX
12-8HINT_MAP_9R/W0hHost Interrupt Map for Channel 9
7-5RESERVEDR/WX
4-0HINT_MAP_8R/W0hHost Interrupt Map for Channel 8

4.14.7.75 ICSS_INTC_HINT_MAP_REG3 Register (Offset = 80Ch) [reset = X]

ICSS_INTC_HINT_MAP_REG3 is shown in Figure 6-476 and described in Table 6-933.

Return to Summary Table.

Host Interrupt Map Register for 12 to 12+3

Table 6-932 ICSS_INTC_HINT_MAP_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 080Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 080Ch
Figure 6-476 ICSS_INTC_HINT_MAP_REG3 Register
31302928272625242322212019181716
RESERVEDHINT_MAP_15RESERVEDHINT_MAP_14
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDHINT_MAP_13RESERVEDHINT_MAP_12
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-933 ICSS_INTC_HINT_MAP_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24HINT_MAP_15R/W0hHost Interrupt Map for Channel 15
23-21RESERVEDR/WX
20-16HINT_MAP_14R/W0hHost Interrupt Map for Channel 14
15-13RESERVEDR/WX
12-8HINT_MAP_13R/W0hHost Interrupt Map for Channel 13
7-5RESERVEDR/WX
4-0HINT_MAP_12R/W0hHost Interrupt Map for Channel 12

4.14.7.76 ICSS_INTC_HINT_MAP_REG4 Register (Offset = 810h) [reset = X]

ICSS_INTC_HINT_MAP_REG4 is shown in Figure 6-477 and described in Table 6-935.

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Host Interrupt Map Register for 16 to 16+4

Table 6-934 ICSS_INTC_HINT_MAP_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0810h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0810h
Figure 6-477 ICSS_INTC_HINT_MAP_REG4 Register
31302928272625242322212019181716
RESERVEDHINT_MAP_19RESERVEDHINT_MAP_18
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDHINT_MAP_17RESERVEDHINT_MAP_16
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-935 ICSS_INTC_HINT_MAP_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24HINT_MAP_19R/W0hHost Interrupt Map for Channel 19
23-21RESERVEDR/WX
20-16HINT_MAP_18R/W0hHost Interrupt Map for Channel 18
15-13RESERVEDR/WX
12-8HINT_MAP_17R/W0hHost Interrupt Map for Channel 17
7-5RESERVEDR/WX
4-0HINT_MAP_16R/W0hHost Interrupt Map for Channel 16

4.14.7.77 ICSS_INTC_PRI_HINT_REG0 Register (Offset = 900h) [reset = X]

ICSS_INTC_PRI_HINT_REG0 is shown in Figure 6-478 and described in Table 6-937.

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Host Int 0 Prioritized Interrupt Register

Table 6-936 ICSS_INTC_PRI_HINT_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0900h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0900h
Figure 6-478 ICSS_INTC_PRI_HINT_REG0 Register
3130292827262524
NONE_HINT_0RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_0
R-XR-0h
76543210
PRI_HINT_0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-937 ICSS_INTC_PRI_HINT_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_0R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_0R0hHost Int 0 Prioritized Interrupt

4.14.7.78 ICSS_INTC_PRI_HINT_REG1 Register (Offset = 904h) [reset = X]

ICSS_INTC_PRI_HINT_REG1 is shown in Figure 6-479 and described in Table 6-939.

Return to Summary Table.

Host Int 1 Prioritized Interrupt Register

Table 6-938 ICSS_INTC_PRI_HINT_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0904h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0904h
Figure 6-479 ICSS_INTC_PRI_HINT_REG1 Register
3130292827262524
NONE_HINT_1RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_1
R-XR-0h
76543210
PRI_HINT_1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-939 ICSS_INTC_PRI_HINT_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_1R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_1R0hHost Int 1 Prioritized Interrupt

4.14.7.79 ICSS_INTC_PRI_HINT_REG2 Register (Offset = 908h) [reset = X]

ICSS_INTC_PRI_HINT_REG2 is shown in Figure 6-480 and described in Table 6-941.

Return to Summary Table.

Host Int 2 Prioritized Interrupt Register

Table 6-940 ICSS_INTC_PRI_HINT_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0908h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0908h
Figure 6-480 ICSS_INTC_PRI_HINT_REG2 Register
3130292827262524
NONE_HINT_2RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_2
R-XR-0h
76543210
PRI_HINT_2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-941 ICSS_INTC_PRI_HINT_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_2R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_2R0hHost Int 2 Prioritized Interrupt

4.14.7.80 ICSS_INTC_PRI_HINT_REG3 Register (Offset = 90Ch) [reset = X]

ICSS_INTC_PRI_HINT_REG3 is shown in Figure 6-481 and described in Table 6-943.

Return to Summary Table.

Host Int 3 Prioritized Interrupt Register

Table 6-942 ICSS_INTC_PRI_HINT_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 090Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 090Ch
Figure 6-481 ICSS_INTC_PRI_HINT_REG3 Register
3130292827262524
NONE_HINT_3RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_3
R-XR-0h
76543210
PRI_HINT_3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-943 ICSS_INTC_PRI_HINT_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_3R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_3R0hHost Int 3 Prioritized Interrupt

4.14.7.81 ICSS_INTC_PRI_HINT_REG4 Register (Offset = 910h) [reset = X]

ICSS_INTC_PRI_HINT_REG4 is shown in Figure 6-482 and described in Table 6-945.

Return to Summary Table.

Host Int 4 Prioritized Interrupt Register

Table 6-944 ICSS_INTC_PRI_HINT_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0910h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0910h
Figure 6-482 ICSS_INTC_PRI_HINT_REG4 Register
3130292827262524
NONE_HINT_4RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_4
R-XR-0h
76543210
PRI_HINT_4
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-945 ICSS_INTC_PRI_HINT_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_4R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_4R0hHost Int 4 Prioritized Interrupt

4.14.7.82 ICSS_INTC_PRI_HINT_REG5 Register (Offset = 914h) [reset = X]

ICSS_INTC_PRI_HINT_REG5 is shown in Figure 6-483 and described in Table 6-947.

Return to Summary Table.

Host Int 5 Prioritized Interrupt Register

Table 6-946 ICSS_INTC_PRI_HINT_REG5 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0914h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0914h
Figure 6-483 ICSS_INTC_PRI_HINT_REG5 Register
3130292827262524
NONE_HINT_5RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_5
R-XR-0h
76543210
PRI_HINT_5
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-947 ICSS_INTC_PRI_HINT_REG5 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_5R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_5R0hHost Int 5 Prioritized Interrupt

4.14.7.83 ICSS_INTC_PRI_HINT_REG6 Register (Offset = 918h) [reset = X]

ICSS_INTC_PRI_HINT_REG6 is shown in Figure 6-484 and described in Table 6-949.

Return to Summary Table.

Host Int 6 Prioritized Interrupt Register

Table 6-948 ICSS_INTC_PRI_HINT_REG6 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0918h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0918h
Figure 6-484 ICSS_INTC_PRI_HINT_REG6 Register
3130292827262524
NONE_HINT_6RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_6
R-XR-0h
76543210
PRI_HINT_6
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-949 ICSS_INTC_PRI_HINT_REG6 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_6R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_6R0hHost Int 6 Prioritized Interrupt

4.14.7.84 ICSS_INTC_PRI_HINT_REG7 Register (Offset = 91Ch) [reset = X]

ICSS_INTC_PRI_HINT_REG7 is shown in Figure 6-485 and described in Table 6-951.

Return to Summary Table.

Host Int 7 Prioritized Interrupt Register

Table 6-950 ICSS_INTC_PRI_HINT_REG7 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 091Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 091Ch
Figure 6-485 ICSS_INTC_PRI_HINT_REG7 Register
3130292827262524
NONE_HINT_7RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_7
R-XR-0h
76543210
PRI_HINT_7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-951 ICSS_INTC_PRI_HINT_REG7 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_7R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_7R0hHost Int 7 Prioritized Interrupt

4.14.7.85 ICSS_INTC_PRI_HINT_REG8 Register (Offset = 920h) [reset = X]

ICSS_INTC_PRI_HINT_REG8 is shown in Figure 6-486 and described in Table 6-953.

Return to Summary Table.

Host Int 8 Prioritized Interrupt Register

Table 6-952 ICSS_INTC_PRI_HINT_REG8 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0920h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0920h
Figure 6-486 ICSS_INTC_PRI_HINT_REG8 Register
3130292827262524
NONE_HINT_8RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_8
R-XR-0h
76543210
PRI_HINT_8
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-953 ICSS_INTC_PRI_HINT_REG8 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_8R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_8R0hHost Int 8 Prioritized Interrupt

4.14.7.86 ICSS_INTC_PRI_HINT_REG9 Register (Offset = 924h) [reset = X]

ICSS_INTC_PRI_HINT_REG9 is shown in Figure 6-487 and described in Table 6-955.

Return to Summary Table.

Host Int 9 Prioritized Interrupt Register

Table 6-954 ICSS_INTC_PRI_HINT_REG9 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0924h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0924h
Figure 6-487 ICSS_INTC_PRI_HINT_REG9 Register
3130292827262524
NONE_HINT_9RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_9
R-XR-0h
76543210
PRI_HINT_9
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-955 ICSS_INTC_PRI_HINT_REG9 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_9R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_9R0hHost Int 9 Prioritized Interrupt

4.14.7.87 ICSS_INTC_PRI_HINT_REG10 Register (Offset = 928h) [reset = X]

ICSS_INTC_PRI_HINT_REG10 is shown in Figure 6-488 and described in Table 6-957.

Return to Summary Table.

Host Int 10 Prioritized Interrupt Register

Table 6-956 ICSS_INTC_PRI_HINT_REG10 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0928h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0928h
Figure 6-488 ICSS_INTC_PRI_HINT_REG10 Register
3130292827262524
NONE_HINT_10RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_10
R-XR-0h
76543210
PRI_HINT_10
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-957 ICSS_INTC_PRI_HINT_REG10 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_10R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_10R0hHost Int 10 Prioritized Interrupt

4.14.7.88 ICSS_INTC_PRI_HINT_REG11 Register (Offset = 92Ch) [reset = X]

ICSS_INTC_PRI_HINT_REG11 is shown in Figure 6-489 and described in Table 6-959.

Return to Summary Table.

Host Int 11 Prioritized Interrupt Register

Table 6-958 ICSS_INTC_PRI_HINT_REG11 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 092Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 092Ch
Figure 6-489 ICSS_INTC_PRI_HINT_REG11 Register
3130292827262524
NONE_HINT_11RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_11
R-XR-0h
76543210
PRI_HINT_11
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-959 ICSS_INTC_PRI_HINT_REG11 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_11R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_11R0hHost Int 11 Prioritized Interrupt

4.14.7.89 ICSS_INTC_PRI_HINT_REG12 Register (Offset = 930h) [reset = X]

ICSS_INTC_PRI_HINT_REG12 is shown in Figure 6-490 and described in Table 6-961.

Return to Summary Table.

Host Int 12 Prioritized Interrupt Register

Table 6-960 ICSS_INTC_PRI_HINT_REG12 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0930h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0930h
Figure 6-490 ICSS_INTC_PRI_HINT_REG12 Register
3130292827262524
NONE_HINT_12RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_12
R-XR-0h
76543210
PRI_HINT_12
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-961 ICSS_INTC_PRI_HINT_REG12 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_12R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_12R0hHost Int 12 Prioritized Interrupt

4.14.7.90 ICSS_INTC_PRI_HINT_REG13 Register (Offset = 934h) [reset = X]

ICSS_INTC_PRI_HINT_REG13 is shown in Figure 6-491 and described in Table 6-963.

Return to Summary Table.

Host Int 13 Prioritized Interrupt Register

Table 6-962 ICSS_INTC_PRI_HINT_REG13 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0934h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0934h
Figure 6-491 ICSS_INTC_PRI_HINT_REG13 Register
3130292827262524
NONE_HINT_13RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_13
R-XR-0h
76543210
PRI_HINT_13
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-963 ICSS_INTC_PRI_HINT_REG13 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_13R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_13R0hHost Int 13 Prioritized Interrupt

4.14.7.91 ICSS_INTC_PRI_HINT_REG14 Register (Offset = 938h) [reset = X]

ICSS_INTC_PRI_HINT_REG14 is shown in Figure 6-492 and described in Table 6-965.

Return to Summary Table.

Host Int 14 Prioritized Interrupt Register

Table 6-964 ICSS_INTC_PRI_HINT_REG14 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0938h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0938h
Figure 6-492 ICSS_INTC_PRI_HINT_REG14 Register
3130292827262524
NONE_HINT_14RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_14
R-XR-0h
76543210
PRI_HINT_14
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-965 ICSS_INTC_PRI_HINT_REG14 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_14R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_14R0hHost Int 14 Prioritized Interrupt

4.14.7.92 ICSS_INTC_PRI_HINT_REG15 Register (Offset = 93Ch) [reset = X]

ICSS_INTC_PRI_HINT_REG15 is shown in Figure 6-493 and described in Table 6-967.

Return to Summary Table.

Host Int 15 Prioritized Interrupt Register

Table 6-966 ICSS_INTC_PRI_HINT_REG15 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 093Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 093Ch
Figure 6-493 ICSS_INTC_PRI_HINT_REG15 Register
3130292827262524
NONE_HINT_15RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_15
R-XR-0h
76543210
PRI_HINT_15
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-967 ICSS_INTC_PRI_HINT_REG15 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_15R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_15R0hHost Int 15 Prioritized Interrupt

4.14.7.93 ICSS_INTC_PRI_HINT_REG16 Register (Offset = 940h) [reset = X]

ICSS_INTC_PRI_HINT_REG16 is shown in Figure 6-494 and described in Table 6-969.

Return to Summary Table.

Host Int 16 Prioritized Interrupt Register

Table 6-968 ICSS_INTC_PRI_HINT_REG16 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0940h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0940h
Figure 6-494 ICSS_INTC_PRI_HINT_REG16 Register
3130292827262524
NONE_HINT_16RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_16
R-XR-0h
76543210
PRI_HINT_16
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-969 ICSS_INTC_PRI_HINT_REG16 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_16R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_16R0hHost Int 16 Prioritized Interrupt

4.14.7.94 ICSS_INTC_PRI_HINT_REG17 Register (Offset = 944h) [reset = X]

ICSS_INTC_PRI_HINT_REG17 is shown in Figure 6-495 and described in Table 6-971.

Return to Summary Table.

Host Int 17 Prioritized Interrupt Register

Table 6-970 ICSS_INTC_PRI_HINT_REG17 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0944h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0944h
Figure 6-495 ICSS_INTC_PRI_HINT_REG17 Register
3130292827262524
NONE_HINT_17RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_17
R-XR-0h
76543210
PRI_HINT_17
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-971 ICSS_INTC_PRI_HINT_REG17 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_17R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_17R0hHost Int 17 Prioritized Interrupt

4.14.7.95 ICSS_INTC_PRI_HINT_REG18 Register (Offset = 948h) [reset = X]

ICSS_INTC_PRI_HINT_REG18 is shown in Figure 6-496 and described in Table 6-973.

Return to Summary Table.

Host Int 18 Prioritized Interrupt Register

Table 6-972 ICSS_INTC_PRI_HINT_REG18 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0948h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0948h
Figure 6-496 ICSS_INTC_PRI_HINT_REG18 Register
3130292827262524
NONE_HINT_18RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_18
R-XR-0h
76543210
PRI_HINT_18
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-973 ICSS_INTC_PRI_HINT_REG18 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_18R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_18R0hHost Int 18 Prioritized Interrupt

4.14.7.96 ICSS_INTC_PRI_HINT_REG19 Register (Offset = 94Ch) [reset = X]

ICSS_INTC_PRI_HINT_REG19 is shown in Figure 6-497 and described in Table 6-975.

Return to Summary Table.

Host Int 19 Prioritized Interrupt Register

Table 6-974 ICSS_INTC_PRI_HINT_REG19 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 094Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 094Ch
Figure 6-497 ICSS_INTC_PRI_HINT_REG19 Register
3130292827262524
NONE_HINT_19RESERVED
R-1hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDPRI_HINT_19
R-XR-0h
76543210
PRI_HINT_19
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 6-975 ICSS_INTC_PRI_HINT_REG19 Register Field Descriptions
BitFieldTypeResetDescription
31NONE_HINT_19R1hNo interrupt pending flag
30-10RESERVEDRX
9-0PRI_HINT_19R0hHost Int 19 Prioritized Interrupt

4.14.7.97 ICSS_INTC_POLARITY_REG0 Register (Offset = D00h) [reset = FFFFFFFFh]

ICSS_INTC_POLARITY_REG0 is shown in Figure 6-498 and described in Table 6-977.

Return to Summary Table.

Polarity Register 0

Table 6-976 ICSS_INTC_POLARITY_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D00h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D00h
Figure 6-498 ICSS_INTC_POLARITY_REG0 Register
3130292827262524
POLARITY_31POLARITY_30POLARITY_29POLARITY_28POLARITY_27POLARITY_26POLARITY_25POLARITY_24
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
POLARITY_23POLARITY_22POLARITY_21POLARITY_20POLARITY_19POLARITY_18POLARITY_17POLARITY_16
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
POLARITY_15POLARITY_14POLARITY_13POLARITY_12POLARITY_11POLARITY_10POLARITY_9POLARITY_8
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
POLARITY_7POLARITY_6POLARITY_5POLARITY_4POLARITY_3POLARITY_2POLARITY_1POLARITY_0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-977 ICSS_INTC_POLARITY_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31POLARITY_31R/W1hPolarity for intr_in[31]
0=low
30POLARITY_30R/W1hPolarity for intr_in[30]
0=low
29POLARITY_29R/W1hPolarity for intr_in[29]
0=low
28POLARITY_28R/W1hPolarity for intr_in[28]
0=low
27POLARITY_27R/W1hPolarity for intr_in[27]
0=low
26POLARITY_26R/W1hPolarity for intr_in[26]
0=low
25POLARITY_25R/W1hPolarity for intr_in[25]
0=low
24POLARITY_24R/W1hPolarity for intr_in[24]
0=low
23POLARITY_23R/W1hPolarity for intr_in[23]
0=low
22POLARITY_22R/W1hPolarity for intr_in[22]
0=low
21POLARITY_21R/W1hPolarity for intr_in[21]
0=low
20POLARITY_20R/W1hPolarity for intr_in[20]
0=low
19POLARITY_19R/W1hPolarity for intr_in[19]
0=low
18POLARITY_18R/W1hPolarity for intr_in[18]
0=low
17POLARITY_17R/W1hPolarity for intr_in[17]
0=low
16POLARITY_16R/W1hPolarity for intr_in[16]
0=low
15POLARITY_15R/W1hPolarity for intr_in[15]
0=low
14POLARITY_14R/W1hPolarity for intr_in[14]
0=low
13POLARITY_13R/W1hPolarity for intr_in[13]
0=low
12POLARITY_12R/W1hPolarity for intr_in[12]
0=low
11POLARITY_11R/W1hPolarity for intr_in[11]
0=low
10POLARITY_10R/W1hPolarity for intr_in[10]
0=low
9POLARITY_9R/W1hPolarity for intr_in[9]
0=low
8POLARITY_8R/W1hPolarity for intr_in[8]
0=low
7POLARITY_7R/W1hPolarity for intr_in[7]
0=low
6POLARITY_6R/W1hPolarity for intr_in[6]
0=low
5POLARITY_5R/W1hPolarity for intr_in[5]
0=low
4POLARITY_4R/W1hPolarity for intr_in[4]
0=low
3POLARITY_3R/W1hPolarity for intr_in[3]
0=low
2POLARITY_2R/W1hPolarity for intr_in[2]
0=low
1POLARITY_1R/W1hPolarity for intr_in[1]
0=low
0POLARITY_0R/W1hPolarity for intr_in[0]
0=low

4.14.7.98 ICSS_INTC_POLARITY_REG1 Register (Offset = D04h) [reset = FFFFFFFFh]

ICSS_INTC_POLARITY_REG1 is shown in Figure 6-499 and described in Table 6-979.

Return to Summary Table.

Polarity Register 1

Table 6-978 ICSS_INTC_POLARITY_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D04h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D04h
Figure 6-499 ICSS_INTC_POLARITY_REG1 Register
3130292827262524
POLARITY_63POLARITY_62POLARITY_61POLARITY_60POLARITY_59POLARITY_58POLARITY_57POLARITY_56
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
POLARITY_55POLARITY_54POLARITY_53POLARITY_52POLARITY_51POLARITY_50POLARITY_49POLARITY_48
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
POLARITY_47POLARITY_46POLARITY_45POLARITY_44POLARITY_43POLARITY_42POLARITY_41POLARITY_40
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
POLARITY_39POLARITY_38POLARITY_37POLARITY_36POLARITY_35POLARITY_34POLARITY_33POLARITY_32
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-979 ICSS_INTC_POLARITY_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31POLARITY_63R/W1hPolarity for intr_in[63]
0=low
30POLARITY_62R/W1hPolarity for intr_in[62]
0=low
29POLARITY_61R/W1hPolarity for intr_in[61]
0=low
28POLARITY_60R/W1hPolarity for intr_in[60]
0=low
27POLARITY_59R/W1hPolarity for intr_in[59]
0=low
26POLARITY_58R/W1hPolarity for intr_in[58]
0=low
25POLARITY_57R/W1hPolarity for intr_in[57]
0=low
24POLARITY_56R/W1hPolarity for intr_in[56]
0=low
23POLARITY_55R/W1hPolarity for intr_in[55]
0=low
22POLARITY_54R/W1hPolarity for intr_in[54]
0=low
21POLARITY_53R/W1hPolarity for intr_in[53]
0=low
20POLARITY_52R/W1hPolarity for intr_in[52]
0=low
19POLARITY_51R/W1hPolarity for intr_in[51]
0=low
18POLARITY_50R/W1hPolarity for intr_in[50]
0=low
17POLARITY_49R/W1hPolarity for intr_in[49]
0=low
16POLARITY_48R/W1hPolarity for intr_in[48]
0=low
15POLARITY_47R/W1hPolarity for intr_in[47]
0=low
14POLARITY_46R/W1hPolarity for intr_in[46]
0=low
13POLARITY_45R/W1hPolarity for intr_in[45]
0=low
12POLARITY_44R/W1hPolarity for intr_in[44]
0=low
11POLARITY_43R/W1hPolarity for intr_in[43]
0=low
10POLARITY_42R/W1hPolarity for intr_in[42]
0=low
9POLARITY_41R/W1hPolarity for intr_in[41]
0=low
8POLARITY_40R/W1hPolarity for intr_in[40]
0=low
7POLARITY_39R/W1hPolarity for intr_in[39]
0=low
6POLARITY_38R/W1hPolarity for intr_in[38]
0=low
5POLARITY_37R/W1hPolarity for intr_in[37]
0=low
4POLARITY_36R/W1hPolarity for intr_in[36]
0=low
3POLARITY_35R/W1hPolarity for intr_in[35]
0=low
2POLARITY_34R/W1hPolarity for intr_in[34]
0=low
1POLARITY_33R/W1hPolarity for intr_in[33]
0=low
0POLARITY_32R/W1hPolarity for intr_in[32]
0=low

4.14.7.99 ICSS_INTC_POLARITY_REG2 Register (Offset = D08h) [reset = FFFFFFFFh]

ICSS_INTC_POLARITY_REG2 is shown in Figure 6-500 and described in Table 6-981.

Return to Summary Table.

Polarity Register 2

Table 6-980 ICSS_INTC_POLARITY_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D08h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D08h
Figure 6-500 ICSS_INTC_POLARITY_REG2 Register
3130292827262524
POLARITY_95POLARITY_94POLARITY_93POLARITY_92POLARITY_91POLARITY_90POLARITY_89POLARITY_88
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
POLARITY_87POLARITY_86POLARITY_85POLARITY_84POLARITY_83POLARITY_82POLARITY_81POLARITY_80
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
POLARITY_79POLARITY_78POLARITY_77POLARITY_76POLARITY_75POLARITY_74POLARITY_73POLARITY_72
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
POLARITY_71POLARITY_70POLARITY_69POLARITY_68POLARITY_67POLARITY_66POLARITY_65POLARITY_64
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-981 ICSS_INTC_POLARITY_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31POLARITY_95R/W1hPolarity for slv_events_in[31]
0=low
30POLARITY_94R/W1hPolarity for slv_events_in[30]
0=low
29POLARITY_93R/W1hPolarity for slv_events_in[29]
0=low
28POLARITY_92R/W1hPolarity for slv_events_in[28]
0=low
27POLARITY_91R/W1hPolarity for slv_events_in[27]
0=low
26POLARITY_90R/W1hPolarity for slv_events_in[26]
0=low
25POLARITY_89R/W1hPolarity for slv_events_in[25]
0=low
24POLARITY_88R/W1hPolarity for slv_events_in[24]
0=low
23POLARITY_87R/W1hPolarity for slv_events_in[23]
0=low
22POLARITY_86R/W1hPolarity for slv_events_in[22]
0=low
21POLARITY_85R/W1hPolarity for slv_events_in[21]
0=low
20POLARITY_84R/W1hPolarity for slv_events_in[20]
0=low
19POLARITY_83R/W1hPolarity for slv_events_in[19]
0=low
18POLARITY_82R/W1hPolarity for slv_events_in[18]
0=low
17POLARITY_81R/W1hPolarity for slv_events_in[17]
0=low
16POLARITY_80R/W1hPolarity for slv_events_in[16]
0=low
15POLARITY_79R/W1hPolarity for slv_events_in[15]
0=low
14POLARITY_78R/W1hPolarity for slv_events_in[14]
0=low
13POLARITY_77R/W1hPolarity for slv_events_in[13]
0=low
12POLARITY_76R/W1hPolarity for slv_events_in[12]
0=low
11POLARITY_75R/W1hPolarity for slv_events_in[11]
0=low
10POLARITY_74R/W1hPolarity for slv_events_in[10]
0=low
9POLARITY_73R/W1hPolarity for slv_events_in[9]
0=low
8POLARITY_72R/W1hPolarity for slv_events_in[8]
0=low
7POLARITY_71R/W1hPolarity for slv_events_in[7]
0=low
6POLARITY_70R/W1hPolarity for slv_events_in[6]
0=low
5POLARITY_69R/W1hPolarity for slv_events_in[5]
0=low
4POLARITY_68R/W1hPolarity for slv_events_in[4]
0=low
3POLARITY_67R/W1hPolarity for slv_events_in[3]
0=low
2POLARITY_66R/W1hPolarity for slv_events_in[2]
0=low
1POLARITY_65R/W1hPolarity for slv_events_in[1]
0=low
0POLARITY_64R/W1hPolarity for slv_events_in[0]
0=low

4.14.7.100 ICSS_INTC_POLARITY_REG3 Register (Offset = D0Ch) [reset = FFFFFFFFh]

ICSS_INTC_POLARITY_REG3 is shown in Figure 6-501 and described in Table 6-983.

Return to Summary Table.

Polarity Register 3

Table 6-982 ICSS_INTC_POLARITY_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D0Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D0Ch
Figure 6-501 ICSS_INTC_POLARITY_REG3 Register
3130292827262524
POLARITY_127POLARITY_126POLARITY_125POLARITY_124POLARITY_123POLARITY_122POLARITY_121POLARITY_120
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
POLARITY_119POLARITY_118POLARITY_117POLARITY_116POLARITY_115POLARITY_114POLARITY_113POLARITY_112
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
POLARITY_111POLARITY_110POLARITY_109POLARITY_108POLARITY_107POLARITY_106POLARITY_105POLARITY_104
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
POLARITY_103POLARITY_102POLARITY_101POLARITY_100POLARITY_99POLARITY_98POLARITY_97POLARITY_96
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-983 ICSS_INTC_POLARITY_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31POLARITY_127R/W1hPolarity for slv_events_in[63]
0=low
30POLARITY_126R/W1hPolarity for slv_events_in[62]
0=low
29POLARITY_125R/W1hPolarity for slv_events_in[61]
0=low
28POLARITY_124R/W1hPolarity for slv_events_in[60]
0=low
27POLARITY_123R/W1hPolarity for slv_events_in[59]
0=low
26POLARITY_122R/W1hPolarity for slv_events_in[58]
0=low
25POLARITY_121R/W1hPolarity for slv_events_in[57]
0=low
24POLARITY_120R/W1hPolarity for slv_events_in[56]
0=low
23POLARITY_119R/W1hPolarity for slv_events_in[55]
0=low
22POLARITY_118R/W1hPolarity for slv_events_in[54]
0=low
21POLARITY_117R/W1hPolarity for slv_events_in[53]
0=low
20POLARITY_116R/W1hPolarity for slv_events_in[52]
0=low
19POLARITY_115R/W1hPolarity for slv_events_in[51]
0=low
18POLARITY_114R/W1hPolarity for slv_events_in[50]
0=low
17POLARITY_113R/W1hPolarity for slv_events_in[49]
0=low
16POLARITY_112R/W1hPolarity for slv_events_in[48]
0=low
15POLARITY_111R/W1hPolarity for slv_events_in[47]
0=low
14POLARITY_110R/W1hPolarity for slv_events_in[46]
0=low
13POLARITY_109R/W1hPolarity for slv_events_in[45]
0=low
12POLARITY_108R/W1hPolarity for slv_events_in[44]
0=low
11POLARITY_107R/W1hPolarity for slv_events_in[43]
0=low
10POLARITY_106R/W1hPolarity for slv_events_in[42]
0=low
9POLARITY_105R/W1hPolarity for slv_events_in[41]
0=low
8POLARITY_104R/W1hPolarity for slv_events_in[40]
0=low
7POLARITY_103R/W1hPolarity for slv_events_in[39]
0=low
6POLARITY_102R/W1hPolarity for slv_events_in[38]
0=low
5POLARITY_101R/W1hPolarity for slv_events_in[37]
0=low
4POLARITY_100R/W1hPolarity for slv_events_in[36]
0=low
3POLARITY_99R/W1hPolarity for slv_events_in[35]
0=low
2POLARITY_98R/W1hPolarity for slv_events_in[34]
0=low
1POLARITY_97R/W1hPolarity for slv_events_in[33]
0=low
0POLARITY_96R/W1hPolarity for slv_events_in[32]
0=low

4.14.7.101 ICSS_INTC_POLARITY_REG4 Register (Offset = D10h) [reset = FFFFFFFFh]

ICSS_INTC_POLARITY_REG4 is shown in Figure 6-502 and described in Table 6-985.

Return to Summary Table.

Polarity Register 4

Table 6-984 ICSS_INTC_POLARITY_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D10h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D10h
Figure 6-502 ICSS_INTC_POLARITY_REG4 Register
3130292827262524
POLARITY_159POLARITY_158POLARITY_157POLARITY_156POLARITY_155POLARITY_154POLARITY_153POLARITY_152
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
POLARITY_151POLARITY_150POLARITY_149POLARITY_148POLARITY_147POLARITY_146POLARITY_145POLARITY_144
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
POLARITY_143POLARITY_142POLARITY_141POLARITY_140POLARITY_139POLARITY_138POLARITY_137POLARITY_136
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
POLARITY_135POLARITY_134POLARITY_133POLARITY_132POLARITY_131POLARITY_130POLARITY_129POLARITY_128
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-985 ICSS_INTC_POLARITY_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31POLARITY_159R/W1hPolarity for slv_events_in[95]
0=low
30POLARITY_158R/W1hPolarity for slv_events_in[94]
0=low
29POLARITY_157R/W1hPolarity for slv_events_in[93]
0=low
28POLARITY_156R/W1hPolarity for slv_events_in[92]
0=low
27POLARITY_155R/W1hPolarity for slv_events_in[91]
0=low
26POLARITY_154R/W1hPolarity for slv_events_in[90]
0=low
25POLARITY_153R/W1hPolarity for slv_events_in[89]
0=low
24POLARITY_152R/W1hPolarity for slv_events_in[88]
0=low
23POLARITY_151R/W1hPolarity for slv_events_in[87]
0=low
22POLARITY_150R/W1hPolarity for slv_events_in[86]
0=low
21POLARITY_149R/W1hPolarity for slv_events_in[85]
0=low
20POLARITY_148R/W1hPolarity for slv_events_in[84]
0=low
19POLARITY_147R/W1hPolarity for slv_events_in[83]
0=low
18POLARITY_146R/W1hPolarity for slv_events_in[82]
0=low
17POLARITY_145R/W1hPolarity for slv_events_in[81]
0=low
16POLARITY_144R/W1hPolarity for slv_events_in[80]
0=low
15POLARITY_143R/W1hPolarity for slv_events_in[79]
0=low
14POLARITY_142R/W1hPolarity for slv_events_in[78]
0=low
13POLARITY_141R/W1hPolarity for slv_events_in[77]
0=low
12POLARITY_140R/W1hPolarity for slv_events_in[76]
0=low
11POLARITY_139R/W1hPolarity for slv_events_in[75]
0=low
10POLARITY_138R/W1hPolarity for slv_events_in[74]
0=low
9POLARITY_137R/W1hPolarity for slv_events_in[73]
0=low
8POLARITY_136R/W1hPolarity for slv_events_in[72]
0=low
7POLARITY_135R/W1hPolarity for slv_events_in[71]
0=low
6POLARITY_134R/W1hPolarity for slv_events_in[70]
0=low
5POLARITY_133R/W1hPolarity for slv_events_in[69]
0=low
4POLARITY_132R/W1hPolarity for slv_events_in[68]
0=low
3POLARITY_131R/W1hPolarity for slv_events_in[67]
0=low
2POLARITY_130R/W1hPolarity for slv_events_in[66]
0=low
1POLARITY_129R/W1hPolarity for slv_events_in[65]
0=low
0POLARITY_128R/W1hPolarity for slv_events_in[64]
0=low

4.14.7.102 ICSS_INTC_TYPE_REG0 Register (Offset = D80h) [reset = 0h]

ICSS_INTC_TYPE_REG0 is shown in Figure 6-503 and described in Table 6-987.

Return to Summary Table.

Type Register 0

Table 6-986 ICSS_INTC_TYPE_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D80h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D80h
Figure 6-503 ICSS_INTC_TYPE_REG0 Register
3130292827262524
TYPE_31TYPE_30TYPE_29TYPE_28TYPE_27TYPE_26TYPE_25TYPE_24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TYPE_23TYPE_22TYPE_21TYPE_20TYPE_19TYPE_18TYPE_17TYPE_16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TYPE_15TYPE_14TYPE_13TYPE_12TYPE_11TYPE_10TYPE_9TYPE_8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TYPE_7TYPE_6TYPE_5TYPE_4TYPE_3TYPE_2TYPE_1TYPE_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-987 ICSS_INTC_TYPE_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31TYPE_31R/W0hType for intr_in[31]
0=level
30TYPE_30R/W0hType for intr_in[30]
0=level
29TYPE_29R/W0hType for intr_in[29]
0=level
28TYPE_28R/W0hType for intr_in[28]
0=level
27TYPE_27R/W0hType for intr_in[27]
0=level
26TYPE_26R/W0hType for intr_in[26]
0=level
25TYPE_25R/W0hType for intr_in[25]
0=level
24TYPE_24R/W0hType for intr_in[24]
0=level
23TYPE_23R/W0hType for intr_in[23]
0=level
22TYPE_22R/W0hType for intr_in[22]
0=level
21TYPE_21R/W0hType for intr_in[21]
0=level
20TYPE_20R/W0hType for intr_in[20]
0=level
19TYPE_19R/W0hType for intr_in[19]
0=level
18TYPE_18R/W0hType for intr_in[18]
0=level
17TYPE_17R/W0hType for intr_in[17]
0=level
16TYPE_16R/W0hType for intr_in[16]
0=level
15TYPE_15R/W0hType for intr_in[15]
0=level
14TYPE_14R/W0hType for intr_in[14]
0=level
13TYPE_13R/W0hType for intr_in[13]
0=level
12TYPE_12R/W0hType for intr_in[12]
0=level
11TYPE_11R/W0hType for intr_in[11]
0=level
10TYPE_10R/W0hType for intr_in[10]
0=level
9TYPE_9R/W0hType for intr_in[9]
0=level
8TYPE_8R/W0hType for intr_in[8]
0=level
7TYPE_7R/W0hType for intr_in[7]
0=level
6TYPE_6R/W0hType for intr_in[6]
0=level
5TYPE_5R/W0hType for intr_in[5]
0=level
4TYPE_4R/W0hType for intr_in[4]
0=level
3TYPE_3R/W0hType for intr_in[3]
0=level
2TYPE_2R/W0hType for intr_in[2]
0=level
1TYPE_1R/W0hType for intr_in[1]
0=level
0TYPE_0R/W0hType for intr_in[0]
0=level

4.14.7.103 ICSS_INTC_TYPE_REG1 Register (Offset = D84h) [reset = 0h]

ICSS_INTC_TYPE_REG1 is shown in Figure 6-504 and described in Table 6-989.

Return to Summary Table.

Type Register 1

Table 6-988 ICSS_INTC_TYPE_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D84h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D84h
Figure 6-504 ICSS_INTC_TYPE_REG1 Register
3130292827262524
TYPE_63TYPE_62TYPE_61TYPE_60TYPE_59TYPE_58TYPE_57TYPE_56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TYPE_55TYPE_54TYPE_53TYPE_52TYPE_51TYPE_50TYPE_49TYPE_48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TYPE_47TYPE_46TYPE_45TYPE_44TYPE_43TYPE_42TYPE_41TYPE_40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TYPE_39TYPE_38TYPE_37TYPE_36TYPE_35TYPE_34TYPE_33TYPE_32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-989 ICSS_INTC_TYPE_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31TYPE_63R/W0hType for intr_in[63]
0=level
30TYPE_62R/W0hType for intr_in[62]
0=level
29TYPE_61R/W0hType for intr_in[61]
0=level
28TYPE_60R/W0hType for intr_in[60]
0=level
27TYPE_59R/W0hType for intr_in[59]
0=level
26TYPE_58R/W0hType for intr_in[58]
0=level
25TYPE_57R/W0hType for intr_in[57]
0=level
24TYPE_56R/W0hType for intr_in[56]
0=level
23TYPE_55R/W0hType for intr_in[55]
0=level
22TYPE_54R/W0hType for intr_in[54]
0=level
21TYPE_53R/W0hType for intr_in[53]
0=level
20TYPE_52R/W0hType for intr_in[52]
0=level
19TYPE_51R/W0hType for intr_in[51]
0=level
18TYPE_50R/W0hType for intr_in[50]
0=level
17TYPE_49R/W0hType for intr_in[49]
0=level
16TYPE_48R/W0hType for intr_in[48]
0=level
15TYPE_47R/W0hType for intr_in[47]
0=level
14TYPE_46R/W0hType for intr_in[46]
0=level
13TYPE_45R/W0hType for intr_in[45]
0=level
12TYPE_44R/W0hType for intr_in[44]
0=level
11TYPE_43R/W0hType for intr_in[43]
0=level
10TYPE_42R/W0hType for intr_in[42]
0=level
9TYPE_41R/W0hType for intr_in[41]
0=level
8TYPE_40R/W0hType for intr_in[40]
0=level
7TYPE_39R/W0hType for intr_in[39]
0=level
6TYPE_38R/W0hType for intr_in[38]
0=level
5TYPE_37R/W0hType for intr_in[37]
0=level
4TYPE_36R/W0hType for intr_in[36]
0=level
3TYPE_35R/W0hType for intr_in[35]
0=level
2TYPE_34R/W0hType for intr_in[34]
0=level
1TYPE_33R/W0hType for intr_in[33]
0=level
0TYPE_32R/W0hType for intr_in[32]
0=level

4.14.7.104 ICSS_INTC_TYPE_REG2 Register (Offset = D88h) [reset = 0h]

ICSS_INTC_TYPE_REG2 is shown in Figure 6-505 and described in Table 6-991.

Return to Summary Table.

Type Register 2

Table 6-990 ICSS_INTC_TYPE_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D88h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D88h
Figure 6-505 ICSS_INTC_TYPE_REG2 Register
3130292827262524
TYPE_95TYPE_94TYPE_93TYPE_92TYPE_91TYPE_90TYPE_89TYPE_88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TYPE_87TYPE_86TYPE_85TYPE_84TYPE_83TYPE_82TYPE_81TYPE_80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TYPE_79TYPE_78TYPE_77TYPE_76TYPE_75TYPE_74TYPE_73TYPE_72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TYPE_71TYPE_70TYPE_69TYPE_68TYPE_67TYPE_66TYPE_65TYPE_64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-991 ICSS_INTC_TYPE_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31TYPE_95R/W0hType for slv_events_in[31]
0=level
30TYPE_94R/W0hType for slv_events_in[30]
0=level
29TYPE_93R/W0hType for slv_events_in[29]
0=level
28TYPE_92R/W0hType for slv_events_in[28]
0=level
27TYPE_91R/W0hType for slv_events_in[27]
0=level
26TYPE_90R/W0hType for slv_events_in[26]
0=level
25TYPE_89R/W0hType for slv_events_in[25]
0=level
24TYPE_88R/W0hType for slv_events_in[24]
0=level
23TYPE_87R/W0hType for slv_events_in[23]
0=level
22TYPE_86R/W0hType for slv_events_in[22]
0=level
21TYPE_85R/W0hType for slv_events_in[21]
0=level
20TYPE_84R/W0hType for slv_events_in[20]
0=level
19TYPE_83R/W0hType for slv_events_in[19]
0=level
18TYPE_82R/W0hType for slv_events_in[18]
0=level
17TYPE_81R/W0hType for slv_events_in[17]
0=level
16TYPE_80R/W0hType for slv_events_in[16]
0=level
15TYPE_79R/W0hType for slv_events_in[15]
0=level
14TYPE_78R/W0hType for slv_events_in[14]
0=level
13TYPE_77R/W0hType for slv_events_in[13]
0=level
12TYPE_76R/W0hType for slv_events_in[12]
0=level
11TYPE_75R/W0hType for slv_events_in[11]
0=level
10TYPE_74R/W0hType for slv_events_in[10]
0=level
9TYPE_73R/W0hType for slv_events_in[9]
0=level
8TYPE_72R/W0hType for slv_events_in[8]
0=level
7TYPE_71R/W0hType for slv_events_in[7]
0=level
6TYPE_70R/W0hType for slv_events_in[6]
0=level
5TYPE_69R/W0hType for slv_events_in[5]
0=level
4TYPE_68R/W0hType for slv_events_in[4]
0=level
3TYPE_67R/W0hType for slv_events_in[3]
0=level
2TYPE_66R/W0hType for slv_events_in[2]
0=level
1TYPE_65R/W0hType for slv_events_in[1]
0=level
0TYPE_64R/W0hType for slv_events_in[0]
0=level

4.14.7.105 ICSS_INTC_TYPE_REG3 Register (Offset = D8Ch) [reset = 0h]

ICSS_INTC_TYPE_REG3 is shown in Figure 6-506 and described in Table 6-993.

Return to Summary Table.

Type Register 3

Table 6-992 ICSS_INTC_TYPE_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D8Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D8Ch
Figure 6-506 ICSS_INTC_TYPE_REG3 Register
3130292827262524
TYPE_127TYPE_126TYPE_125TYPE_124TYPE_123TYPE_122TYPE_121TYPE_120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TYPE_119TYPE_118TYPE_117TYPE_116TYPE_115TYPE_114TYPE_113TYPE_112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TYPE_111TYPE_110TYPE_109TYPE_108TYPE_107TYPE_106TYPE_105TYPE_104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TYPE_103TYPE_102TYPE_101TYPE_100TYPE_99TYPE_98TYPE_97TYPE_96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-993 ICSS_INTC_TYPE_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31TYPE_127R/W0hType for slv_events_in[63]
0=level
30TYPE_126R/W0hType for slv_events_in[62]
0=level
29TYPE_125R/W0hType for slv_events_in[61]
0=level
28TYPE_124R/W0hType for slv_events_in[60]
0=level
27TYPE_123R/W0hType for slv_events_in[59]
0=level
26TYPE_122R/W0hType for slv_events_in[58]
0=level
25TYPE_121R/W0hType for slv_events_in[57]
0=level
24TYPE_120R/W0hType for slv_events_in[56]
0=level
23TYPE_119R/W0hType for slv_events_in[55]
0=level
22TYPE_118R/W0hType for slv_events_in[54]
0=level
21TYPE_117R/W0hType for slv_events_in[53]
0=level
20TYPE_116R/W0hType for slv_events_in[52]
0=level
19TYPE_115R/W0hType for slv_events_in[51]
0=level
18TYPE_114R/W0hType for slv_events_in[50]
0=level
17TYPE_113R/W0hType for slv_events_in[49]
0=level
16TYPE_112R/W0hType for slv_events_in[48]
0=level
15TYPE_111R/W0hType for slv_events_in[47]
0=level
14TYPE_110R/W0hType for slv_events_in[46]
0=level
13TYPE_109R/W0hType for slv_events_in[45]
0=level
12TYPE_108R/W0hType for slv_events_in[44]
0=level
11TYPE_107R/W0hType for slv_events_in[43]
0=level
10TYPE_106R/W0hType for slv_events_in[42]
0=level
9TYPE_105R/W0hType for slv_events_in[41]
0=level
8TYPE_104R/W0hType for slv_events_in[40]
0=level
7TYPE_103R/W0hType for slv_events_in[39]
0=level
6TYPE_102R/W0hType for slv_events_in[38]
0=level
5TYPE_101R/W0hType for slv_events_in[37]
0=level
4TYPE_100R/W0hType for slv_events_in[36]
0=level
3TYPE_99R/W0hType for slv_events_in[35]
0=level
2TYPE_98R/W0hType for slv_events_in[34]
0=level
1TYPE_97R/W0hType for slv_events_in[33]
0=level
0TYPE_96R/W0hType for slv_events_in[32]
0=level

4.14.7.106 ICSS_INTC_TYPE_REG4 Register (Offset = D90h) [reset = 0h]

ICSS_INTC_TYPE_REG4 is shown in Figure 6-507 and described in Table 6-995.

Return to Summary Table.

Type Register 4

Table 6-994 ICSS_INTC_TYPE_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 0D90h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 0D90h
Figure 6-507 ICSS_INTC_TYPE_REG4 Register
3130292827262524
TYPE_159TYPE_158TYPE_157TYPE_156TYPE_155TYPE_154TYPE_153TYPE_152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TYPE_151TYPE_150TYPE_149TYPE_148TYPE_147TYPE_146TYPE_145TYPE_144
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TYPE_143TYPE_142TYPE_141TYPE_140TYPE_139TYPE_138TYPE_137TYPE_136
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TYPE_135TYPE_134TYPE_133TYPE_132TYPE_131TYPE_130TYPE_129TYPE_128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-995 ICSS_INTC_TYPE_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31TYPE_159R/W0hType for slv_events_in[95]
0=level
30TYPE_158R/W0hType for slv_events_in[94]
0=level
29TYPE_157R/W0hType for slv_events_in[93]
0=level
28TYPE_156R/W0hType for slv_events_in[92]
0=level
27TYPE_155R/W0hType for slv_events_in[91]
0=level
26TYPE_154R/W0hType for slv_events_in[90]
0=level
25TYPE_153R/W0hType for slv_events_in[89]
0=level
24TYPE_152R/W0hType for slv_events_in[88]
0=level
23TYPE_151R/W0hType for slv_events_in[87]
0=level
22TYPE_150R/W0hType for slv_events_in[86]
0=level
21TYPE_149R/W0hType for slv_events_in[85]
0=level
20TYPE_148R/W0hType for slv_events_in[84]
0=level
19TYPE_147R/W0hType for slv_events_in[83]
0=level
18TYPE_146R/W0hType for slv_events_in[82]
0=level
17TYPE_145R/W0hType for slv_events_in[81]
0=level
16TYPE_144R/W0hType for slv_events_in[80]
0=level
15TYPE_143R/W0hType for slv_events_in[79]
0=level
14TYPE_142R/W0hType for slv_events_in[78]
0=level
13TYPE_141R/W0hType for slv_events_in[77]
0=level
12TYPE_140R/W0hType for slv_events_in[76]
0=level
11TYPE_139R/W0hType for slv_events_in[75]
0=level
10TYPE_138R/W0hType for slv_events_in[74]
0=level
9TYPE_137R/W0hType for slv_events_in[73]
0=level
8TYPE_136R/W0hType for slv_events_in[72]
0=level
7TYPE_135R/W0hType for slv_events_in[71]
0=level
6TYPE_134R/W0hType for slv_events_in[70]
0=level
5TYPE_133R/W0hType for slv_events_in[69]
0=level
4TYPE_132R/W0hType for slv_events_in[68]
0=level
3TYPE_131R/W0hType for slv_events_in[67]
0=level
2TYPE_130R/W0hType for slv_events_in[66]
0=level
1TYPE_129R/W0hType for slv_events_in[65]
0=level
0TYPE_128R/W0hType for slv_events_in[64]
0=level

4.14.7.107 ICSS_INTC_NEST_LEVEL_REG0 Register (Offset = 1100h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG0 is shown in Figure 6-508 and described in Table 6-997.

Return to Summary Table.

Host Int 0 Nesting Level Register

Table 6-996 ICSS_INTC_NEST_LEVEL_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1100h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1100h
Figure 6-508 ICSS_INTC_NEST_LEVEL_REG0 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_0
R/W-XR/W-100h
76543210
NEST_HINT_0
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-997 ICSS_INTC_NEST_LEVEL_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_0R/W100hHost Int 0 Nesting Level

4.14.7.108 ICSS_INTC_NEST_LEVEL_REG1 Register (Offset = 1104h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG1 is shown in Figure 6-509 and described in Table 6-999.

Return to Summary Table.

Host Int 1 Nesting Level Register

Table 6-998 ICSS_INTC_NEST_LEVEL_REG1 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1104h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1104h
Figure 6-509 ICSS_INTC_NEST_LEVEL_REG1 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_1
R/W-XR/W-100h
76543210
NEST_HINT_1
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-999 ICSS_INTC_NEST_LEVEL_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_1R/W100hHost Int 1 Nesting Level

4.14.7.109 ICSS_INTC_NEST_LEVEL_REG2 Register (Offset = 1108h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG2 is shown in Figure 6-510 and described in Table 6-1001.

Return to Summary Table.

Host Int 2 Nesting Level Register

Table 6-1000 ICSS_INTC_NEST_LEVEL_REG2 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1108h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1108h
Figure 6-510 ICSS_INTC_NEST_LEVEL_REG2 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_2
R/W-XR/W-100h
76543210
NEST_HINT_2
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1001 ICSS_INTC_NEST_LEVEL_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_2R/W100hHost Int 2 Nesting Level

4.14.7.110 ICSS_INTC_NEST_LEVEL_REG3 Register (Offset = 110Ch) [reset = X]

ICSS_INTC_NEST_LEVEL_REG3 is shown in Figure 6-511 and described in Table 6-1003.

Return to Summary Table.

Host Int 3 Nesting Level Register

Table 6-1002 ICSS_INTC_NEST_LEVEL_REG3 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 110Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 110Ch
Figure 6-511 ICSS_INTC_NEST_LEVEL_REG3 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_3
R/W-XR/W-100h
76543210
NEST_HINT_3
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1003 ICSS_INTC_NEST_LEVEL_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_3R/W100hHost Int 3 Nesting Level

4.14.7.111 ICSS_INTC_NEST_LEVEL_REG4 Register (Offset = 1110h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG4 is shown in Figure 6-512 and described in Table 6-1005.

Return to Summary Table.

Host Int 4 Nesting Level Register

Table 6-1004 ICSS_INTC_NEST_LEVEL_REG4 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1110h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1110h
Figure 6-512 ICSS_INTC_NEST_LEVEL_REG4 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_4
R/W-XR/W-100h
76543210
NEST_HINT_4
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1005 ICSS_INTC_NEST_LEVEL_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_4R/W100hHost Int 4 Nesting Level

4.14.7.112 ICSS_INTC_NEST_LEVEL_REG5 Register (Offset = 1114h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG5 is shown in Figure 6-513 and described in Table 6-1007.

Return to Summary Table.

Host Int 5 Nesting Level Register

Table 6-1006 ICSS_INTC_NEST_LEVEL_REG5 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1114h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1114h
Figure 6-513 ICSS_INTC_NEST_LEVEL_REG5 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_5
R/W-XR/W-100h
76543210
NEST_HINT_5
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1007 ICSS_INTC_NEST_LEVEL_REG5 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_5R/W100hHost Int 5 Nesting Level

4.14.7.113 ICSS_INTC_NEST_LEVEL_REG6 Register (Offset = 1118h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG6 is shown in Figure 6-514 and described in Table 6-1009.

Return to Summary Table.

Host Int 6 Nesting Level Register

Table 6-1008 ICSS_INTC_NEST_LEVEL_REG6 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1118h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1118h
Figure 6-514 ICSS_INTC_NEST_LEVEL_REG6 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_6
R/W-XR/W-100h
76543210
NEST_HINT_6
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1009 ICSS_INTC_NEST_LEVEL_REG6 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_6R/W100hHost Int 6 Nesting Level

4.14.7.114 ICSS_INTC_NEST_LEVEL_REG7 Register (Offset = 111Ch) [reset = X]

ICSS_INTC_NEST_LEVEL_REG7 is shown in Figure 6-515 and described in Table 6-1011.

Return to Summary Table.

Host Int 7 Nesting Level Register

Table 6-1010 ICSS_INTC_NEST_LEVEL_REG7 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 111Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 111Ch
Figure 6-515 ICSS_INTC_NEST_LEVEL_REG7 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_7
R/W-XR/W-100h
76543210
NEST_HINT_7
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1011 ICSS_INTC_NEST_LEVEL_REG7 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_7R/W100hHost Int 7 Nesting Level

4.14.7.115 ICSS_INTC_NEST_LEVEL_REG8 Register (Offset = 1120h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG8 is shown in Figure 6-516 and described in Table 6-1013.

Return to Summary Table.

Host Int 8 Nesting Level Register

Table 6-1012 ICSS_INTC_NEST_LEVEL_REG8 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1120h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1120h
Figure 6-516 ICSS_INTC_NEST_LEVEL_REG8 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_8
R/W-XR/W-100h
76543210
NEST_HINT_8
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1013 ICSS_INTC_NEST_LEVEL_REG8 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_8R/W100hHost Int 8 Nesting Level

4.14.7.116 ICSS_INTC_NEST_LEVEL_REG9 Register (Offset = 1124h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG9 is shown in Figure 6-517 and described in Table 6-1015.

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Host Int 9 Nesting Level Register

Table 6-1014 ICSS_INTC_NEST_LEVEL_REG9 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1124h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1124h
Figure 6-517 ICSS_INTC_NEST_LEVEL_REG9 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_9
R/W-XR/W-100h
76543210
NEST_HINT_9
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1015 ICSS_INTC_NEST_LEVEL_REG9 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_9R/W100hHost Int 9 Nesting Level

4.14.7.117 ICSS_INTC_NEST_LEVEL_REG10 Register (Offset = 1128h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG10 is shown in Figure 6-518 and described in Table 6-1017.

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Host Int 10 Nesting Level Register

Table 6-1016 ICSS_INTC_NEST_LEVEL_REG10 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1128h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1128h
Figure 6-518 ICSS_INTC_NEST_LEVEL_REG10 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_10
R/W-XR/W-100h
76543210
NEST_HINT_10
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1017 ICSS_INTC_NEST_LEVEL_REG10 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_10R/W100hHost Int 10 Nesting Level

4.14.7.118 ICSS_INTC_NEST_LEVEL_REG11 Register (Offset = 112Ch) [reset = X]

ICSS_INTC_NEST_LEVEL_REG11 is shown in Figure 6-519 and described in Table 6-1019.

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Host Int 11 Nesting Level Register

Table 6-1018 ICSS_INTC_NEST_LEVEL_REG11 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 112Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 112Ch
Figure 6-519 ICSS_INTC_NEST_LEVEL_REG11 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_11
R/W-XR/W-100h
76543210
NEST_HINT_11
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1019 ICSS_INTC_NEST_LEVEL_REG11 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_11R/W100hHost Int 11 Nesting Level

4.14.7.119 ICSS_INTC_NEST_LEVEL_REG12 Register (Offset = 1130h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG12 is shown in Figure 6-520 and described in Table 6-1021.

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Host Int 11 Nesting Level Register

Table 6-1020 ICSS_INTC_NEST_LEVEL_REG12 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1130h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1130h
Figure 6-520 ICSS_INTC_NEST_LEVEL_REG12 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_12
R/W-XR/W-100h
76543210
NEST_HINT_12
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1021 ICSS_INTC_NEST_LEVEL_REG12 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_12R/W100hHost Int 12 Nesting Level

4.14.7.120 ICSS_INTC_NEST_LEVEL_REG13 Register (Offset = 1134h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG13 is shown in Figure 6-521 and described in Table 6-1023.

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Host Int 11 Nesting Level Register

Table 6-1022 ICSS_INTC_NEST_LEVEL_REG13 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1134h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1134h
Figure 6-521 ICSS_INTC_NEST_LEVEL_REG13 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_13
R/W-XR/W-100h
76543210
NEST_HINT_13
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1023 ICSS_INTC_NEST_LEVEL_REG13 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_13R/W100hHost Int 13 Nesting Level

4.14.7.121 ICSS_INTC_NEST_LEVEL_REG14 Register (Offset = 1138h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG14 is shown in Figure 6-522 and described in Table 6-1025.

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Host Int 11 Nesting Level Register

Table 6-1024 ICSS_INTC_NEST_LEVEL_REG14 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1138h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1138h
Figure 6-522 ICSS_INTC_NEST_LEVEL_REG14 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_14
R/W-XR/W-100h
76543210
NEST_HINT_14
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1025 ICSS_INTC_NEST_LEVEL_REG14 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_14R/W100hHost Int 14 Nesting Level

4.14.7.122 ICSS_INTC_NEST_LEVEL_REG15 Register (Offset = 113Ch) [reset = X]

ICSS_INTC_NEST_LEVEL_REG15 is shown in Figure 6-523 and described in Table 6-1027.

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Host Int 11 Nesting Level Register

Table 6-1026 ICSS_INTC_NEST_LEVEL_REG15 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 113Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 113Ch
Figure 6-523 ICSS_INTC_NEST_LEVEL_REG15 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_15
R/W-XR/W-100h
76543210
NEST_HINT_15
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1027 ICSS_INTC_NEST_LEVEL_REG15 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_15R/W100hHost Int 15 Nesting Level

4.14.7.123 ICSS_INTC_NEST_LEVEL_REG16 Register (Offset = 1140h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG16 is shown in Figure 6-524 and described in Table 6-1029.

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Host Int 11 Nesting Level Register

Table 6-1028 ICSS_INTC_NEST_LEVEL_REG16 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1140h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1140h
Figure 6-524 ICSS_INTC_NEST_LEVEL_REG16 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_16
R/W-XR/W-100h
76543210
NEST_HINT_16
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1029 ICSS_INTC_NEST_LEVEL_REG16 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_16R/W100hHost Int 16 Nesting Level

4.14.7.124 ICSS_INTC_NEST_LEVEL_REG17 Register (Offset = 1144h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG17 is shown in Figure 6-525 and described in Table 6-1031.

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Host Int 11 Nesting Level Register

Table 6-1030 ICSS_INTC_NEST_LEVEL_REG17 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1144h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1144h
Figure 6-525 ICSS_INTC_NEST_LEVEL_REG17 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_17
R/W-XR/W-100h
76543210
NEST_HINT_17
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1031 ICSS_INTC_NEST_LEVEL_REG17 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_17R/W100hHost Int 17 Nesting Level

4.14.7.125 ICSS_INTC_NEST_LEVEL_REG18 Register (Offset = 1148h) [reset = X]

ICSS_INTC_NEST_LEVEL_REG18 is shown in Figure 6-526 and described in Table 6-1033.

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Host Int 11 Nesting Level Register

Table 6-1032 ICSS_INTC_NEST_LEVEL_REG18 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1148h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1148h
Figure 6-526 ICSS_INTC_NEST_LEVEL_REG18 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_18
R/W-XR/W-100h
76543210
NEST_HINT_18
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1033 ICSS_INTC_NEST_LEVEL_REG18 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_18R/W100hHost Int 18 Nesting Level

4.14.7.126 ICSS_INTC_NEST_LEVEL_REG19 Register (Offset = 114Ch) [reset = X]

ICSS_INTC_NEST_LEVEL_REG19 is shown in Figure 6-527 and described in Table 6-1035.

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Host Int 11 Nesting Level Register

Table 6-1034 ICSS_INTC_NEST_LEVEL_REG19 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 114Ch
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 114Ch
Figure 6-527 ICSS_INTC_NEST_LEVEL_REG19 Register
3130292827262524
NEST_AUTO_OVRRESERVED
W-XR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDNEST_HINT_19
R/W-XR/W-100h
76543210
NEST_HINT_19
R/W-100h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 6-1035 ICSS_INTC_NEST_LEVEL_REG19 Register Field Descriptions
BitFieldTypeResetDescription
31NEST_AUTO_OVRWXNesting Level Override Automatic
30-9RESERVEDR/WX
8-0NEST_HINT_19R/W100hHost Int 19 Nesting Level

4.14.7.127 ICSS_INTC_ENABLE_HINT_REG0 Register (Offset = 1500h) [reset = X]

ICSS_INTC_ENABLE_HINT_REG0 is shown in Figure 6-528 and described in Table 6-1037.

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Host Int Enable Register 0

Table 6-1036 ICSS_INTC_ENABLE_HINT_REG0 Instances
InstancePhysical Address
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV3002 1500h
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV300A 1500h
Figure 6-528 ICSS_INTC_ENABLE_HINT_REG0 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDENABLE_HINT_19ENABLE_HINT_18ENABLE_HINT_17ENABLE_HINT_16
R/W-XR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
ENABLE_HINT_15ENABLE_HINT_14ENABLE_HINT_13ENABLE_HINT_12ENABLE_HINT_11ENABLE_HINT_10ENABLE_HINT_9ENABLE_HINT_8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ENABLE_HINT_7ENABLE_HINT_6ENABLE_HINT_5ENABLE_HINT_4ENABLE_HINT_3ENABLE_HINT_2ENABLE_HINT_1ENABLE_HINT_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 6-1037 ICSS_INTC_ENABLE_HINT_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19ENABLE_HINT_19R/W0hEnable for Host Int 19
18ENABLE_HINT_18R/W0hEnable for Host Int 18
17ENABLE_HINT_17R/W0hEnable for Host Int 17
16ENABLE_HINT_16R/W0hEnable for Host Int 16
15ENABLE_HINT_15R/W0hEnable for Host Int 15
14ENABLE_HINT_14R/W0hEnable for Host Int 14
13ENABLE_HINT_13R/W0hEnable for Host Int 13
12ENABLE_HINT_12R/W0hEnable for Host Int 12
11ENABLE_HINT_11R/W0hEnable for Host Int 11
10ENABLE_HINT_10R/W0hEnable for Host Int 10
9ENABLE_HINT_9R/W0hEnable for Host Int 9
8ENABLE_HINT_8R/W0hEnable for Host Int 8
7ENABLE_HINT_7R/W0hEnable for Host Int 7
6ENABLE_HINT_6R/W0hEnable for Host Int 6
5ENABLE_HINT_5R/W0hEnable for Host Int 5
4ENABLE_HINT_4R/W0hEnable for Host Int 4
3ENABLE_HINT_3R/W0hEnable for Host Int 3
2ENABLE_HINT_2R/W0hEnable for Host Int 2
1ENABLE_HINT_1R/W0hEnable for Host Int 1
0ENABLE_HINT_0R/W0hEnable for Host Int 0