SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-1823, Table 6-1824, Table 6-1825, Table 6-1826, Table 6-1827, and Table 6-1828 list the memory-mapped registers for the PRU_TASKS_MGR_TASKS_MGR_PRU0, PRU_TASKS_MGR_TASKS_MGR_RTU0, PRU_TASKS_MGR_TASKS_MGR_PRU1, PRU_TASKS_MGR_TASKS_MGR_RTU1, PRU_TASKS_MGR_TASKS_MGR_PRU_TX0 and PRU_TASKS_MGR_TASKS_MGR_PRU_TX1. All register offset addresses not listed in Table 6-1823 to Table 6-1828 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A000h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A000h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A100h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A100h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A200h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A200h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A300h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A300h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR Physical Address | PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR_MMR Physical Address |
---|---|---|---|---|
0h | TASKS_MGR_GLOBAL_CFG | Global Configuration | 3002 A000h | 300A A000h |
4h | TASKS_MGR_GLOBAL_STATUS | Global Status | 3002 A004h | 300A A004h |
8h | TASKS_MGR_TS1_PC_S0 | Task1 Subroutine0 PC | 3002 A008h | 300A A008h |
Ch | TASKS_MGR_TS1_PC_S1 | Task1 Subroutine1 PC | 3002 A00Ch | 300A A00Ch |
10h | TASKS_MGR_TS1_PC_S2 | Task1 Subroutine2 PC | 3002 A010h | 300A A010h |
14h | TASKS_MGR_TS1_PC_S3 | Task1 Subroutine3 PC | 3002 A014h | 300A A014h |
18h | TASKS_MGR_TS1_PC_S4 | Task1 Subroutine4 PC | 3002 A018h | 300A A018h |
1Ch | TASKS_MGR_TS2_PC_S0 | Task2 Subroutine0 PC | 3002 A01Ch | 300A A01Ch |
20h | TASKS_MGR_TS2_PC_S1 | Task2 Subroutine1 PC | 3002 A020h | 300A A020h |
24h | TASKS_MGR_TS2_PC_S2 | Task2 Subroutine2 PC | 3002 A024h | 300A A024h |
28h | TASKS_MGR_TS2_PC_S3 | Task2 Subroutine3 PC | 3002 A028h | 300A A028h |
2Ch | TASKS_MGR_TS2_PC_S4 | Task2 Subroutine4 PC | 3002 A02Ch | 300A A02Ch |
30h | TASKS_MGR_RX_CFG | RX Configuration | 3002 A030h | 300A A030h |
34h | TASKS_MGR_TX_CFG | TX Configuration | 3002 A034h | 300A A034h |
38h | TASKS_MGR_TS1_GEN_CFG1 | Generic TS1 Configuration1 | 3002 A038h | 300A A038h |
3Ch | TASKS_MGR_TS1_GEN_CFG2 | Generic TS1 Configuration2 | 3002 A03Ch | 300A A03Ch |
40h | TASKS_MGR_TS2_GEN_CFG1 | Generic TS2 Configuration1 | 3002 A040h | 300A A040h |
44h | TASKS_MGR_TS2_GEN_CFG2 | Generic TS2 Configuration2 | 3002 A044h | 300A A044h |
48h | TASKS_MGR_CAP_EN_CFG | Enable Capture new Event Configuration | 3002 A048h | 300A A048h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR Physical Address | PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR Physical Address |
---|---|---|---|---|
0h | TASKS_MGR_GLOBAL_CFG | Global Configuration | 3002 A100h | 300A A100h |
4h | TASKS_MGR_GLOBAL_STATUS | Global Status | 3002 A104h | 300A A104h |
8h | TASKS_MGR_TS1_PC_S0 | Task1 Subroutine0 PC | 3002 A108h | 300A A108h |
Ch | TASKS_MGR_TS1_PC_S1 | Task1 Subroutine1 PC | 3002 A10Ch | 300A A10Ch |
10h | TASKS_MGR_TS1_PC_S2 | Task1 Subroutine2 PC | 3002 A110h | 300A A110h |
14h | TASKS_MGR_TS1_PC_S3 | Task1 Subroutine3 PC | 3002 A114h | 300A A114h |
18h | TASKS_MGR_TS1_PC_S4 | Task1 Subroutine4 PC | 3002 A118h | 300A A118h |
1Ch | TASKS_MGR_TS2_PC_S0 | Task2 Subroutine0 PC | 3002 A11Ch | 300A A11Ch |
20h | TASKS_MGR_TS2_PC_S1 | Task2 Subroutine1 PC | 3002 A120h | 300A A120h |
24h | TASKS_MGR_TS2_PC_S2 | Task2 Subroutine2 PC | 3002 A124h | 300A A124h |
28h | TASKS_MGR_TS2_PC_S3 | Task2 Subroutine3 PC | 3002 A128h | 300A A128h |
2Ch | TASKS_MGR_TS2_PC_S4 | Task2 Subroutine4 PC | 3002 A12Ch | 300A A12Ch |
30h | TASKS_MGR_RX_CFG | RX Configuration | 3002 A130h | 300A A130h |
34h | TASKS_MGR_TX_CFG | TX Configuration | 3002 A134h | 300A A134h |
38h | TASKS_MGR_TS1_GEN_CFG1 | Generic TS1 Configuration1 | 3002 A138h | 300A A138h |
3Ch | TASKS_MGR_TS1_GEN_CFG2 | Generic TS1 Configuration2 | 3002 A13Ch | 300A A13Ch |
40h | TASKS_MGR_TS2_GEN_CFG1 | Generic TS2 Configuration1 | 3002 A140h | 300A A140h |
44h | TASKS_MGR_TS2_GEN_CFG2 | Generic TS2 Configuration2 | 3002 A144h | 300A A144h |
48h | TASKS_MGR_CAP_EN_CFG | Enable Capture new Event Configuration | 3002 A148h | 300A A148h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR Physical Address | PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR Physical Address |
---|---|---|---|---|
0h | TASKS_MGR_GLOBAL_CFG | Global Configuration | 3002 A200h | 300A A200h |
4h | TASKS_MGR_GLOBAL_STATUS | Global Status | 3002 A204h | 300A A204h |
8h | TASKS_MGR_TS1_PC_S0 | TS1 Sub0 PC | 3002 A208h | 300A A208h |
Ch | TASKS_MGR_TS1_PC_S1 | TS1 Sub1 PC | 3002 A20Ch | 300A A20Ch |
10h | TASKS_MGR_TS1_PC_S2 | TS1 Sub2 PC | 3002 A210h | 300A A210h |
14h | TASKS_MGR_TS1_PC_S3 | TS1 Sub3 PC | 3002 A214h | 300A A214h |
18h | TASKS_MGR_TS1_PC_S4 | TS1 Sub4 PC | 3002 A218h | 300A A218h |
1Ch | TASKS_MGR_TS2_PC_S0 | TS2 Sub0 PC | 3002 A21Ch | 300A A21Ch |
20h | TASKS_MGR_TS2_PC_S1 | TS2 Sub1 PC | 3002 A220h | 300A A220h |
24h | TASKS_MGR_TS2_PC_S2 | TS2 Sub2 PC | 3002 A224h | 300A A224h |
28h | TASKS_MGR_TS2_PC_S3 | TS2 Sub3 PC | 3002 A228h | 300A A228h |
2Ch | TASKS_MGR_TS2_PC_S4 | TS2 Sub4 PC | 3002 A22Ch | 300A A22Ch |
30h | TASKS_MGR_RX_CFG | RX Configuration | 3002 A230h | 300A A230h |
34h | TASKS_MGR_TX_CFG | TX Configuration | 3002 A234h | 300A A234h |
38h | TASKS_MGR_TS1_GEN_CFG1 | Generic TS1 Configuration1 | 3002 A238h | 300A A238h |
3Ch | TASKS_MGR_TS1_GEN_CFG2 | Generic TS1 Configuration2 | 3002 A23Ch | 300A A23Ch |
40h | TASKS_MGR_TS2_GEN_CFG1 | Generic TS2 Configuration1 | 3002 A240h | 300A A240h |
44h | TASKS_MGR_TS2_GEN_CFG2 | Generic TS2 Configuration2 | 3002 A244h | 300A A244h |
48h | TASKS_MGR_CAP_EN_CFG | Enable capture new event cfg | 3002 A248h | 300A A248h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR Physical Address | PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR Physical Address |
---|---|---|---|---|
0h | TASKS_MGR_GLOBAL_CFG | Global Configuration | 3002 A300h | 300A A300h |
4h | TASKS_MGR_GLOBAL_STATUS | Global Status | 3002 A304h | 300A A304h |
8h | TASKS_MGR_TS1_PC_S0 | Task1 Subroutine0 PC | 3002 A308h | 300A A308h |
Ch | TASKS_MGR_TS1_PC_S1 | Task1 Subroutine1 PC | 3002 A30Ch | 300A A30Ch |
10h | TASKS_MGR_TS1_PC_S2 | Task1 Subroutine2 PC | 3002 A310h | 300A A310h |
14h | TASKS_MGR_TS1_PC_S3 | Task1 Subroutine3 PC | 3002 A314h | 300A A314h |
18h | TASKS_MGR_TS1_PC_S4 | Task1 Subroutine4 PC | 3002 A318h | 300A A318h |
1Ch | TASKS_MGR_TS2_PC_S0 | Task2 Subroutine0 PC | 3002 A31Ch | 300A A31Ch |
20h | TASKS_MGR_TS2_PC_S1 | Task2 Subroutine1 PC | 3002 A320h | 300A A320h |
24h | TASKS_MGR_TS2_PC_S2 | Task2 Subroutine2 PC | 3002 A324h | 300A A324h |
28h | TASKS_MGR_TS2_PC_S3 | Task2 Subroutine3 PC | 3002 A328h | 300A A328h |
2Ch | TASKS_MGR_TS2_PC_S4 | Task2 Subroutine4 PC | 3002 A32Ch | 300A A32Ch |
30h | TASKS_MGR_RX_CFG | RX Configuration | 3002 A330h | 300A A330h |
34h | TASKS_MGR_TX_CFG | TX Configuration | 3002 A334h | 300A A334h |
38h | TASKS_MGR_TS1_GEN_CFG1 | Generic TS1 Configuration1 | 3002 A338h | 300A A338h |
3Ch | TASKS_MGR_TS1_GEN_CFG2 | Generic TS1 Configuration2 | 3002 A33Ch | 300A A33Ch |
40h | TASKS_MGR_TS2_GEN_CFG1 | Generic TS2 Configuration1 | 3002 A340h | 300A A340h |
44h | TASKS_MGR_TS2_GEN_CFG2 | Generic TS2 Configuration2 | 3002 A344h | 300A A344h |
48h | TASKS_MGR_CAP_EN_CFG | Enable Capture new Event Configuration | 3002 A348h | 300A A348h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR Physical Address | PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR Physical Address |
---|---|---|---|---|
0h | TASKS_MGR_GLOBAL_CFG | Global Configuration | 3002 A400h | 300A A400h |
4h | TASKS_MGR_GLOBAL_STATUS | Global Status | 3002 A404h | 300A A404h |
8h | TASKS_MGR_TS1_PC_S0 | Task1 Subroutine0 PC | 3002 A408h | 300A A408h |
Ch | TASKS_MGR_TS1_PC_S1 | Task1 Subroutine1 PC | 3002 A40Ch | 300A A40Ch |
10h | TASKS_MGR_TS1_PC_S2 | Task1 Subroutine2 PC | 3002 A410h | 300A A410h |
14h | TASKS_MGR_TS1_PC_S3 | Task1 Subroutine3 PC | 3002 A414h | 300A A414h |
18h | TASKS_MGR_TS1_PC_S4 | Task1 Subroutine4 PC | 3002 A418h | 300A A418h |
1Ch | TASKS_MGR_TS2_PC_S0 | Task2 Subroutine0 PC | 3002 A41Ch | 300A A41Ch |
20h | TASKS_MGR_TS2_PC_S1 | Task2 Subroutine1 PC | 3002 A420h | 300A A420h |
24h | TASKS_MGR_TS2_PC_S2 | Task2 Subroutine2 PC | 3002 A424h | 300A A424h |
28h | TASKS_MGR_TS2_PC_S3 | Task2 Subroutine3 PC | 3002 A428h | 300A A428h |
2Ch | TASKS_MGR_TS2_PC_S4 | Task2 Subroutine4 PC | 3002 A42Ch | 300A A42Ch |
30h | TASKS_MGR_RX_CFG | RX Configuration | 3002 A430h | 300A A430h |
34h | TASKS_MGR_TX_CFG | TX Configuration | 3002 A434h | 300A A434h |
38h | TASKS_MGR_TS1_GEN_CFG1 | Generic TS1 Configuration1 | 3002 A438h | 300A A438h |
3Ch | TASKS_MGR_TS1_GEN_CFG2 | Generic TS1 Configuration2 | 3002 A43Ch | 300A A43Ch |
40h | TASKS_MGR_TS2_GEN_CFG1 | Generic TS2 Configuration1 | 3002 A440h | 300A A440h |
44h | TASKS_MGR_TS2_GEN_CFG2 | Generic TS2 Configuration2 | 3002 A444h | 300A A444h |
48h | TASKS_MGR_CAP_EN_CFG | Enable Capture new Event Configuration | 3002 A448h | 300A A448h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR Physical Address | PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR Physical Address |
---|---|---|---|---|
0h | TASKS_MGR_GLOBAL_CFG | Global Configuration | 3002 A500h | 300A A500h |
4h | TASKS_MGR_GLOBAL_STATUS | Global Status | 3002 A504h | 300A A504h |
8h | TASKS_MGR_TS1_PC_S0 | Task1 Subroutine0 PC | 3002 A508h | 300A A508h |
Ch | TASKS_MGR_TS1_PC_S1 | Task1 Subroutine1 PC | 3002 A50Ch | 300A A50Ch |
10h | TASKS_MGR_TS1_PC_S2 | Task1 Subroutine2 PC | 3002 A510h | 300A A510h |
14h | TASKS_MGR_TS1_PC_S3 | Task1 Subroutine3 PC | 3002 A514h | 300A A514h |
18h | TASKS_MGR_TS1_PC_S4 | Task1 Subroutine4 PC | 3002 A518h | 300A A518h |
1Ch | TASKS_MGR_TS2_PC_S0 | Task2 Subroutine0 PC | 3002 A51Ch | 300A A51Ch |
20h | TASKS_MGR_TS2_PC_S1 | Task2 Subroutine1 PC | 3002 A520h | 300A A520h |
24h | TASKS_MGR_TS2_PC_S2 | Task2 Subroutine2 PC | 3002 A524h | 300A A524h |
28h | TASKS_MGR_TS2_PC_S3 | Task2 Subroutine3 PC | 3002 A528h | 300A A528h |
2Ch | TASKS_MGR_TS2_PC_S4 | Task2 Subroutine4 PC | 3002 A52Ch | 300A A52Ch |
30h | TASKS_MGR_RX_CFG | RX Configuration | 3002 A530h | 300A A530h |
34h | TASKS_MGR_TX_CFG | TX Configuration | 3002 A534h | 300A A534h |
38h | TASKS_MGR_TS1_GEN_CFG1 | Generic TS1 Configuration1 | 3002 A538h | 300A A538h |
3Ch | TASKS_MGR_TS1_GEN_CFG2 | Generic TS1 Configuration2 | 3002 A53Ch | 300A A53Ch |
40h | TASKS_MGR_TS2_GEN_CFG1 | Generic TS2 Configuration1 | 3002 A540h | 300A A540h |
44h | TASKS_MGR_TS2_GEN_CFG2 | Generic TS2 Configuration2 | 3002 A544h | 300A A544h |
48h | TASKS_MGR_CAP_EN_CFG | Enable Capture new Event Configuration | 3002 A548h | 300A A548h |
TASKS_MGR_GLOBAL_CFG is shown in Figure 6-910 and described in Table 6-1830.
Return to Summary Table.
Global Configuration
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A000h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A000h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A100h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A100h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A200h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A200h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A300h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A300h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TS2_EN_S4 | TS2_EN_S3 | TS2_EN_S2 | TS2_EN_S1 | |||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS2_EN_S0 | TS1_EN_S4 | TS1_EN_S3 | TS1_EN_S2 | TS1_EN_S1 | TS1_EN_S0 | TASKS_MGR_MODE | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | X | |
11 | TS2_EN_S4 | R/W | 0h | TS2 Sub4 0: Disabled 1: Enabled |
10 | TS2_EN_S3 | R/W | 0h | TS2 Sub3 0: Disabled 1: Enabled |
9 | TS2_EN_S2 | R/W | 0h | TS2 Sub2 0: Disabled 1: Enabled |
8 | TS2_EN_S1 | R/W | 0h | TS2 Sub1 0: Disabled 1: Enabled |
7 | TS2_EN_S0 | R/W | 0h | TS2 Sub0 0: Disabled 1: Enabled |
6 | TS1_EN_S4 | R/W | 0h | TS1 Sub4 0: Disabled 1: Enabled |
5 | TS1_EN_S3 | R/W | 0h | TS1 Sub3 0: Disabled 1: Enabled |
4 | TS1_EN_S2 | R/W | 0h | TS1 Sub2 0: Disabled 1: Enabled |
3 | TS1_EN_S1 | R/W | 0h | TS1 Sub1 0: Disabled 1: Enabled |
2 | TS1_EN_S0 | R/W | 0h | TS1 Sub0 0: Disabled 1: Enabled |
1-0 | TASKS_MGR_MODE | R/W | 0h | TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW |
TASKS_MGR_GLOBAL_STATUS is shown in Figure 6-911 and described in Table 6-1832.
Return to Summary Table.
Global Status
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A004h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A004h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A104h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A104h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A204h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A204h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A304h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A304h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TS2_SUB_PEND_4 | TS2_SUB_PEND_3 | |||||
R-X | R-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TS2_SUB_PEND_2 | TS2_SUB_PEND_1 | TS2_SUB_PEND_0 | TS1_SUB_PEND_4 | TS1_SUB_PEND_3 | TS1_SUB_PEND_2 | TS1_SUB_PEND_1 | TS1_SUB_PEND_0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS2_STATE | TS1_STATE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | X | |
17 | TS2_SUB_PEND_4 | R | 0h | Task2 Sub4 Pend State |
16 | TS2_SUB_PEND_3 | R | 0h | Task2 Sub3 Pend State |
15 | TS2_SUB_PEND_2 | R | 0h | Task2 Sub2 Pend State |
14 | TS2_SUB_PEND_1 | R | 0h | Task2 Sub1 Pend State |
13 | TS2_SUB_PEND_0 | R | 0h | Task2 Sub0 Pend State |
12 | TS1_SUB_PEND_4 | R | 0h | Task1 Sub4 Pend State |
11 | TS1_SUB_PEND_3 | R | 0h | Task1 Sub3 Pend State |
10 | TS1_SUB_PEND_2 | R | 0h | Task1 Sub2 Pend State |
9 | TS1_SUB_PEND_1 | R | 0h | Task1 Sub1 Pend State |
8 | TS1_SUB_PEND_0 | R | 0h | Task1 Sub0 Pend State |
7-4 | TS2_STATE | R | 0h |
Indicates the sub-tasks of Task2 State 4b'0000 = TS2_Idle 4b'0001 = TS2_S0 4b'0010 = TS2_S1 4b'0011 = TS2_S2 4b'0100 = TS2_S3 4b'0101 = TS2_S4 4b'0110...4b'1111 = Reserved |
3-0 | TS1_STATE | R | 0h |
Indicates the sub-tasks of Task1 State 4b'0000 = TS1_Idle 4b'0001 = TS1_S0 4b'0010 = TS1_S1 4b'0011 = TS1_S2 4b'0100 = TS1_S3 4b'0101 = TS1_S4 4b'0110...4b'1111 = Reserved |
TASKS_MGR_TS1_PC_S0 is shown in Figure 6-912 and described in Table 6-1834.
Return to Summary Table.
TS1 Sub0 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A008h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A008h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A108h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A108h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A208h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A208h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A308h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A308h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS1_PC_S0 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS1_PC_S0 | R/W | 0h | TS1 Sub0 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS1_PC_S1 is shown in Figure 6-913 and described in Table 6-1836.
Return to Summary Table.
TS1 Sub1 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A00Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A00Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A10Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A10Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A20Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A20Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A30Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A30Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS1_PC_S1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS1_PC_S1 | R/W | 0h | TS1 Sub1 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS1_PC_S2 is shown in Figure 6-914 and described in Table 6-1838.
Return to Summary Table.
TS1 Sub2 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A010h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A010h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A110h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A110h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A210h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A210h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A310h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A310h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS1_PC_S2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS1_PC_S2 | R/W | 0h | TS1 Sub2 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS1_PC_S3 is shown in Figure 6-915 and described in Table 6-1840.
Return to Summary Table.
TS1 Sub3 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A014h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A014h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A114h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A114h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A214h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A214h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A314h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A314h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS1_PC_S3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS1_PC_S3 | R/W | 0h | TS1 Sub3 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS1_PC_S4 is shown in Figure 6-916 and described in Table 6-1842.
Return to Summary Table.
TS1 Sub4 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A018h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A018h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A118h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A118h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A218h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A218h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A318h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A318h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS1_PC_S4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS1_PC_S4 | R/W | 0h | TS1 Sub4 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS2_PC_S0 is shown in Figure 6-917 and described in Table 6-1844.
Return to Summary Table.
TS2 Sub0 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A01Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A01Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A11Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A11Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A21Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A21Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A31Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A31Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS2_PC_S0 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS2_PC_S0 | R/W | 0h | TS2 Sub0 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS2_PC_S1 is shown in Figure 6-918 and described in Table 6-1846.
Return to Summary Table.
TS2 Sub1 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A020h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A020h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A120h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A120h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A220h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A220h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A320h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A320h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS2_PC_S1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS2_PC_S1 | R/W | 0h | TS2 Sub1 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS2_PC_S2 is shown in Figure 6-919 and described in Table 6-1848.
Return to Summary Table.
TS2 Sub2 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A024h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A024h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A124h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A124h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A224h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A224h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A324h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A324h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS2_PC_S2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS2_PC_S2 | R/W | 0h | TS2 Sub2 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS2_PC_S3 is shown in Figure 6-920 and described in Table 6-1850.
Return to Summary Table.
TS2 Sub3 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A028h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A028h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A128h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A128h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A228h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A228h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A328h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A328h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS2_PC_S3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS2_PC_S3 | R/W | 0h | TS2 Sub3 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_TS2_PC_S4 is shown in Figure 6-921 and described in Table 6-1852.
Return to Summary Table.
TS2 Sub4 PC
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A02Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A02Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A12Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A12Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A22Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A22Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A32Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A32Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS2_PC_S4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TS2_PC_S4 | R/W | 0h | TS2 Sub4 Program Counter (function pointer in code word units i.e function offset in byte address/4) |
TASKS_MGR_RX_CFG is shown in Figure 6-922 and described in Table 6-1854.
Return to Summary Table.
RX Configuration
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A030h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A030h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A130h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A130h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A230h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A230h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A330h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A330h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BKN_SIZE | BK2_SIZE | BK1_SIZE | ||||||||||||
R/W-X | R/W-1Fh | R/W-1Fh | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | X | |
14-10 | BKN_SIZE | R/W | 1Fh | RX BKN Size, After BK1 and BK2, then after another 1 to 32 Bytes |
9-5 | BK2_SIZE | R/W | 1Fh | RX BK2 Size, The Second 1 to 32 Bytes trigger |
4-0 | BK1_SIZE | R/W | 1Fh | RX BK1 Size, The first 1 to 32 Bytes trigger |
TASKS_MGR_TX_CFG is shown in Figure 6-923 and described in Table 6-1856.
Return to Summary Table.
TX Configuration
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A034h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A034h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A134h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A134h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A234h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A234h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A334h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A334h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_WM | ||||||||||||||||||||||||||||||
R/W-X | R/W-1Fh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | X | |
5-0 | TX_WM | R/W | 1Fh | TX L2 Water Mark Level 1 to 64 Bytes |
TASKS_MGR_TS1_GEN_CFG1 is shown in Figure 6-924 and described in Table 6-1858.
Return to Summary Table.
Generic TS1 Configuration1
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A038h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A038h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A138h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A138h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A238h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A238h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A338h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A338h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TS1_GEN_S3_MX | TS1_GEN_S2_MX | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS1_GEN_S1_MX | TS1_GEN_S0_MX | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TS1_GEN_S3_MX | R/W | 0h | TS1 Generic Sub3 MX Select |
23-16 | TS1_GEN_S2_MX | R/W | 0h | TS1 Generic Sub2 MX Select |
15-8 | TS1_GEN_S1_MX | R/W | 0h | TS1 Generic Sub1 MX Select |
7-0 | TS1_GEN_S0_MX | R/W | 0h | TS1 Generic Sub0 MX Select |
TASKS_MGR_TS1_GEN_CFG2 is shown in Figure 6-925 and described in Table 6-1860.
Return to Summary Table.
Generic TS1 Configuration2
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A03Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A03Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A13Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A13Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A23Ch |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A23Ch |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A33Ch |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A33Ch |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS1_GEN_S4_MX | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | TS1_GEN_S4_MX | R/W | 0h | TS1 Generic Sub4 MX Select |
TASKS_MGR_TS2_GEN_CFG1 is shown in Figure 6-926 and described in Table 6-1862.
Return to Summary Table.
Generic TS2 Configuration1
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A040h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A040h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A140h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A140h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A240h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A240h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A340h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A340h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TS2_GEN_S3_MX | TS2_GEN_S2_MX | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS2_GEN_S1_MX | TS2_GEN_S0_MX | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TS2_GEN_S3_MX | R/W | 0h | TS2 Generic Sub3 MX Select |
23-16 | TS2_GEN_S2_MX | R/W | 0h | TS2 Generic Sub2 MX Select |
15-8 | TS2_GEN_S1_MX | R/W | 0h | TS2 Generic Sub1 MX Select |
7-0 | TS2_GEN_S0_MX | R/W | 0h | TS2 Generic Sub0 MX Select |
TASKS_MGR_TS2_GEN_CFG2 is shown in Figure 6-927 and described in Table 6-1864.
Return to Summary Table.
Generic TS2 Configuration2
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A044h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A044h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A144h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A144h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A244h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A244h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A344h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A344h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS2_GEN_S4_MX | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | TS2_GEN_S4_MX | R/W | 0h | TS2 Generic Sub4 MX Select |
TASKS_MGR_CAP_EN_CFG is shown in Figure 6-928 and described in Table 6-1866.
Return to Summary Table.
This register allows you to enable a capture of a new event when you are active in the sub task. By default, all new events to the same active task are masked until you exit that sub task from being captured When disabled (reset state). All new events to the current active task are masked from being captured. Only when this task is completed a new event can get captured for that task. When enabled, a new event which occurs in a current active task will get captured, when that task yields it will reenter that same task if not other higher priority events are pending
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 3002 A048h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR | 300A A048h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 3002 A148h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR | 300A A148h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 3002 A248h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR | 300A A248h |
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 3002 A348h |
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR | 300A A348h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 3002 A400h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR | 300A A400h |
PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 3002 A500h |
PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR | 300A A500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAP_NEW_TS1_EN_S4 | CAP_NEW_TS1_EN_S3 | CAP_NEW_TS1_EN_S2 | CAP_NEW_TS1_EN_S1 | CAP_NEW_TS1_EN_S0 | ||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | CAP_NEW_TS1_EN_S4 | R/W | 0h | Capture new event enable. TS1 Sub4. |
3 | CAP_NEW_TS1_EN_S3 | R/W | 0h | Capture new event enable. TS1 Sub3. |
2 | CAP_NEW_TS1_EN_S2 | R/W | 0h | Capture new event enable. TS1 Sub2. |
1 | CAP_NEW_TS1_EN_S1 | R/W | 0h | Capture new event enable. TS1 Sub1. |
0 | CAP_NEW_TS1_EN_S0 | R/W | 0h | Capture new event enable. TS1 Sub0. |