SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_VINT_enable_set_j | Interrupt Enable Set Register | 4800 0000h+ Formula |
8h+ Formula | 64 | DMASS0_INTAGGR_0_VINT_enable_clear_j | Interrupt Enable Clear Register | 4800 0008h+ Formula |
10h+ Formula | 64 | DMASS0_INTAGGR_0_VINT_status_set_j | Interrupt Status Set Register | 4800 0010h+ Formula |
18h+ Formula | 64 | DMASS0_INTAGGR_0_VINT_status_clear_j | Interrupt Status Clear Register | 4800 0018h+ Formula |
20h+ Formula | 64 | DMASS0_INTAGGR_0_VINT_statusm_j | Interrupt Masked Status Register | 4800 0020h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_ENTRY_imap_j | Interrupt Mapping Register | 4810 0000h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h | 64 | DMASS0_INTAGGR_0_revision | Revision Register | 4811 0000h |
8h | 64 | DMASS0_INTAGGR_0_intcap | Interrupt Capabilities | 4811 0008h |
10h | 64 | DMASS0_INTAGGR_0_auxcap | Auxiliary Capabilities | 4811 0010h |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_levi_map_j | Local to global event mapping | 4812 0000h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_uentry0_map_j | Unmapped Event Mapping Register | 4818 0000h+ Formula |
8000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry1_map_j | Unmapped Event Mapping Register | 4818 8000h+ Formula |
9000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry2_map_j | Unmapped Event Mapping Register | 4818 9000h+ Formula |
A000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry3_map_j | Unmapped Event Mapping Register | 4818 A000h+ Formula |
B000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry4_map_j | Unmapped Event Mapping Register | 4818 B000h+ Formula |
C000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry5_map_j | Unmapped Event Mapping Register | 4818 C000h+ Formula |
D000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry6_map_j | Unmapped Event Mapping Register | 4818 D000h+ Formula |
10000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry7_map_j | Unmapped Event Mapping Register | 4819 0000h+ Formula |
11000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry8_map_j | Unmapped Event Mapping Register | 4819 1000h+ Formula |
12000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry9_map_j | Unmapped Event Mapping Register | 4819 2000h+ Formula |
13000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry10_map_j | Unmapped Event Mapping Register | 4819 3000h+ Formula |
14000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry11_map_j | Unmapped Event Mapping Register | 4819 4000h+ Formula |
15000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry12_map_j | Unmapped Event Mapping Register | 4819 5000h+ Formula |
16000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry13_map_j | Unmapped Event Mapping Register | 4819 6000h+ Formula |
17000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry14_map_j | Unmapped Event Mapping Register | 4819 7000h+ Formula |
18000h+ Formula | 64 | DMASS0_INTAGGR_0_uentry15_map_j | Unmapped Event Mapping Register | 4819 8000h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_gevi_mcmap_j | Multicast event mapping | 4821 0000h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_gevi_map_j | Gobal Event Mapping Register | 4822 0000h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_INTAGGR_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 64 | DMASS0_INTAGGR_0_gevi_count_j | ETL Count Register | 4A00 0000h+ Formula |
Short Description: Interrupt Enable Set Register
Long Description:
Return to Summary Table
Offset = 0h + (j * 1000h); where j = 0h to B7h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4800 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
INTR_ENABLE | |||||||||||||||
R/W1TS | |||||||||||||||
0 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
INTR_ENABLE | |||||||||||||||
R/W1TS | |||||||||||||||
0 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INTR_ENABLE | |||||||||||||||
R/W1TS | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_ENABLE | |||||||||||||||
R/W1TS | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 - 0 | INTR_ENABLE | R/W1TS | 0h | Interrupt enable set value. On writes, set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register. |
Short Description: Interrupt Enable Clear Register
Long Description:
Return to Summary Table
Offset = 8h + (j * 1000h); where j = 0h to B7h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4800 0008h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
INTR_ENABLE | |||||||||||||||
R/W1TC | |||||||||||||||
0 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
INTR_ENABLE | |||||||||||||||
R/W1TC | |||||||||||||||
0 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INTR_ENABLE | |||||||||||||||
R/W1TC | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_ENABLE | |||||||||||||||
R/W1TC | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 - 0 | INTR_ENABLE | R/W1TC | 0h | Interrupt enable clear value. On writes, set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register. |
Short Description: Interrupt Status Set Register
Long Description:
Return to Summary Table
Offset = 10h + (j * 1000h); where j = 0h to B7h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4800 0010h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
INTR_STATUS | |||||||||||||||
R/W1TS | |||||||||||||||
0 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
INTR_STATUS | |||||||||||||||
R/W1TS | |||||||||||||||
0 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INTR_STATUS | |||||||||||||||
R/W1TS | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_STATUS | |||||||||||||||
R/W1TS | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 - 0 | INTR_STATUS | R/W1TS | 0h | Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set |
Short Description: Interrupt Status Clear Register
Long Description:
Return to Summary Table
Offset = 18h + (j * 1000h); where j = 0h to B7h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4800 0018h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
INTR_STATUS | |||||||||||||||
R/W1TC | |||||||||||||||
0 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
INTR_STATUS | |||||||||||||||
R/W1TC | |||||||||||||||
0 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INTR_STATUS | |||||||||||||||
R/W1TC | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_STATUS | |||||||||||||||
R/W1TC | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 - 0 | INTR_STATUS | R/W1TC | 0h | Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared |
Short Description: Interrupt Masked Status Register
Long Description:
Return to Summary Table
Offset = 20h + (j * 1000h); where j = 0h to B7h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4800 0020h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
INTR_STATUSM | |||||||||||||||
R/NA | |||||||||||||||
0 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
INTR_STATUSM | |||||||||||||||
R/NA | |||||||||||||||
0 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INTR_STATUSM | |||||||||||||||
R/NA | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_STATUSM | |||||||||||||||
R/NA | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 - 0 | INTR_STATUSM | R/NA | 0h | Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers |
Short Description: Interrupt Mapping Register
Long Description:
Return to Summary Table
Offset = 0h + (j * 8h); where j = 0h to 5FFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4810 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | REGNUM | ||||||||||||||
NONE | R/W | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REGNUM | RESERVED | BITNUM | |||||||||||||
R/W | NONE | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
16 - 8 | REGNUM | R/W | 0h | Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in. |
RESERVED | NONE | Reserved | ||
5 - 0 | BITNUM | R/W | 0h | Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in. |
Short Description: Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4811 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R | |||||||||||||||
110011010010110 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
10 | 1 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 - 16 | MODID | R | 6696h | Module ID field |
15 - 11 | REVRTL | R | 2h | RTL revision. Will vary depending on release. |
10 - 8 | REVMAJ | R | 1h | Major revision |
7 - 6 | CUSTOM | R | 0h | Custom |
5 - 0 | REVMIN | R | 1h | Minor revision |
Short Description: Interrupt Capabilities
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4811 0008h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VINTR_CNT | |||||||||||||||
R | |||||||||||||||
10111000 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEVT_CNT | |||||||||||||||
R | |||||||||||||||
11000000000 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 - 16 | VINTR_CNT | R | B8h | Virtual interrupt register/pin count |
15 - 0 | SEVT_CNT | R | 600h | Number of 'event to virt int' mapping registers |
Short Description: Auxiliary Capabilities
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4811 0010h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
UNMAP_CNT | |||||||||||||||
R | |||||||||||||||
11000000010100 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
MEVI_CNT | |||||||||||||||
R | |||||||||||||||
10000000 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
LEVI_CNT | |||||||||||||||
R | |||||||||||||||
100000 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GEVI_CNT | |||||||||||||||
R | |||||||||||||||
100000000 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 - 48 | UNMAP_CNT | R | 3014h | Number of multicast event registers. Not all registers in the range are necessarily valid. |
47 - 32 | MEVI_CNT | R | 80h | Number of multicast event registers |
31 - 16 | LEVI_CNT | R | 20h | Local input events for local to global translation |
15 - 0 | GEVI_CNT | R | 100h | Number of event counting registers |
Short Description: Local to global event mapping
Long Description:
Return to Summary Table
Offset = 0h + (j * 20h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4812 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GEVIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | MODE | R/W | 0h | Local event detection mode. This field is set to 0 for pulsed events, and to 1 for rising edge eventss |
RESERVED | NONE | Reserved | ||
15 - 0 | GEVIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 0h + (j * 8h); where j = 0h to 3FFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 8000h + (j * 8h); where j = 0h to 29h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 8000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 9000h + (j * 8h); where j = 0h to 6Fh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 9000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = a000h + (j * 8h); where j = 0h to 1Ch
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 A000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = b000h + (j * 8h); where j = 0h to AFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 B000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = c000h + (j * 8h); where j = 0h to AFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 C000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = d000h + (j * 8h); where j = 0h to AFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4818 D000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 10000h + (j * 8h); where j = 0h to 1Bh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 11000h + (j * 8h); where j = 0h to 1Bh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 1000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 12000h + (j * 8h); where j = 0h to 1Bh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 2000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 13000h + (j * 8h); where j = 0h to 13h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 3000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 14000h + (j * 8h); where j = 0h to 13h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 4000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 15000h + (j * 8h); where j = 0h to 13h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 5000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 16000h + (j * 8h); where j = 0h to 13h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 6000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 17000h + (j * 8h); where j = 0h to 13h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 7000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Unmapped Event Mapping Register
Long Description:
Return to Summary Table
Offset = 18000h + (j * 8h); where j = 0h to 13h
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4819 8000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UMAPIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | UMAPIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: Multicast event mapping
Long Description:
Return to Summary Table
Offset = 0h + (j * 20h); where j = 0h to 7Fh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4821 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
IRQMODE1 | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
GEVIDX1 | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE0 | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GEVIDX0 | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63 | IRQMODE1 | R/W | 0h | IRQ Mode Flag 1. When set, this register act like a mapper with bitnum in 37:32 and regnum in 46:38. |
RESERVED | NONE | Reserved | ||
47 - 32 | GEVIDX1 | R/W | FFFFh | Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable. |
31 | IRQMODE0 | R/W | 0h | IRQ Mode Flag 0. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | GEVIDX0 | R/W | FFFFh | Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable. |
Short Description: Gobal Event Mapping Register
Long Description:
Return to Summary Table
Offset = 0h + (j * 20h); where j = 0h to FFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4822 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQMODE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GEVIDX | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 | IRQMODE | R/W | 0h | IRQ Mode Flag. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. |
RESERVED | NONE | Reserved | ||
15 - 0 | GEVIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. |
Short Description: ETL Count Register
Long Description:
Return to Summary Table
Offset = 0h + (j * 1000h); where j = 0h to FFh
Instance Name | Base Address |
---|---|
DMASS0_INTAGGR_0 | 4A00 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CCNT | |||||||||||||||
R/WTD | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCNT | |||||||||||||||
R/WTD | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
31 - 0 | CCNT | R/WTD | 0h | Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write, this field will be decremented by the value written. Writing a value greater than the current count is illegal. |
Access Type | Code | Description |
---|---|---|
R/W1TS | R/W1TS | Read/Write 1 To Set |
R/W1TC | R/W1TC | Read/Write 1 To Clear |
R/NA | R/NA | Undefined |
R/W | R/W | Read / Write |
R | R | Read |
R/WTD | R/WTD | Undefined |