SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 9-59 shows the mapping of events to the GICSS0 PPI inputs. There are 16 PPI events per A53 core.
PPI events can be configured for either low-level (default) or high-pulse operation.
PPI events represent events 16-31 of each A53 core.
Interrupt Input Line | Interrupt ID | Source Interrupt |
---|---|---|
PPI events for A53SS0_CORE0 | ||
GICSS0_PPI0_0_IN_22 | 22 | COMMIRQ0_0 |
GICSS0_PPI0_0_IN_23 | 23 | PMUIRQ0_0 |
GICSS0_PPI0_0_IN_24 | 24 | CTIIRQ0_0 |
GICSS0_PPI0_0_IN_25 | 25 | VCPUMNTIRQ0_0 |
GICSS0_PPI0_0_IN_26 | 26 | CNTHPIRQ0_0 |
GICSS0_PPI0_0_IN_27 | 27 | CNTVIRQ0_0 |
GICSS0_PPI0_0_IN_29 | 29 | CNTPSIRQ0_0 |
GICSS0_PPI0_0_IN_30 | 30 | CNTPNSIRQ0_0 |
GICSS0_PPI0_0_IN_31 | 31 | CTIIRQ1_0 |
PPI events for A53SS0_CORE1 | ||
GICSS0_PPI0_1_IN_22 | 22 | COMMIRQ1_0 |
GICSS0_PPI0_1_IN_23 | 23 | PMUIRQ1_0 |
GICSS0_PPI0_1_IN_24 | 24 | CTIIRQ1_0 |
GICSS0_PPI0_1_IN_25 | 25 | VCPUMNTIRQ1_0 |
GICSS0_PPI0_1_IN_26 | 26 | CNTHPIRQ1_0 |
GICSS0_PPI0_1_IN_27 | 27 | CNTVIRQ1_0 |
GICSS0_PPI0_1_IN_29 | 29 | CNTPSIRQ1_0 |
GICSS0_PPI0_1_IN_30 | 30 | CNTPNSIRQ1_0 |
GICSS0_PPI0_1_IN_31 | 31 | CTIIRQ0_0 |