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There is one ESM module integrated in the device MAIN domain - ESM0. Figure 12-2529 shows the integration of ESM0.
Table 12-4834 through Table 12-4837 summarize the integration of ESM in the device MAIN domain.
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
---|---|---|---|---|
ESM0 | PSC0 | PD0 | LPSC0 | CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
ESM0 | ESM0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | ESM0 Interface and Functional clock |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
ESM0 | ESM0_RST | MOD_G_RST | LPSC0 | ESM0 Asynchronous module reset |
ESM0_POR_RST | MOD_POR_RST | LPSC0 | ESM0 Power-on module reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
ESM0 | ESM0_ESM_INT_CFG_LVL_0 | GICSS0_SPI_IN_180 | COMPUTE_CLUSTER0 | ESM0 configuration error interrupt | Level |
R5FSS0_CORE0_INTR_IN_167 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_167 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_167 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_167 | R5FSS1_CORE1 | ||||
ESM0_ESM_INT_LOW_LVL_0 | GICSS0_SPI_IN_182 | COMPUTE_CLUSTER0 | ESM0 low priority interrupt | Level | |
R5FSS0_CORE0_INTR_IN_169 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_169 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_169 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_169 | R5FSS1_CORE1 | ||||
ESM0_ESM_INT_HI_LVL_0 | GICSS0_SPI_IN_181 | COMPUTE_CLUSTER0 | ESM0 high priority interrupt | Level | |
R5FSS0_CORE0_INTR_IN_168 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_168 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_168 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_168 | R5FSS1_CORE1 |
Table 12-4837 lists only the ESM0 interrupt outputs and input resets. For the mapping of system interrupt error events to ESM0 interrupt inputs, see Section 9.4, Interrupt Sources. For more information of ESM0 output reset to device reset logic, see Section 5.3, Reset.
For a description of the interrupt requests, see Section 12.6.2.4.1, Interrupt Requests.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.