SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This device includes two PRU_ICSSG instances named PRU_ICSSG0 and PRU_ICSSG1. The PRU_ICSSG includes six PRU RISC cores: PRU0, RTU_PRU0, TX_PRU0, PRU1, RTU_PRU1 and TX_PRU1. Each PRU supports basic debug functionality as detailed in Table 13-11.
Capability | Feature | Notes |
---|---|---|
Basic Debug | Processor halt | Support user-requested entry into the suspended state |
Single step | Execution of a single instruction before entering the suspended state | |
Software breakpoints | Software breakpoints are supported via opcode replacement | |
Core register access | Access to processor core registers | |
System memory access | Access to memory from perspective of CPU |