SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-500 lists the memory-mapped registers for the UART. All register offset addresses not listed in Table 12-500 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
UART0 | 0280 0000h |
UART1 | 0281 0000h |
UART2 | 0282 0000h |
UART3 | 0283 0000h |
UART4 | 0284 0000h |
UART5 | 0285 0000h |
UART6 | 0286 0000h |
UART0 | 04A0 0000h |
MCU_UART1 | 04A1 0000h |
Offset | Acronym | Register Name | UART0 Physical Address | UART1 Physical Address | UART2 Physical Address |
---|---|---|---|---|---|
0h | UART_THR | Transmit holding register | 0280 0000h | 0281 0000h | 0282 0000h |
0h | UART_RHR | Receiver holding register | 0280 0000h | 0281 0000h | 0282 0000h |
0h | UART_DLL | Baud clock divisor LSB value register | 0280 0000h | 0281 0000h | 0282 0000h |
4h | UART_IER_UART | UART mode interrupt enable register | 0280 0004h | 0281 0004h | 0282 0004h |
4h | UART_IER_IRDA | IrDA mode interrupt enable register | 0280 0004h | 0281 0004h | 0282 0004h |
4h | UART_IER_CIR | CIR mode interrupt enable register | 0280 0004h | 0281 0004h | 0282 0004h |
4h | UART_DLH | Baud clock divisor MSB value register | 0280 0004h | 0281 0004h | 0282 0004h |
8h | UART_IIR_UART | UART mode interrupt identification register | 0280 0008h | 0281 0008h | 0282 0008h |
8h | UART_IIR_IRDA | IrDA mode interrupt identification register | 0280 0008h | 0281 0008h | 0282 0008h |
8h | UART_IIR_CIR | CIR mode interrupt identification register | 0280 0008h | 0281 0008h | 0282 0008h |
8h | UART_FCR | FIFO control register | 0280 0008h | 0281 0008h | 0282 0008h |
8h | UART_EFR | Enhanced feature register | 0280 0008h | 0281 0008h | 0282 0008h |
Ch | UART_LCR | Line control register | 0280 000Ch | 0281 000Ch | 0282 000Ch |
10h | UART_MCR | Modem control register | 0280 0010h | 0281 0010h | 0282 0010h |
10h | UART_XON1_ADDR1 | UART mode XON1 character, IrDA mode ADDR1 address register | 0280 0010h | 0281 0010h | 0282 0010h |
14h | UART_LSR_UART | UART mode line status register | 0280 0014h | 0281 0014h | 0282 0014h |
14h | UART_LSR_IRDA | IrDA mode line status register | 0280 0014h | 0281 0014h | 0282 0014h |
14h | UART_LSR_CIR | CIR mode line status register | 0280 0014h | 0281 0014h | 0282 0014h |
14h | UART_XON2_ADDR2 | UART mode XON2 character, IrDA mode ADDR2 address register | 0280 0014h | 0281 0014h | 0282 0014h |
18h | UART_MSR | Modem status register | 0280 0018h | 0281 0018h | 0282 0018h |
18h | UART_XOFF1 | UART mode XOFF1 character | 0280 0018h | 0281 0018h | 0282 0018h |
18h | UART_TCR | Transmission control register | 0280 0018h | 0281 0018h | 0282 0018h |
1Ch | UART_SPR | Scratchpad register | 0280 001Ch | 0281 001Ch | 0282 001Ch |
1Ch | UART_XOFF2 | UART mode XOFF2 character | 0280 001Ch | 0281 001Ch | 0282 001Ch |
1Ch | UART_TLR | Trigger level register | 0280 001Ch | 0281 001Ch | 0282 001Ch |
20h | UART_MDR1 | Mode definition register 1 | 0280 0020h | 0281 0020h | 0282 0020h |
24h | UART_MDR2 | Mode definition register 2 | 0280 0024h | 0281 0024h | 0282 0024h |
28h | UART_SFLSR | Status FIFO line status register | 0280 0028h | 0281 0028h | 0282 0028h |
28h | UART_TXFLL | Transmit frame length register low | 0280 0028h | 0281 0028h | 0282 0028h |
2Ch | UART_RESUME | Resume halted operation register | 0280 002Ch | 0281 002Ch | 0282 002Ch |
2Ch | UART_TXFLH | Transmit frame length register high | 0280 002Ch | 0281 002Ch | 0282 002Ch |
30h | UART_SFREGL | Status FIFO register low | 0280 0030h | 0281 0030h | 0282 0030h |
30h | UART_RXFLL | Received frame length register low | 0280 0030h | 0281 0030h | 0282 0030h |
34h | UART_SFREGH | Status FIFO register high | 0280 0034h | 0281 0034h | 0282 0034h |
34h | UART_RXFLH | Received frame length register high | 0280 0034h | 0281 0034h | 0282 0034h |
38h | UART_BLR | BOF control register | 0280 0038h | 0281 0038h | 0282 0038h |
38h | UART_UASR | UART autobauding status register | 0280 0038h | 0281 0038h | 0282 0038h |
3Ch | UART_ACREG | Auxiliary control register | 0280 003Ch | 0281 003Ch | 0282 003Ch |
40h | UART_SCR | Supplementary control register | 0280 0040h | 0281 0040h | 0282 0040h |
44h | UART_SSR | Supplementary status register | 0280 0044h | 0281 0044h | 0282 0044h |
48h | UART_EBLR | BOF length register | 0280 0048h | 0281 0048h | 0282 0048h |
50h | UART_MVR | Module version register | 0280 0050h | 0281 0050h | 0282 0050h |
54h | UART_SYSC | System configuration register | 0280 0054h | 0281 0054h | 0282 0054h |
58h | UART_SYSS | System status register | 0280 0058h | 0281 0058h | 0282 0058h |
5Ch | UART_WER | Wake-up enable register | 0280 005Ch | 0281 005Ch | 0282 005Ch |
60h | UART_CFPS | Carrier frequency prescaler register | 0280 0060h | 0281 0060h | 0282 0060h |
64h | UART_RXFIFO_LVL | RX FIFO level register | 0280 0064h | 0281 0064h | 0282 0064h |
68h | UART_TXFIFO_LVL | TX FIFO level register | 0280 0068h | 0281 0068h | 0282 0068h |
6Ch | UART_IER2 | Interrupt enable register 2 | 0280 006Ch | 0281 006Ch | 0282 006Ch |
70h | UART_ISR2 | Interrupt status register 2 | 0280 0070h | 0281 0070h | 0282 0070h |
74h | UART_FREQ_SEL | Sample per bit selector register | 0280 0074h | 0281 0074h | 0282 0074h |
78h | UART_ABAUD_1ST_CHAR | 0280 0078h | 0281 0078h | 0282 0078h | |
7Ch | UART_BAUD_2ND_CHAR | 0280 007Ch | 0281 007Ch | 0282 007Ch | |
80h | UART_MDR3 | Mode definition register 3 | 0280 0080h | 0281 0080h | 0282 0080h |
84h | UART_TX_DMA_THRESHOLD | TX DMA threshold level register | 0280 0084h | 0281 0084h | 0282 0084h |
88h | UART_MDR4 | Mode definition register 4 | 0280 0088h | 0281 0088h | 0282 0088h |
8Ch | UART_EFR2 | Enhanced features register 2 | 0280 008Ch | 0281 008Ch | 0282 008Ch |
90h | UART_ECR | Enhanced control register | 0280 0090h | 0281 0090h | 0282 0090h |
94h | UART_TIMEGUARD | Timeguard register | 0280 0094h | 0281 0094h | 0282 0094h |
98h | UART_TIMEOUTL | Timeout lower byte register | 0280 0098h | 0281 0098h | 0282 0098h |
9Ch | UART_TIMEOUTH | Timeout higher byte register | 0280 009Ch | 0281 009Ch | 0282 009Ch |
A0h | UART_SCCR | Smartcard mode control register | 0280 00A0h | 0281 00A0h | 0282 00A0h |
A4h | UART_ERHR | Extended receive holding register | 0280 00A4h | 0281 00A4h | 0282 00A4h |
A4h | UART_ETHR | Extended transmit holding register | 0280 00A4h | 0281 00A4h | 0282 00A4h |
A8h | UART_MAR | Multidrop address register | 0280 00A8h | 0281 00A8h | 0282 00A8h |
ACh | UART_MMR | Multidrop mask register | 0280 00ACh | 0281 00ACh | 0282 00ACh |
B0h | UART_MBR | Multidrop broadcast address register | 0280 00B0h | 0281 00B0h | 0282 00B0h |
Offset | Acronym | Register Name | UART3 Physical Address | UART4 Physical Address | UART5 Physical Address |
---|---|---|---|---|---|
0h | UART_THR | Transmit holding register | 0283 0000h | 0284 0000h | 0285 0000h |
0h | UART_RHR | Receiver holding register | 0283 0000h | 0284 0000h | 0285 0000h |
0h | UART_DLL | Baud clock divisor LSB value register | 0283 0000h | 0284 0000h | 0285 0000h |
4h | UART_IER_UART | UART mode interrupt enable register | 0283 0004h | 0284 0004h | 0285 0004h |
4h | UART_IER_IRDA | IrDA mode interrupt enable register | 0283 0004h | 0284 0004h | 0285 0004h |
4h | UART_IER_CIR | CIR mode interrupt enable register | 0283 0004h | 0284 0004h | 0285 0004h |
4h | UART_DLH | Baud clock divisor MSB value register | 0283 0004h | 0284 0004h | 0285 0004h |
8h | UART_IIR_UART | UART mode interrupt identification register | 0283 0008h | 0284 0008h | 0285 0008h |
8h | UART_IIR_IRDA | IrDA mode interrupt identification register | 0283 0008h | 0284 0008h | 0285 0008h |
8h | UART_IIR_CIR | CIR mode interrupt identification register | 0283 0008h | 0284 0008h | 0285 0008h |
8h | UART_FCR | FIFO control register | 0283 0008h | 0284 0008h | 0285 0008h |
8h | UART_EFR | Enhanced feature register | 0283 0008h | 0284 0008h | 0285 0008h |
Ch | UART_LCR | Line control register | 0283 000Ch | 0284 000Ch | 0285 000Ch |
10h | UART_MCR | Modem control register | 0283 0010h | 0284 0010h | 0285 0010h |
10h | UART_XON1_ADDR1 | UART mode XON1 character, IrDA mode ADDR1 address register | 0283 0010h | 0284 0010h | 0285 0010h |
14h | UART_LSR_UART | UART mode line status register | 0283 0014h | 0284 0014h | 0285 0014h |
14h | UART_LSR_IRDA | IrDA mode line status register | 0283 0014h | 0284 0014h | 0285 0014h |
14h | UART_LSR_CIR | CIR mode line status register | 0283 0014h | 0284 0014h | 0285 0014h |
14h | UART_XON2_ADDR2 | UART mode XON2 character, IrDA mode ADDR2 address register | 0283 0014h | 0284 0014h | 0285 0014h |
18h | UART_MSR | Modem status register | 0283 0018h | 0284 0018h | 0285 0018h |
18h | UART_XOFF1 | UART mode XOFF1 character | 0283 0018h | 0284 0018h | 0285 0018h |
18h | UART_TCR | Transmission control register | 0283 0018h | 0284 0018h | 0285 0018h |
1Ch | UART_SPR | Scratchpad register | 0283 001Ch | 0284 001Ch | 0285 001Ch |
1Ch | UART_XOFF2 | UART mode XOFF2 character | 0283 001Ch | 0284 001Ch | 0285 001Ch |
1Ch | UART_TLR | Trigger level register | 0283 001Ch | 0284 001Ch | 0285 001Ch |
20h | UART_MDR1 | Mode definition register 1 | 0283 0020h | 0284 0020h | 0285 0020h |
24h | UART_MDR2 | Mode definition register 2 | 0283 0024h | 0284 0024h | 0285 0024h |
28h | UART_SFLSR | Status FIFO line status register | 0283 0028h | 0284 0028h | 0285 0028h |
28h | UART_TXFLL | Transmit frame length register low | 0283 0028h | 0284 0028h | 0285 0028h |
2Ch | UART_RESUME | Resume halted operation register | 0283 002Ch | 0284 002Ch | 0285 002Ch |
2Ch | UART_TXFLH | Transmit frame length register high | 0283 002Ch | 0284 002Ch | 0285 002Ch |
30h | UART_SFREGL | Status FIFO register low | 0283 0030h | 0284 0030h | 0285 0030h |
30h | UART_RXFLL | Received frame length register low | 0283 0030h | 0284 0030h | 0285 0030h |
34h | UART_SFREGH | Status FIFO register high | 0283 0034h | 0284 0034h | 0285 0034h |
34h | UART_RXFLH | Received frame length register high | 0283 0034h | 0284 0034h | 0285 0034h |
38h | UART_BLR | BOF control register | 0283 0038h | 0284 0038h | 0285 0038h |
38h | UART_UASR | UART autobauding status register | 0283 0038h | 0284 0038h | 0285 0038h |
3Ch | UART_ACREG | Auxiliary control register | 0283 003Ch | 0284 003Ch | 0285 003Ch |
40h | UART_SCR | Supplementary control register | 0283 0040h | 0284 0040h | 0285 0040h |
44h | UART_SSR | Supplementary status register | 0283 0044h | 0284 0044h | 0285 0044h |
48h | UART_EBLR | BOF length register | 0283 0048h | 0284 0048h | 0285 0048h |
50h | UART_MVR | Module version register | 0283 0050h | 0284 0050h | 0285 0050h |
54h | UART_SYSC | System configuration register | 0283 0054h | 0284 0054h | 0285 0054h |
58h | UART_SYSS | System status register | 0283 0058h | 0284 0058h | 0285 0058h |
5Ch | UART_WER | Wake-up enable register | 0283 005Ch | 0284 005Ch | 0285 005Ch |
60h | UART_CFPS | Carrier frequency prescaler register | 0283 0060h | 0284 0060h | 0285 0060h |
64h | UART_RXFIFO_LVL | RX FIFO level register | 0283 0064h | 0284 0064h | 0285 0064h |
68h | UART_TXFIFO_LVL | TX FIFO level register | 0283 0068h | 0284 0068h | 0285 0068h |
6Ch | UART_IER2 | Interrupt enable register 2 | 0283 006Ch | 0284 006Ch | 0285 006Ch |
70h | UART_ISR2 | Interrupt status register 2 | 0283 0070h | 0284 0070h | 0285 0070h |
74h | UART_FREQ_SEL | Sample per bit selector register | 0283 0074h | 0284 0074h | 0285 0074h |
78h | UART_ABAUD_1ST_CHAR | 0283 0078h | 0284 0078h | 0285 0078h | |
7Ch | UART_BAUD_2ND_CHAR | 0283 007Ch | 0284 007Ch | 0285 007Ch | |
80h | UART_MDR3 | Mode definition register 3 | 0283 0080h | 0284 0080h | 0285 0080h |
84h | UART_TX_DMA_THRESHOLD | TX DMA threshold level register | 0283 0084h | 0284 0084h | 0285 0084h |
88h | UART_MDR4 | Mode definition register 4 | 0283 0088h | 0284 0088h | 0285 0088h |
8Ch | UART_EFR2 | Enhanced features register 2 | 0283 008Ch | 0284 008Ch | 0285 008Ch |
90h | UART_ECR | Enhanced control register | 0283 0090h | 0284 0090h | 0285 0090h |
94h | UART_TIMEGUARD | Timeguard register | 0283 0094h | 0284 0094h | 0285 0094h |
98h | UART_TIMEOUTL | Timeout lower byte register | 0283 0098h | 0284 0098h | 0285 0098h |
9Ch | UART_TIMEOUTH | Timeout higher byte register | 0283 009Ch | 0284 009Ch | 0285 009Ch |
A0h | UART_SCCR | Smartcard mode control register | 0283 00A0h | 0284 00A0h | 0285 00A0h |
A4h | UART_ERHR | Extended receive holding register | 0283 00A4h | 0284 00A4h | 0285 00A4h |
A4h | UART_ETHR | Extended transmit holding register | 0283 00A4h | 0284 00A4h | 0285 00A4h |
A8h | UART_MAR | Multidrop address register | 0283 00A8h | 0284 00A8h | 0285 00A8h |
ACh | UART_MMR | Multidrop mask register | 0283 00ACh | 0284 00ACh | 0285 00ACh |
B0h | UART_MBR | Multidrop broadcast address register | 0283 00B0h | 0284 00B0h | 0285 00B0h |
Offset | Acronym | Register Name | UART6 Physical Address | MCU_UART0 Physical Address | MCU_UART1 Physical Address |
---|---|---|---|---|---|
0h | UART_THR | Transmit holding register | 0286 0000h | 04A0 0000h | 04A1 0000h |
0h | UART_RHR | Receiver holding register | 0286 0000h | 04A0 0000h | 04A1 0000h |
0h | UART_DLL | Baud clock divisor LSB value register | 0286 0000h | 04A0 0000h | 04A1 0000h |
4h | UART_IER_UART | UART mode interrupt enable register | 0286 0004h | 04A0 0004h | 04A1 0004h |
4h | UART_IER_IRDA | IrDA mode interrupt enable register | 0286 0004h | 04A0 0004h | 04A1 0004h |
4h | UART_IER_CIR | CIR mode interrupt enable register | 0286 0004h | 04A0 0004h | 04A1 0004h |
4h | UART_DLH | Baud clock divisor MSB value register | 0286 0004h | 04A0 0004h | 04A1 0004h |
8h | UART_IIR_UART | UART mode interrupt identification register | 0286 0008h | 04A0 0008h | 04A1 0008h |
8h | UART_IIR_IRDA | IrDA mode interrupt identification register | 0286 0008h | 04A0 0008h | 04A1 0008h |
8h | UART_IIR_CIR | CIR mode interrupt identification register | 0286 0008h | 04A0 0008h | 04A1 0008h |
8h | UART_FCR | FIFO control register | 0286 0008h | 04A0 0008h | 04A1 0008h |
8h | UART_EFR | Enhanced feature register | 0286 0008h | 04A0 0008h | 04A1 0008h |
Ch | UART_LCR | Line control register | 0286 000Ch | 04A0 000Ch | 04A1 000Ch |
10h | UART_MCR | Modem control register | 0286 0010h | 04A0 0010h | 04A1 0010h |
10h | UART_XON1_ADDR1 | UART mode XON1 character, IrDA mode ADDR1 address register | 0286 0010h | 04A0 0010h | 04A1 0010h |
14h | UART_LSR_UART | UART mode line status register | 0286 0014h | 04A0 0014h | 04A1 0014h |
14h | UART_LSR_IRDA | IrDA mode line status register | 0286 0014h | 04A0 0014h | 04A1 0014h |
14h | UART_LSR_CIR | CIR mode line status register | 0286 0014h | 04A0 0014h | 04A1 0014h |
14h | UART_XON2_ADDR2 | UART mode XON2 character, IrDA mode ADDR2 address register | 0286 0014h | 04A0 0014h | 04A1 0014h |
18h | UART_MSR | Modem status register | 0286 0018h | 04A0 0018h | 04A1 0018h |
18h | UART_XOFF1 | UART mode XOFF1 character | 0286 0018h | 04A0 0018h | 04A1 0018h |
18h | UART_TCR | Transmission control register | 0286 0018h | 04A0 0018h | 04A1 0018h |
1Ch | UART_SPR | Scratchpad register | 0286 001Ch | 04A0 001Ch | 04A1 001Ch |
1Ch | UART_XOFF2 | UART mode XOFF2 character | 0286 001Ch | 04A0 001Ch | 04A1 001Ch |
1Ch | UART_TLR | Trigger level register | 0286 001Ch | 04A0 001Ch | 04A1 001Ch |
20h | UART_MDR1 | Mode definition register 1 | 0286 0020h | 04A0 0020h | 04A1 0020h |
24h | UART_MDR2 | Mode definition register 2 | 0286 0024h | 04A0 0024h | 04A1 0024h |
28h | UART_SFLSR | Status FIFO line status register | 0286 0028h | 04A0 0028h | 04A1 0028h |
28h | UART_TXFLL | Transmit frame length register low | 0286 0028h | 04A0 0028h | 04A1 0028h |
2Ch | UART_RESUME | Resume halted operation register | 0286 002Ch | 04A0 002Ch | 04A1 002Ch |
2Ch | UART_TXFLH | Transmit frame length register high | 0286 002Ch | 04A0 002Ch | 04A1 002Ch |
30h | UART_SFREGL | Status FIFO register low | 0286 0030h | 04A0 0030h | 04A1 0030h |
30h | UART_RXFLL | Received frame length register low | 0286 0030h | 04A0 0030h | 04A1 0030h |
34h | UART_SFREGH | Status FIFO register high | 0286 0034h | 04A0 0034h | 04A1 0034h |
34h | UART_RXFLH | Received frame length register high | 0286 0034h | 04A0 0034h | 04A1 0034h |
38h | UART_BLR | BOF control register | 0286 0038h | 04A0 0038h | 04A1 0038h |
38h | UART_UASR | UART autobauding status register | 0286 0038h | 04A0 0038h | 04A1 0038h |
3Ch | UART_ACREG | Auxiliary control register | 0286 003Ch | 04A0 003Ch | 04A1 003Ch |
40h | UART_SCR | Supplementary control register | 0286 0040h | 04A0 0040h | 04A1 0040h |
44h | UART_SSR | Supplementary status register | 0286 0044h | 04A0 0044h | 04A1 0044h |
48h | UART_EBLR | BOF length register | 0286 0048h | 04A0 0048h | 04A1 0048h |
50h | UART_MVR | Module version register | 0286 0050h | 04A0 0050h | 04A1 0050h |
54h | UART_SYSC | System configuration register | 0286 0054h | 04A0 0054h | 04A1 0054h |
58h | UART_SYSS | System status register | 0286 0058h | 04A0 0058h | 04A1 0058h |
5Ch | UART_WER | Wake-up enable register | 0286 005Ch | 04A0 005Ch | 04A1 005Ch |
60h | UART_CFPS | Carrier frequency prescaler register | 0286 0060h | 04A0 0060h | 04A1 0060h |
64h | UART_RXFIFO_LVL | RX FIFO level register | 0286 0064h | 04A0 0064h | 04A1 0064h |
68h | UART_TXFIFO_LVL | TX FIFO level register | 0286 0068h | 04A0 0068h | 04A1 0068h |
6Ch | UART_IER2 | Interrupt enable register 2 | 0286 006Ch | 04A0 006Ch | 04A1 006Ch |
70h | UART_ISR2 | Interrupt status register 2 | 0286 0070h | 04A0 0070h | 04A1 0070h |
74h | UART_FREQ_SEL | Sample per bit selector register | 0286 0074h | 04A0 0074h | 04A1 0074h |
78h | UART_ABAUD_1ST_CHAR | 0286 0078h | 04A0 0078h | 04A1 0078h | |
7Ch | UART_BAUD_2ND_CHAR | 0286 007Ch | 04A0 007Ch | 04A1 007Ch | |
80h | UART_MDR3 | Mode definition register 3 | 0286 0080h | 04A0 0080h | 04A1 0080h |
84h | UART_TX_DMA_THRESHOLD | TX DMA threshold level register | 0286 0084h | 04A0 0084h | 04A1 0084h |
88h | UART_MDR4 | Mode definition register 4 | 0286 0088h | 04A0 0088h | 04A1 0088h |
8Ch | UART_EFR2 | Enhanced features register 2 | 0286 008Ch | 04A0 008Ch | 04A1 008Ch |
90h | UART_ECR | Enhanced control register | 0286 0090h | 04A0 0090h | 04A1 0090h |
94h | UART_TIMEGUARD | Timeguard register | 0286 0094h | 04A0 0094h | 04A1 0094h |
98h | UART_TIMEOUTL | Timeout lower byte register | 0286 0098h | 04A0 0098h | 04A1 0098h |
9Ch | UART_TIMEOUTH | Timeout higher byte register | 0286 009Ch | 04A0 009Ch | 04A1 009Ch |
A0h | UART_SCCR | Smartcard mode control register | 0286 00A0h | 04A0 00A0h | 04A1 00A0h |
A4h | UART_ERHR | Extended receive holding register | 0286 00A4h | 04A0 00A4h | 04A1 00A4h |
A4h | UART_ETHR | Extended transmit holding register | 0286 00A4h | 04A0 00A4h | 04A1 00A4h |
A8h | UART_MAR | Multidrop address register | 0286 00A8h | 04A0 00A8h | 04A1 00A8h |
ACh | UART_MMR | Multidrop mask register | 0286 00ACh | 04A0 00ACh | 04A1 00ACh |
B0h | UART_MBR | Multidrop broadcast address register | 0286 00B0h | 04A0 00B0h | 04A1 00B0h |
UART_THR is shown in Figure 12-274 and described in Table 12-504.
Return to Summary Table.
The transmitter section consists of the transmit holding register (UART_THR) and the transmit shift register. The UART_THR is a 64-byte FIFO. The local host (LH) writes data to the UART_THR. The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data.
Instance | Physical Address |
---|---|
UART0 | 0280 0000h |
UART1 | 0281 0000h |
UART2 | 0282 0000h |
UART3 | 0283 0000h |
UART4 | 0284 0000h |
UART5 | 0285 0000h |
UART6 | 0286 0000h |
MCU_UART0 | 04A0 0000h |
MCU_UART1 | 04A1 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THR | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | THR | W | 0h |
Transmit holding register |
UART_RHR is shown in Figure 12-275 and described in Table 12-506.
Return to Summary Table.
The receiver section consists of the receiver holding register (UART_RHR) and the receiver shift register. The UART_RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the UART_RHR. If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the UART_RHR is not overwritten.
Instance | Physical Address |
---|---|
UART0 | 0280 0000h |
UART1 | 0281 0000h |
UART2 | 0282 0000h |
UART3 | 0283 0000h |
UART4 | 0284 0000h |
UART5 | 0285 0000h |
UART6 | 0286 0000h |
MCU_UART0 | 04A0 0000h |
MCU_UART1 | 04A1 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RHR | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | RHR | R | 0h |
Receive holding register |
UART_DLL is shown in Figure 12-276 and described in Table 12-508.
Return to Summary Table.
This register, with UART_DLH, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. UART_DLH stores the most-significant part of the divisor. UART_DLL stores the least-significant part of the divisor.
Instance | Physical Address |
---|---|
UART0 | 0280 0000h |
UART1 | 0281 0000h |
UART2 | 0282 0000h |
UART3 | 0283 0000h |
UART4 | 0284 0000h |
UART5 | 0285 0000h |
UART6 | 0286 0000h |
MCU_UART0 | 04A0 0000h |
MCU_UART1 | 04A1 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLOCK_LSB | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | CLOCK_LSB | R/W | 0h |
Stores the 8-bit LSB divisor value |
UART_IER_UART is shown in Figure 12-277 and described in Table 12-510.
Return to Summary Table.
Interrupt enable register
The interrupt enable register (UART_IER_UART) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, UART_RHR interrupt, UART_THR interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit.
Instance | Physical Address |
---|---|
UART0 | 0280 0004h |
UART1 | 0281 0004h |
UART2 | 0282 0004h |
UART3 | 0283 0004h |
UART4 | 0284 0004h |
UART5 | 0285 0004h |
UART6 | 0286 0004h |
MCU_UART0 | 04A0 0004h |
MCU_UART1 | 04A1 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTS_IT | RTS_IT | XOFF_IT | SLEEP_MODE | MODEM_STS_IT | LINE_STS_IT | THR_IT | RHR_IT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | CTS_IT | R/W | 0h |
|
6 | RTS_IT | R/W | 0h |
|
5 | XOFF_IT | R/W | 0h |
|
4 | SLEEP_MODE | R/W | 0h |
|
3 | MODEM_STS_IT | R/W | 0h |
|
2 | LINE_STS_IT | R/W | 0h |
|
1 | THR_IT | R/W | 0h |
|
0 | RHR_IT | R/W | 0h |
|
UART_IER_IRDA is shown in Figure 12-278 and described in Table 12-512.
Return to Summary Table.
There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The UART_MDR2[0] should be read to determine the status in the event of this interrupt.
Instance | Physical Address |
---|---|
UART0 | 0280 0004h |
UART1 | 0281 0004h |
UART2 | 0282 0004h |
UART3 | 0283 0004h |
UART4 | 0284 0004h |
UART5 | 0285 0004h |
UART6 | 0286 0004h |
MCU_UART0 | 04A0 0004h |
MCU_UART1 | 04A1 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOF_IT | LINE_STS_IT | TX_STATUS_IT | STS_FIFO_TRIG_IT | RX_OVERRUN_IT | LAST_RX_BYTE_IT | THR_IT | RHR_IT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | EOF_IT | R/W | 0h |
|
6 | LINE_STS_IT | R/W | 0h |
|
5 | TX_STATUS_IT | R/W | 0h |
|
4 | STS_FIFO_TRIG_IT | R/W | 0h |
|
3 | RX_OVERRUN_IT | R/W | 0h |
|
2 | LAST_RX_BYTE_IT | R/W | 0h |
|
1 | THR_IT | R/W | 0h |
|
0 | RHR_IT | R/W | 0h |
|
UART_IER_CIR is shown in Figure 12-279 and described in Table 12-514.
Return to Summary Table.
There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (UART_EBLR). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case UART_MDR2[0] = 0.
Instance | Physical Address |
---|---|
UART0 | 0280 0004h |
UART1 | 0281 0004h |
UART2 | 0282 0004h |
UART3 | 0283 0004h |
UART4 | 0284 0004h |
UART5 | 0285 0004h |
UART6 | 0286 0004h |
MCU_UART0 | 04A0 0004h |
MCU_UART1 | 04A1 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOT_USED | TX_STATUS_IT | RESERVED | RX_OVERRUN_IT | RX_STOP_IT | THR_IT | RHR_IT | |
R/W-0h | R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | NOT_USED | R/W | 0h | |
5 | TX_STATUS_IT | R/W | 0h |
|
4 | RESERVED | R/W | X | |
3 | RX_OVERRUN_IT | R/W | 0h |
|
2 | RX_STOP_IT | R/W | 0h |
|
1 | THR_IT | R/W | 0h |
|
0 | RHR_IT | R/W | 0h |
|
UART_DLH is shown in Figure 12-280 and described in Table 12-516.
Return to Summary Table.
This register, with UART_DLL, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor.
Instance | Physical Address |
---|---|
UART0 | 0280 0004h |
UART1 | 0281 0004h |
UART2 | 0282 0004h |
UART3 | 0283 0004h |
UART4 | 0284 0004h |
UART5 | 0285 0004h |
UART6 | 0286 0004h |
MCU_UART0 | 04A0 0004h |
MCU_UART1 | 04A1 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLOCK_MSB | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h |
Reserved |
5-0 | CLOCK_MSB | R/W | 0h |
Stores the 6-bit MSB divisor value |
UART_IIR_UART is shown in Figure 12-281 and described in Table 12-518.
Return to Summary Table.
Interrupt identification register.
The UART_IIR_UART is a read-only register that
provides the source of the interrupt in a prioritized manner.
Instance | Physical Address |
---|---|
UART0 | 0280 0008h |
UART1 | 0281 0008h |
UART2 | 0282 0008h |
UART3 | 0283 0008h |
UART4 | 0284 0008h |
UART5 | 0285 0008h |
UART6 | 0286 0008h |
MCU_UART0 | 04A0 0008h |
MCU_UART1 | 04A1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FCR_MIRROR | IT_TYPE | IT_PENDING | |||||
R-0h | R-0h | R-1h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | FCR_MIRROR | R | 0h |
Mirror the contents of UART_FCR[0] on both bits. |
5-1 | IT_TYPE | R | 0h |
Read 0h = Modem
interrupt. Priority = 4 |
0 | IT_PENDING | R | 1h |
Read 0h = An
interrupt is pending. |
UART_IIR_IRDA is shown in Figure 12-282 and described in Table 12-520.
Return to Summary Table.
The interrupt line is activated whenever one of the 8 interrupts is active.
Instance | Physical Address |
---|---|
UART0 | 0280 0008h |
UART1 | 0281 0008h |
UART2 | 0282 0008h |
UART3 | 0283 0008h |
UART4 | 0284 0008h |
UART5 | 0285 0008h |
UART6 | 0286 0008h |
MCU_UART0 | 04A0 0008h |
MCU_UART1 | 04A1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOF_IT | LINE_STS_IT | TX_STATUS_IT | STS_FIFO_IT | RX_OE_IT | RX_FIFO_LAST_BYTE_IT | THR_IT | RHR_IT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | EOF_IT | R | 0h |
|
6 | LINE_STS_IT | R | 0h |
|
5 | TX_STATUS_IT | R | 0h |
|
4 | STS_FIFO_IT | R | 0h |
|
3 | RX_OE_IT | R | 0h |
|
2 | RX_FIFO_LAST_BYTE_IT | R | 0h |
|
1 | THR_IT | R | 0h |
|
0 | RHR_IT | R | 0h |
|
UART_IIR_CIR is shown in Figure 12-283 and described in Table 12-522.
Return to Summary Table.
The interrupt line is activated whenever one of the 6 interrupts is active.
Instance | Physical Address |
---|---|
UART0 | 0280 0008h |
UART1 | 0281 0008h |
UART2 | 0282 0008h |
UART3 | 0283 0008h |
UART4 | 0284 0008h |
UART5 | 0285 0008h |
UART6 | 0286 0008h |
MCU_UART0 | 04A0 0008h |
MCU_UART1 | 04A1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STATUS_IT | RESERVED | RX_OE_IT | RX_STOP_IT | THR_IT | RHR_IT | |
R-X | R-0h | R-X | R-0h | R-0h | R-0h | R-0h | |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | RESERVED | R | X | |
5 | TX_STATUS_IT | R | 0h |
Read 0h = TX
status interrupt inactive |
4 | RESERVED | R | X | |
3 | RX_OE_IT | R | 0h |
Read 0h = RX
overrun interrupt inactive |
2 | RX_STOP_IT | R | 0h |
Read 0h = Receive
stop interrupt inactive |
1 | THR_IT | R | 0h |
Read 0h = THR
interrupt inactive |
0 | RHR_IT | R | 0h |
Read 0h = RHR
interrupt inactive |
UART_FCR is shown in Figure 12-284 and described in Table 12-524.
Return to Summary Table.
FIFO control register
Notes: Bits 4 and 5 can only be written to when
UART_EFR[4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running
(DLL and DLH set to 0). See Table 12-459 for UART_FCR[5:4] setting restriction when UART_SCR[6] = 1. See Table 12-460 for UART_FCR[7:6] setting restriction when UART_SCR[7] = 1.
Instance | Physical Address |
---|---|
UART0 | 0280 0008h |
UART1 | 0281 0008h |
UART2 | 0282 0008h |
UART3 | 0283 0008h |
UART4 | 0284 0008h |
UART5 | 0285 0008h |
UART6 | 0286 0008h |
MCU_UART0 | 04A0 0008h |
MCU_UART1 | 04A1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_FIFO_TRIG | TX_FIFO_TRIG | DMA_MODE | TX_FIFO_CLEAR | RX_FIFO_CLEAR | FIFO_EN | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | RX_FIFO_TRIG | W | 0h |
Sets the trigger
level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] =
0000: |
5-4 | TX_FIFO_TRIG | W | 0h |
Sets the trigger
level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] =
0000: |
3 | DMA_MODE | W | 0h |
This register is
considered if UART_SCR[0] = 0. |
2 | TX_FIFO_CLEAR | W | 0h |
|
1 | RX_FIFO_CLEAR | W | 0h |
|
0 | FIFO_EN | W | 0h |
|
UART_EFR is shown in Figure 12-285 and described in Table 12-526.
Return to Summary Table.
Enhanced feature register
This register enables or disables enhanced features.
Most of the enhanced functions apply only to UART modes, but UART_EFR[4] enables
write accesses to UART_FCR[5:4], the TX trigger level, which is also used in IrDA
modes.
Instance | Physical Address |
---|---|
UART0 | 0280 0008h |
UART1 | 0281 0008h |
UART2 | 0282 0008h |
UART3 | 0283 0008h |
UART4 | 0284 0008h |
UART5 | 0285 0008h |
UART6 | 0286 0008h |
MCU_UART0 | 04A0 0008h |
MCU_UART1 | 04A1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTO_CTS_EN | AUTO_RTS_EN | SPECIAL_CHAR_DETECT | ENHANCED_EN | SW_FLOW_CONTROL | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | AUTO_CTS_EN | R/W | 0h |
Auto-CTS enable
bit |
6 | AUTO_RTS_EN | R/W | 0h |
Auto-RTS enable
bit |
5 | SPECIAL_CHAR_DETECT | R/W | 0h |
|
4 | ENHANCED_EN | R/W | 0h |
Enhanced functions
write enable bit |
3-0 | SW_FLOW_CONTROL | R/W | 0h |
Combinations of software flow control can be selected by programming bit 3 - bit 0. See UART_EFR[3:0] Software Flow Control Options. |
UART_LCR is shown in Figure 12-286 and described in Table 12-528.
Return to Summary Table.
Line control register UART_LCR[6:0] define transmission and reception parameters. Note: When UART_LCR[6] is set to 1, the TX line is forced to 0 and remains in this state as long as UART_LCR[6] = 1.
Instance | Physical Address |
---|---|
UART0 | 0280 000Ch |
UART1 | 0281 000Ch |
UART2 | 0282 000Ch |
UART3 | 0283 000Ch |
UART4 | 0284 000Ch |
UART5 | 0285 000Ch |
UART6 | 0286 000Ch |
MCU_UART0 | 04A0 000Ch |
MCU_UART1 | 04A1 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV_EN | BREAK_EN | PARITY_TYPE2 | PARITY_TYPE1 | PARITY_EN | NB_STOP | CHAR_LENGTH | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | DIV_EN | R/W | 0h |
|
6 | BREAK_EN | R/W | 0h |
Break control
bit |
5 | PARITY_TYPE2 | R/W | 0h |
Selects the forced parity format (if UART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR[4] = 1, the parity bit is forced to 0 in the transmitted and received data. |
4 | PARITY_TYPE1 | R/W | 0h |
|
3 | PARITY_EN | R/W | 0h |
0h = No parity |
2 | NB_STOP | R/W | 0h |
Specifies the
number of stop-bits |
1-0 | CHAR_LENGTH | R/W | 0h |
Specifies the word
length to be transmitted or received |
UART_MCR is shown in Figure 12-287 and described in Table 12-530.
Return to Summary Table.
Modem control register UART_MCR[3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem.
Instance | Physical Address |
---|---|
UART0 | 0280 0010h |
UART1 | 0281 0010h |
UART2 | 0282 0010h |
UART3 | 0283 0010h |
UART4 | 0284 0010h |
UART5 | 0285 0010h |
UART6 | 0286 0010h |
MCU_UART0 | 04A0 0010h |
MCU_UART1 | 04A1 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCR_TLR | XON_EN | LOOPBACK_EN | CD_STS_CH | RI_STS_CH | RTS | DTR |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | RESERVED | R | 0h | |
6 | TCR_TLR | R/W | 0h |
0h = No action |
5 | XON_EN | R/W | 0h |
0h = Disable XON
any function. |
4 | LOOPBACK_EN | R/W | 0h |
0h = Normal
operating mode |
3 | CD_STS_CH | R/W | 0h |
0h = In loopback,
forces DCD* input high and IRQ outputs to inactive state |
2 | RI_STS_CH | R/W | 0h |
0h = In loopback,
forces RI* input high |
1 | RTS | R/W | 0h |
In loopback,
controls the UART_MSR[4] bit. If auto-RTS is enabled, the RTS*
output is controlled by hardware flow control. |
0 | DTR | R/W | 0h |
0h = Force DTR*
output to inactive (high). |
UART_XON1_ADDR1 is shown in Figure 12-288 and described in Table 12-532.
Return to Summary Table.
UART mode: XON1 character, IrDA mode: ADDR1 address
Instance | Physical Address |
---|---|
UART0 | 0280 0010h |
UART1 | 0281 0010h |
UART2 | 0282 0010h |
UART3 | 0283 0010h |
UART4 | 0284 0010h |
UART5 | 0285 0010h |
UART6 | 0286 0010h |
MCU_UART0 | 04A0 0010h |
MCU_UART1 | 04A1 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XON_WORD1 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | XON_WORD1 | R/W | 0h |
Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes |
UART_LSR_UART is shown in Figure 12-289 and described in Table 12-534.
Return to Summary Table.
Line status register
Instance | Physical Address |
---|---|
UART0 | 0280 0014h |
UART1 | 0281 0014h |
UART2 | 0282 0014h |
UART3 | 0283 0014h |
UART4 | 0284 0014h |
UART5 | 0285 0014h |
UART6 | 0286 0014h |
MCU_UART0 | 04A0 0014h |
MCU_UART1 | 04A1 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_FIFO_STS | TX_SR_E | TX_FIFO_E | RX_BI | RX_FE | RX_PE | RX_OE | RX_FIFO_E |
R-0h | R-1h | R-1h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | RX_FIFO_STS | R | 0h |
Read 0h = Normal
operation |
6 | TX_SR_E | R | 1h |
Read 0h =
Transmitter hold (TX FIFO) and shift registers are not empty. |
5 | TX_FIFO_E | R | 1h |
Read 0h = Transmit
hold register (TX FIFO) is not empty. |
4 | RX_BI | R | 0h |
Read 0h = No break
condition |
3 | RX_FE | R | 0h |
Read 0h = No
framing error in data RX FIFO |
2 | RX_PE | R | 0h |
Read 0h = No
parity error in data from RX FIFO |
1 | RX_OE | R | 0h |
Read 0h = No
overrun error |
0 | RX_FIFO_E | R | 0h |
Read 0h = No data
in the RX FIFO |
UART_LSR_IRDA is shown in Figure 12-290 and described in Table 12-536.
Return to Summary Table.
When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read).
Instance | Physical Address |
---|---|
UART0 | 0280 0014h |
UART1 | 0281 0014h |
UART2 | 0282 0014h |
UART3 | 0283 0014h |
UART4 | 0284 0014h |
UART5 | 0285 0014h |
UART6 | 0286 0014h |
MCU_UART0 | 04A0 0014h |
MCU_UART1 | 04A1 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR_EMPTY | STS_FIFO_FULL | RX_LAST_BYTE | FRAME_TOO_LONG | ABORT | CRC | STS_FIFO_E | RX_FIFO_E |
R-1h | R-0h | R-0h | R-0h | R-0h | R-0h | R-1h | R-1h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | THR_EMPTY | R | 1h |
Read 0h = Transmit
holding register (TX FIFO) is not empty. |
6 | STS_FIFO_FULL | R | 0h |
Read 0h = Status
FIFO not full |
5 | RX_LAST_BYTE | R | 0h |
Read 0h = The RX
FIFO (RHR) does not contain the last byte of the frame to be
read. |
4 | FRAME_TOO_LONG | R | 0h |
Read 0h = No
frame-too-long error in frame |
3 | ABORT | R | 0h |
Read 0h = No abort
pattern error in frame |
2 | CRC | R | 0h |
Read 0h = No CRC
error in frame |
1 | STS_FIFO_E | R | 1h |
Read 0h = Status
FIFO not empty |
0 | RX_FIFO_E | R | 1h |
Read 0h = No data
in the RX FIFO |
UART_LSR_CIR is shown in Figure 12-291 and described in Table 12-538.
Return to Summary Table.
Line status register in CIR mode
Instance | Physical Address |
---|---|
UART0 | 0280 0014h |
UART1 | 0281 0014h |
UART2 | 0282 0014h |
UART3 | 0283 0014h |
UART4 | 0284 0014h |
UART5 | 0285 0014h |
UART6 | 0286 0014h |
MCU_UART0 | 04A0 0014h |
MCU_UART1 | 04A1 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR_EMPTY | RESERVED | RX_STOP | RESERVED | RX_FIFO_E | |||
R-1h | R-0h | R-0h | R-X | R-1h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | THR_EMPTY | R | 1h |
Read 0h = Transmit
holding register (TX FIFO) is not empty. |
6 | RESERVED | R | 0h | |
5 | RX_STOP | R | 0h |
The RX_STOP is
generated based on the value set in the BOF Length register
(UART_EBLR). It is cleared on a single read of the UART_LSR
register. |
4-1 | RESERVED | R | X | |
0 | RX_FIFO_E | R | 1h |
Read 0h = At least
one data character in the RX FIFO |
UART_XON2_ADDR2 is shown in Figure 12-292 and described in Table 12-540.
Return to Summary Table.
Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes
Instance | Physical Address |
---|---|
UART0 | 0280 0014h |
UART1 | 0281 0014h |
UART2 | 0282 0014h |
UART3 | 0283 0014h |
UART4 | 0284 0014h |
UART5 | 0285 0014h |
UART6 | 0286 0014h |
MCU_UART0 | 04A0 0014h |
MCU_UART1 | 04A1 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XON_WORD2 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | XON_WORD2 | R/W | 0h |
Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes |
UART_MSR is shown in Figure 12-293 and described in Table 12-542.
Return to Summary Table.
Modem status register. UART mode
only.
This register provides information about the
current state of the control lines from the modem, data set, or peripheral device to
the LH. It also indicates when a control input from the modem changes state.
Instance | Physical Address |
---|---|
UART0 | 0280 0018h |
UART1 | 0281 0018h |
UART2 | 0282 0018h |
UART3 | 0283 0018h |
UART4 | 0284 0018h |
UART5 | 0285 0018h |
UART6 | 0286 0018h |
MCU_UART0 | 04A0 0018h |
MCU_UART1 | 04A1 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCD_STS | NRI_STS | NDSR_STS | NCTS_STS | DCD_STS | RI_STS | DSR_STS | CTS_STS |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | NCD_STS | R | 0h |
This bit is the complement of the DCD* input. In loopback mode, it is equivalent to UART_MCR[3]. |
6 | NRI_STS | R | 0h |
This bit is the complement of the RI* input. In loopback mode, it is equivalent to UART_MCR[2]. |
5 | NDSR_STS | R | 0h |
This bit is the complement of the DSR* input. In loopback mode, it is equivalent to UART_MCR[0]. |
4 | NCTS_STS | R | 0h |
This bit is the complement of the CTS* input. In loopback mode, it is equivalent to UART_MCR[1]. |
3 | DCD_STS | R | 0h |
Indicates that DCD* input (or UART_MCR[3] in loopback) changed. Cleared on a read. |
2 | RI_STS | R | 0h |
Indicates that RI* input (or UART_MCR[2] in loopback) changed state from low to high. Cleared on a read. |
1 | DSR_STS | R | 0h |
|
0 | CTS_STS | R | 0h |
|
UART_XOFF1 is shown in Figure 12-294 and described in Table 12-544.
Return to Summary Table.
UART mode XOFF1 character
Instance | Physical Address |
---|---|
UART0 | 0280 0018h |
UART1 | 0281 0018h |
UART2 | 0282 0018h |
UART3 | 0283 0018h |
UART4 | 0284 0018h |
UART5 | 0285 0018h |
UART6 | 0286 0018h |
MCU_UART0 | 04A0 0018h |
MCU_UART1 | 04A1 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XOFF_WORD1 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | XOFF_WORD1 | R/W | 0h |
Stores the 8-bit XOFF1 character used in UART modes |
UART_TCR is shown in Figure 12-295 and described in Table 12-546.
Return to Summary Table.
Transmission control register
This register stores the RX FIFO threshold levels to
start/stop transmission during hardware/software flow control. Notes: Trigger levels
from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x
[4-bit register value]) The programmer must ensure that UART_TCR[3:0] >
UART_TCR[7:4] when auto-RTS or software flow control is enabled to avoid a
mis-operation of the device. In FIFO interrupt mode with flow control, the
programmer must ensure that the trigger level to halt transmission is greater than
or equal to the RX FIFO trigger level (UART_TLR[7:4] or UART_FCR[7:6]); otherwise,
FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not
exist because a DMA request is sent each time a byte is received.
Instance | Physical Address |
---|---|
UART0 | 0280 0018h |
UART1 | 0281 0018h |
UART2 | 0282 0018h |
UART3 | 0283 0018h |
UART4 | 0284 0018h |
UART5 | 0285 0018h |
UART6 | 0286 0018h |
MCU_UART0 | 04A0 0018h |
MCU_UART1 | 04A1 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_FIFO_TRIG_START | RX_FIFO_TRIG_HALT | ||||||
R/W-0h | R/W-Fh | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-4 | RX_FIFO_TRIG_START | R/W | 0h |
RX FIFO trigger level to RESTORE transmission (0 - 60) |
3-0 | RX_FIFO_TRIG_HALT | R/W | Fh |
RX FIFO trigger level to HALT transmission (0 - 60) |
UART_SPR is shown in Figure 12-296 and described in Table 12-548.
Return to Summary Table.
Scratchpad register
This read/write register does not control the module.
It is a scratchpad register to be used by the programmer to hold temporary data.
Instance | Physical Address |
---|---|
UART0 | 0280 001Ch |
UART1 | 0281 001Ch |
UART2 | 0282 001Ch |
UART3 | 0283 001Ch |
UART4 | 0284 001Ch |
UART5 | 0285 001Ch |
UART6 | 0286 001Ch |
MCU_UART0 | 04A0 001Ch |
MCU_UART1 | 04A1 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPR_WORD | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | SPR_WORD | R/W | 0h |
Scratchpad register |
UART_XOFF2 is shown in Figure 12-297 and described in Table 12-550.
Return to Summary Table.
UART mode XOFF2 character
Instance | Physical Address |
---|---|
UART0 | 0280 001Ch |
UART1 | 0281 001Ch |
UART2 | 0282 001Ch |
UART3 | 0283 001Ch |
UART4 | 0284 001Ch |
UART5 | 0285 001Ch |
UART6 | 0286 001Ch |
MCU_UART0 | 04A0 001Ch |
MCU_UART1 | 04A1 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XOFF_WORD2 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | XOFF_WORD2 | R/W | 0h |
Stores the 8-bit XOFF2 character used in UART modes. |
UART_TLR is shown in Figure 12-298 and described in Table 12-552.
Return to Summary Table.
Trigger level register
This register stores the programmable transmit and RX
FIFO trigger levels for DMA and IRQ generation.
Instance | Physical Address |
---|---|
UART0 | 0280 001Ch |
UART1 | 0281 001Ch |
UART2 | 0282 001Ch |
UART3 | 0283 001Ch |
UART4 | 0284 001Ch |
UART5 | 0285 001Ch |
UART6 | 0286 001Ch |
MCU_UART0 | 04A0 001Ch |
MCU_UART1 | 04A1 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_FIFO_TRIG_DMA | TX_FIFO_TRIG_DMA | ||||||
R/W-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-4 | RX_FIFO_TRIG_DMA | R/W | 0h |
Receive FIFO trigger level |
3-0 | TX_FIFO_TRIG_DMA | R/W | 0h |
Transmit FIFO trigger level |
UART_MDR1 is shown in Figure 12-299 and described in Table 12-554.
Return to Summary Table.
Mode definition register 1
The mode of operation can be programmed by writing to
MDR1[2:0] and therefore the UART_MDR1 must be programmed on startup after
configuration of the configuration registers (UART_DLL, UART_DLH, and UART_LCR). The
value of MDR1[2:0] must not be changed again during normal operation. Note: If the
module is disabled by setting the MODE_SELECT field to 111, interrupt requests can
still be generated unless disabled through the interrupt enable register (UART_IER).
In this case, UART mode interrupts are visible. Reading the interrupt identification
register (UART_IIR) shows UART mode interrupt flags.
Instance | Physical Address |
---|---|
UART0 | 0280 0020h |
UART1 | 0281 0020h |
UART2 | 0282 0020h |
UART3 | 0283 0020h |
UART4 | 0284 0020h |
UART5 | 0285 0020h |
UART6 | 0286 0020h |
MCU_UART0 | 04A0 0020h |
MCU_UART1 | 04A1 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAME_END_MODE | SIP_MODE | SCT | SET_TXIR | IR_SLEEP | MODE_SELECT | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-7h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | FRAME_END_MODE | R/W | 0h |
IrDA mode only |
6 | SIP_MODE | R/W | 0h |
MIR/FIR modes
only |
5 | SCT | R/W | 0h |
Store and control
the transmission. |
4 | SET_TXIR | R/W | 0h |
Used to configure
the infrared transceiver |
3 | IR_SLEEP | R/W | 0h |
0h = IrDA/CIR
sleep mode disabled |
2-0 | MODE_SELECT | R/W | 7h |
0h = UART 16x
mode |
UART_MDR2 is shown in Figure 12-300 and described in Table 12-556.
Return to Summary Table.
Mode definition register 2
IR-IrDA and IR-CIR modes only. UART_MDR2[0] describes
the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read
after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the
trigger level for the frame status FIFO (8 entries) and must be programmed before
the mode is programmed in UART_MDR1[2:0].
Note: The
UART_MDR2[6] gives the flexibility to invert the RX pin in the UART to ensure that
the protocol at the input of the transceiver module has the same polarity at module
level. By default, the RX pin is inverted because most transceivers invert the IR
receive pin.
Instance | Physical Address |
---|---|
UART0 | 0280 0024h |
UART1 | 0281 0024h |
UART2 | 0282 0024h |
UART3 | 0283 0024h |
UART4 | 0284 0024h |
UART5 | 0285 0024h |
UART6 | 0286 0024h |
MCU_UART0 | 04A0 0024h |
MCU_UART1 | 04A1 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET_TXIR_ALT | IRRXINVERT | CIR_PULSE_MODE | UART_PULSE | STS_FIFO_TRIG | IRTX_UNDERRUN | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | SET_TXIR_ALT | R/W | 0h |
Provide alternate
function for UART_MDR1[4] (SET_TXIR). |
6 | IRRXINVERT | R/W | 0h |
IR mode only (IrDA
and CIR). Invert RX pin in the module before the voting or
sampling system logic of the infrared block. This does not
affect the RX path in UART modem modes. |
5-4 | CIR_PULSE_MODE | R/W | 0h |
CIR pulse
modulation definition. Defines high level of the pulse width
associated with a digit: |
3 | UART_PULSE | R/W | 0h |
UART mode only.
Allows pulse shaping in UART mode. |
2-1 | STS_FIFO_TRIG | R/W | 0h |
IR-IrDA mode only.
Frame status FIFO threshold select: |
0 | IRTX_UNDERRUN | R | 0h |
IrDA transmission
status interrupt. When the UART_IIR[5] interrupt occurs, the
meaning of the interrupt is: |
UART_SFLSR is shown in Figure 12-301 and described in Table 12-558.
Return to Summary Table.
Status FIFO line status register
IrDA modes only. Reading this register effectively
reads frame status information from the status FIFO (this register does not
physically exist). Reading this register increments the status FIFO read pointer
(UART_SFREGL and UART_SFREGH must be read first).
Instance | Physical Address |
---|---|
UART0 | 0280 0028h |
UART1 | 0281 0028h |
UART2 | 0282 0028h |
UART3 | 0283 0028h |
UART4 | 0284 0028h |
UART5 | 0285 0028h |
UART6 | 0286 0028h |
MCU_UART0 | 04A0 0028h |
MCU_UART1 | 04A1 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OE_ERROR | FRAME_TOO_LONG_ERROR | ABORT_DETECT | CRC_ERROR | RESERVED | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-5 | RESERVED | R | 0h | |
4 | OE_ERROR | R | 0h |
Read 1h = Overrun
error in RX FIFO when frame at top of RX FIFO was received |
3 | FRAME_TOO_LONG_ERROR | R | 0h |
Read 1h = Frame-length too long error in frame at top of RX FIFO |
2 | ABORT_DETECT | R | 0h |
Read 1h = Abort pattern detected in frame at top of RX FIFO |
1 | CRC_ERROR | R | 0h |
Read 1h = CRC error in frame at top of RX FIFO |
0 | RESERVED | R | 0h |
UART_TXFLL is shown in Figure 12-302 and described in Table 12-560.
Return to Summary Table.
Transmit frame length register low
IrDA modes only. The UART_TXFLL and UART_TXFLH
registers hold the 13-bit transmit frame length (expressed in bytes). UART_TXFLL
holds the LSBs and UART_TXFLH holds the MSBs. The frame length value is used if the
frame length method of frame closing is used.
Instance | Physical Address |
---|---|
UART0 | 0280 0028h |
UART1 | 0281 0028h |
UART2 | 0282 0028h |
UART3 | 0283 0028h |
UART4 | 0284 0028h |
UART5 | 0285 0028h |
UART6 | 0286 0028h |
MCU_UART0 | 04A0 0028h |
MCU_UART1 | 04A1 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXFLL | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | TXFLL | W | 0h |
LSB register used to specify the frame length |
UART_RESUME is shown in Figure 12-303 and described in Table 12-562.
Return to Summary Table.
IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00.
Instance | Physical Address |
---|---|
UART0 | 0280 002Ch |
UART1 | 0281 002Ch |
UART2 | 0282 002Ch |
UART3 | 0283 002Ch |
UART4 | 0284 002Ch |
UART5 | 0285 002Ch |
UART6 | 0286 002Ch |
MCU_UART0 | 04A0 002Ch |
MCU_UART1 | 04A1 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESUME | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | RESUME | R | 0h |
Dummy read to restart the TX or RX |
UART_TXFLH is shown in Figure 12-304 and described in Table 12-564.
Return to Summary Table.
Transmit frame length register high
IrDA modes only. The UART_TXFLL and UART_TXFLH
registers hold the 13-bit transmit frame length (expressed in bytes). UART_TXFLL
holds the LSBs and UART_TXFLH holds the MSBs. The frame length value is used if the
frame length method of frame closing is used.
Instance | Physical Address |
---|---|
UART0 | 0280 002Ch |
UART1 | 0281 002Ch |
UART2 | 0282 002Ch |
UART3 | 0283 002Ch |
UART4 | 0284 002Ch |
UART5 | 0285 002Ch |
UART6 | 0286 002Ch |
MCU_UART0 | 04A0 002Ch |
MCU_UART1 | 04A1 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TXFLH | |||||||||||||
R-0h | R-0h | W-0h | |||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-5 | RESERVED | R | 0h | |
4-0 | TXFLH | W | 0h |
MSB register used to specify the frame length |
UART_SFREGL is shown in Figure 12-305 and described in Table 12-566.
Return to Summary Table.
Status FIFO register low
IrDA modes only. The frame lengths of received frames
are written into the status FIFO. This information can be read by reading the
UART_SFREGL and UART_SFREGH registers (these registers do not physically exist). The
LSBs are read from UART_SFREGL and the MSBs are read from UART_SFREGH. Reading these
registers does not alter the status FIFO read pointer. These registers should be
read before the pointer is incremented by reading the UART_SFLSR register.
Instance | Physical Address |
---|---|
UART0 | 0280 0030h |
UART1 | 0281 0030h |
UART2 | 0282 0030h |
UART3 | 0283 0030h |
UART4 | 0284 0030h |
UART5 | 0285 0030h |
UART6 | 0286 0030h |
MCU_UART0 | 04A0 0030h |
MCU_UART1 | 04A1 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SFREGL | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | SFREGL | R | 0h |
LSB part of the frame length |
UART_RXFLL is shown in Figure 12-306 and described in Table 12-568.
Return to Summary Table.
Received frame length register low
IrDA modes only. The UART_RXFLL and UART_RXFLH
registers hold the 12-bit receive maximum frame length. UART_RXFLL holds the LSBs
and UART_RXFLH holds the MSBs. If the intended maximum receive frame length is n
bytes, program the UART_RXFLL and UART_RXFLH registers to be n + 3 in SIR or MIR
modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and
stop flag; 2 bytes are associated with the FIR stop flag).
Instance | Physical Address |
---|---|
UART0 | 0280 0030h |
UART1 | 0281 0030h |
UART2 | 0282 0030h |
UART3 | 0283 0030h |
UART4 | 0284 0030h |
UART5 | 0285 0030h |
UART6 | 0286 0030h |
MCU_UART0 | 04A0 0030h |
MCU_UART1 | 04A1 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXFLL | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | RXFLL | W | 0h |
LSB register used to specify the frame length in reception |
UART_SFREGH is shown in Figure 12-307 and described in Table 12-570.
Return to Summary Table.
Status FIFO register high
IrDA modes only. The frame lengths of received frames
are written into the status FIFO. This information can be read by reading the
UART_SFREGL and UART_SFREGH registers (these registers do not physically exist). The
LSBs are read from UART_SFREGL and the MSBs are read from UART_SFREGH. Reading these
registers does not alter the status FIFO read pointer. These registers should be
read before the pointer is incremented by reading the UART_SFLSR register.
Instance | Physical Address |
---|---|
UART0 | 0280 0034h |
UART1 | 0281 0034h |
UART2 | 0282 0034h |
UART3 | 0283 0034h |
UART4 | 0284 0034h |
UART5 | 0285 0034h |
UART6 | 0286 0034h |
MCU_UART0 | 04A0 0034h |
MCU_UART1 | 04A1 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SFREGH | |||||||||||||
R-0h | R-0h | R-0h | |||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-4 | RESERVED | R | 0h | |
3-0 | SFREGH | R | 0h |
MSB part of the frame length |
UART_RXFLH is shown in Figure 12-308 and described in Table 12-572.
Return to Summary Table.
Received frame length register high
IrDA modes only. The UART_RXFLL and UART_RXFLH
registers hold the 12-bit receive maximum frame length. UART_RXFLL holds the LSBs
and UART_RXFLH holds the MSBs. If the intended maximum receive frame length is n
bytes, program the UART_RXFLL and UART_RXFLH to be n + 3 in SIR or MIR modes and n +
6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2
bytes are associated with the FIR stop flag).
Instance | Physical Address |
---|---|
UART0 | 0280 0034h |
UART1 | 0281 0034h |
UART2 | 0282 0034h |
UART3 | 0283 0034h |
UART4 | 0284 0034h |
UART5 | 0285 0034h |
UART6 | 0286 0034h |
MCU_UART0 | 04A0 0034h |
MCU_UART1 | 04A1 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RXFLH | |||||||||||||
R-0h | R-0h | W-0h | |||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-4 | RESERVED | R | 0h | |
3-0 | RXFLH | W | 0h |
MSB register used to specify the frame length in reception |
UART_BLR is shown in Figure 12-309 and described in Table 12-574.
Return to Summary Table.
BOF control register
IrDA modes only. The UART_BLR[6] bit selects whether
0xC0 or 0xFF start patterns are to be used, when multiple start flags are required
in SIR mode. If only one start flag is required, this is always 0xC0. If n start
flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0
flag (immediately preceding the first data byte).
Instance | Physical Address |
---|---|
UART0 | 0280 0038h |
UART1 | 0281 0038h |
UART2 | 0282 0038h |
UART3 | 0283 0038h |
UART4 | 0284 0038h |
UART5 | 0285 0038h |
UART6 | 0286 0038h |
MCU_UART0 | 04A0 0038h |
MCU_UART1 | 04A1 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS_FIFO_RESET | XBOF_TYPE | RESERVED | |||||
R/W1S-0h | R/W-1h | R-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | STS_FIFO_RESET | R/W1S | 0h |
Status FIFO reset. This bit is self-clearing. |
6 | XBOF_TYPE | R/W | 1h |
SIR xBOF select |
5-0 | RESERVED | R | 0h |
UART_UASR is shown in Figure 12-310 and described in Table 12-576.
Return to Summary Table.
UART autobauding status register
UART autobauding mode only. This status register
returns the speed, the number of bits by characters, and the type of the parity in
UART autobauding mode. In autobauding mode, the input frequency of the UART modem
must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud
rate recognition.
Note: When the UART is in
autobauding mode, this register, instead of the UART_LCR, UART_DLL, and UART_DLH
registers, is used to set up transmission according to the characteristics of the
previous reception.
To reset the autobauding hardware
(to start a new AT detection), set UART_MDR1[2:0] to 111 (reset value), then set
UART_MDR1[2:1] to 010 (UART in autobaud mode).
To set
the UART to standard mode (no autobaud), set UART_MDR1[2:1] to 000.
Instance | Physical Address |
---|---|
UART0 | 0280 0038h |
UART1 | 0281 0038h |
UART2 | 0282 0038h |
UART3 | 0283 0038h |
UART4 | 0284 0038h |
UART5 | 0285 0038h |
UART6 | 0286 0038h |
MCU_UART0 | 04A0 0038h |
MCU_UART1 | 04A1 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PARITY_TYPE | BIT_BY_CHAR | SPEED | |||||
R-0h | R-0h | R-0h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | PARITY_TYPE | R | 0h |
Read 0h = No
parity identified |
5 | BIT_BY_CHAR | R | 0h |
Read 0h = 7-bit
character identified |
4-0 | SPEED | R | 0h |
Used to report the
speed identified |
UART_ACREG is shown in Figure 12-311 and described in Table 12-578.
Return to Summary Table.
Auxiliary control register. IR-IrDA and IR-CIR modes only.
Instance | Physical Address |
---|---|
UART0 | 0280 003Ch |
UART1 | 0281 003Ch |
UART2 | 0282 003Ch |
UART3 | 0283 003Ch |
UART4 | 0284 003Ch |
UART5 | 0285 003Ch |
UART6 | 0286 003Ch |
MCU_UART0 | 04A0 003Ch |
MCU_UART1 | 04A1 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PULSE_TYPE | SD_MOD | DIS_IR_RX | DIS_TX_UNDERRUN | SEND_SIP | SCTX_EN | ABORT_EN | EOT_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W1S-0h | R/W1S-0h | R/W-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | PULSE_TYPE | R/W | 0h |
SIR pulse width
select |
6 | SD_MOD | R/W | 0h |
Primary output
used to configure transceivers. Connected to the SD/MODE input
pin of IrDA transceivers. |
5 | DIS_IR_RX | R/W | 0h |
0h = Normal
operation (RX input automatically disabled during transmit but
enabled outside of transmit operation) |
4 | DIS_TX_UNDERRUN | R/W | 0h |
It is recommended
to disable TX FIFO underrun capability by masking corresponding
underrun interrupt. When disabling underrun by setting
UART_ACREG[4] = 1, garbage data is sent over TX line. |
3 | SEND_SIP | R/W1S | 0h |
MIR/FIR modes
only. Send serial infrared interaction pulse (SIP). If this bit
is set during an MIR/FIR transmission, the SIP is sent at the
end of it. This bit is cleared automatically at the end of the
SIP transmission. |
2 | SCTX_EN | R/W1S | 0h |
Store and controlled TX start. When UART_MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing. |
1 | ABORT_EN | R/W | 0h |
Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and UART_MDR1[5] = 1, UART IrDA starts a new transfer with data of the previous frame when the abort frame is sent. Therefore, TX FIFO must be reset before sending an abort frame. |
0 | EOT_EN | R/W1S | 0h |
EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO). |
UART_SCR is shown in Figure 12-312 and described in Table 12-580.
Return to Summary Table.
Supplementary control register
Note: Bit 4 enables the wake-up interrupt, but this
interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt
occurs and there is no interrupt pending in the UART_IIR register, the UART_SSR[1]
bit must be checked. To clear the wake-up interrupt, bit UART_SCR[4] must be reset
to 0.
Instance | Physical Address |
---|---|
UART0 | 0280 0040h |
UART1 | 0281 0040h |
UART2 | 0282 0040h |
UART3 | 0283 0040h |
UART4 | 0284 0040h |
UART5 | 0285 0040h |
UART6 | 0286 0040h |
MCU_UART0 | 04A0 0040h |
MCU_UART1 | 04A1 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_TRIG_GRANU1 | TX_TRIG_GRANU1 | DSR_IT | RX_CTS_DSR_WAKE_UP_ENABLE | TX_EMPTY_CTL_IT | DMA_MODE_2 | DMA_MODE_CTL | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | RX_TRIG_GRANU1 | R/W | 0h |
0h = Disables the
granularity of 1 for trigger RX level |
6 | TX_TRIG_GRANU1 | R/W | 0h |
0h = Disables the
granularity of 1 for trigger TX level |
5 | DSR_IT | R/W | 0h |
0h = Disables DSR*
interrupt |
4 | RX_CTS_DSR_WAKE_UP_ENABLE | R/W | 0h |
0h = Disables the
wake-up interrupt and clears SSR[1] |
3 | TX_EMPTY_CTL_IT | R/W | 0h |
0h = Normal mode
for THR interrupt |
2-1 | DMA_MODE_2 | R/W | 0h |
Used to specify
the DMA mode valid if the UART_SCR[0] bit = 1 |
0 | DMA_MODE_CTL | R/W | 0h |
0h = The DMA_MODE
is set with UART_FCR[3]. |
UART_SSR is shown in Figure 12-313 and described in Table 12-582.
Return to Summary Table.
Supplementary status register
Note: Bit 1 is reset only when UART_SCR[4] is reset
to 0.
Instance | Physical Address |
---|---|
UART0 | 0280 0044h |
UART1 | 0281 0044h |
UART2 | 0282 0044h |
UART3 | 0283 0044h |
UART4 | 0284 0044h |
UART5 | 0285 0044h |
UART6 | 0286 0044h |
MCU_UART0 | 04A0 0044h |
MCU_UART1 | 04A1 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA_COUNTER_RST | RX_CTS_DSR_WAKE_UP_STS | TX_FIFO_FULL | ||||
R-0h | R/W-1h | R-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-3 | RESERVED | R | 0h | |
2 | DMA_COUNTER_RST | R/W | 1h |
0h = The DMA
counter will not be reset if the corresponding FIFO is reset
(through UART_FCR[1] or UART_FCR[2]). |
1 | RX_CTS_DSR_WAKE_UP_STS | R | 0h |
Read 0h = No
falling edge event on RX, CTS*, and DSR* |
0 | TX_FIFO_FULL | R | 0h |
Read 0h = TX FIFO
is not full. |
UART_EBLR is shown in Figure 12-314 and described in Table 12-584.
Return to Summary Table.
BOF length register
IR-IrDA and IR-CIR modes only. In IR-IrDA SIR
operation, this register specifies the number of BOF + xBOFs to transmit. Value set
into this register must account for the BOF character; therefore, to send only one
BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this
register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR
mode, this register specifies the number of additional start flags (MIR protocol
mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the
number of consecutive 0s to be received before generating the RX_STOP interrupt
(UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set
to 0, this feature is deactivated and always in reception state, which can be
disabled by setting the UART_ACREG[5] to 1.
Note: If
the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last
byte are filled with 0s and passed into the RX FIFO.
Instance | Physical Address |
---|---|
UART0 | 0280 0048h |
UART1 | 0281 0048h |
UART2 | 0282 0048h |
UART3 | 0283 0048h |
UART4 | 0284 0048h |
UART5 | 0285 0048h |
UART6 | 0286 0048h |
MCU_UART0 | 04A0 0048h |
MCU_UART1 | 04A1 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EBLR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | EBLR | R/W | 0h |
IR-IrDA mode: This
register allows definition of up to 176 xBOFs, the maximum
required by IrDA specification. |
UART_MVR is shown in Figure 12-315 and described in Table 12-586.
Return to Summary Table.
Module version register
The reset value is fixed by hardware and corresponds
to the RTL revision of this module. A reset has no effect on the value returned.
Instance | Physical Address |
---|---|
UART0 | 0280 0050h |
UART1 | 0281 0050h |
UART2 | 0282 0050h |
UART3 | 0283 0050h |
UART4 | 0284 0050h |
UART5 | 0285 0050h |
UART6 | 0286 0050h |
MCU_UART0 | 04A0 0050h |
MCU_UART1 | 04A1 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SCHEME | RESERVED | FUNC | |||||
R-1h | R-0h | R-742h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FUNC | |||||||
R-742h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RTL | MAJOR | ||||||
8h | R-6h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM | MINOR | ||||||
R-0h | R-3h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h |
Scheme revision number of module |
29-28 | RESERVED | R | 0h | |
27-16 | FUNC | R | 742h |
Function revision number of module |
15-11 | RTL | R | 8h |
Rtl revision number of module |
10-8 | MAJOR | R | 6h |
Major revision number of the module |
7-6 | CUSTOM | R | 0h |
Custom revision number of the module |
5-0 | MINOR | R | 3h |
Minor revision number of the module |
UART_SYSC is shown in Figure 12-316 and described in Table 12-588.
Return to Summary Table.
System configuration register
The AUTOIDLE bit controls a power-saving technique to
reduce the logic power consumption of the open-core protocol (OCP) interface. When
the feature is enabled, the clock is gated off until an OCP command for this device
is detected. When the software reset bit is set high, it causes a full device
reset.
Instance | Physical Address |
---|---|
UART0 | 0280 0054h |
UART1 | 0281 0054h |
UART2 | 0282 0054h |
UART3 | 0283 0054h |
UART4 | 0284 0054h |
UART5 | 0285 0054h |
UART6 | 0286 0054h |
MCU_UART0 | 04A0 0054h |
MCU_UART1 | 04A1 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEMODE | ENAWAKEUP | SOFTRESET | AUTOIDLE | |||
R-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-5 | RESERVED | R | 0h | |
4-3 | IDLEMODE | R/W | 0h |
Power management
req/ack control ref: OCP Design Guidelines Version 1.1 |
2 | ENAWAKEUP | R/W | 0h |
Wake-up feature
control |
1 | SOFTRESET | W | 0h |
Software reset.
Set this bit to 1 to trigger a module reset. This bit is
automatically reset by the hardware. Read returns 0. |
0 | AUTOIDLE | R/W | 0h |
Internal OCP clock
gating strategy |
UART_SYSS is shown in Figure 12-317 and described in Table 12-590.
Return to Summary Table.
System status register
Instance | Physical Address |
---|---|
UART0 | 0280 0058h |
UART1 | 0281 0058h |
UART2 | 0282 0058h |
UART3 | 0283 0058h |
UART4 | 0284 0058h |
UART5 | 0285 0058h |
UART6 | 0286 0058h |
MCU_UART0 | 04A0 0058h |
MCU_UART1 | 04A1 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETDONE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-1 | RESERVED | R | 0h | |
0 | RESETDONE | R | 0h |
Internal reset
monitoring |
UART_WER is shown in Figure 12-318 and described in Table 12-592.
Return to Summary Table.
Wake-up enable register
The UART wake-up enable register is used to mask and
unmask a UART event that would subsequently notify the system. An event is any
activity in the logic that could cause an interrupt and/or an activity that would
require the system to wake up. Even if the wakeup is disabled for certain events, if
these events are also an interrupt to the UART, the UART registers the
interrupt.
Instance | Physical Address |
---|---|
UART0 | 0280 005Ch |
UART1 | 0281 005Ch |
UART2 | 0282 005Ch |
UART3 | 0283 005Ch |
UART4 | 0284 005Ch |
UART5 | 0285 005Ch |
UART6 | 0286 005Ch |
MCU_UART0 | 04A0 005Ch |
MCU_UART1 | 04A1 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVENT_7_TX_WAKEUP_EN | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT | EVENT_5_RHR_INTERRUPT | EVENT_4_RX_ACTIVITY | EVENT_3_DCD_CD_ACTIVITY | EVENT_2_RI_ACTIVITY | EVENT_1_DSR_ACTIVITY | EVENT_0_CTS_ACTIVITY |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | EVENT_7_TX_WAKEUP_EN | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
6 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
5 | EVENT_5_RHR_INTERRUPT | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
4 | EVENT_4_RX_ACTIVITY | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
3 | EVENT_3_DCD_CD_ACTIVITY | R/W | 1h |
0h = Event is not
allowed to wake up the system |
2 | EVENT_2_RI_ACTIVITY | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
1 | EVENT_1_DSR_ACTIVITY | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
0 | EVENT_0_CTS_ACTIVITY | R/W | 1h |
0h = Event is not
allowed to wake up the system. |
UART_CFPS is shown in Figure 12-319 and described in Table 12-594.
Return to Summary Table.
Carrier frequency prescaler
Because the consumer IR works at modulation rates of
30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR
logic. This register sets the divisor rate to give a range to accommodate the
remote-control requirements in baud multiples of 12x. The value of the CFPS at reset
is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz
carrier is prescaled by the CFPS, which is then divided by the 12x baud
multiple.
Instance | Physical Address |
---|---|
UART0 | 0280 0060h |
UART1 | 0281 0060h |
UART2 | 0282 0060h |
UART3 | 0283 0060h |
UART4 | 0284 0060h |
UART5 | 0285 0060h |
UART6 | 0286 0060h |
MCU_UART0 | 04A0 0060h |
MCU_UART1 | 04A1 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CFPS | ||||||||||||||||||||||||||||||
R-0h | R/W-69h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | CFPS | R/W | 69h |
System clock
frequency prescaler at (12x multiple). Examples for CFPS
values: |
UART_RXFIFO_LVL is shown in Figure 12-320 and described in Table 12-596.
Return to Summary Table.
Level of the RX FIFO
Instance | Physical Address |
---|---|
UART0 | 0280 0064h |
UART1 | 0281 0064h |
UART2 | 0282 0064h |
UART3 | 0283 0064h |
UART4 | 0284 0064h |
UART5 | 0285 0064h |
UART6 | 0286 0064h |
MCU_UART0 | 04A0 0064h |
MCU_UART1 | 04A1 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXFIFO_LVL | ||||||||||||||
R-0h | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | RXFIFO_LVL | R | 0h |
Shows the number of received bytes in the RX FIFO |
UART_TXFIFO_LVL is shown in Figure 12-321 and described in Table 12-598.
Return to Summary Table.
Level of the TX FIFO
Instance | Physical Address |
---|---|
UART0 | 0280 0068h |
UART1 | 0281 0068h |
UART2 | 0282 0068h |
UART3 | 0283 0068h |
UART4 | 0284 0068h |
UART5 | 0285 0068h |
UART6 | 0286 0068h |
MCU_UART0 | 04A0 0068h |
MCU_UART1 | 04A1 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXFIFO_LVL | ||||||||||||||
R-0h | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | TXFIFO_LVL | R | 0h |
Shows the number of written bytes in the TX FIFO |
UART_IER2 is shown in and described in Table 12-600.
Return to Summary Table.
Enables RX/TX FIFOs empty corresponding interrupts
Instance | Physical Address |
---|---|
UART0 | 0280 006Ch |
UART1 | 0281 006Ch |
UART2 | 0282 006Ch |
UART3 | 0283 006Ch |
UART4 | 0284 006Ch |
UART5 | 0285 006Ch |
UART6 | 0286 006Ch |
MCU_UART0 | 04A0 006Ch |
MCU_UART1 | 04A1 006Ch |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
2 | RHR_IT_DIS | R/W | 0h |
0h = Enables the
RHR interrupt. |
1 | EN_TXFIFO_EMPTY | R/W | 0h |
Enables TX FIFO
empty corresponding interrupt |
0 | EN_RXFIFO_EMPTY | R/W | 0h |
Enables RX FIFO
empty corresponding interrupt |
UART_ISR2 is shown in Figure 12-322 and described in Table 12-602.
Return to Summary Table.
Status of RX/TX FIFOs empty corresponding interrupts
Instance | Physical Address |
---|---|
UART0 | 0280 0070h |
UART1 | 0281 0070h |
UART2 | 0282 0070h |
UART3 | 0283 0070h |
UART4 | 0284 0070h |
UART5 | 0285 0070h |
UART6 | 0286 0070h |
MCU_UART0 | 04A0 0070h |
MCU_UART1 | 04A1 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXFIFO_EMPTY_STS | RXFIFO_EMPTY_STS | |||||
R-0h | R/W1C-1h | R/W1C-1h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-2 | RESERVED | R | 0h | |
1 | TXFIFO_EMPTY_STS | R/W1C | 1h |
Used to generate
interrupt if the TX_FIFO is empty (software flow control) |
0 | RXFIFO_EMPTY_STS | R/W1C | 1h |
Used to generate
interrupt if the RX_FIFO is empty (software flow control) |
UART_FREQ_SEL is shown in Figure 12-323 and described in Table 12-604.
Return to Summary Table.
Sample per bit selector
Instance | Physical Address |
---|---|
UART0 | 0280 0074h |
UART1 | 0281 0074h |
UART2 | 0282 0074h |
UART3 | 0283 0074h |
UART4 | 0284 0074h |
UART5 | 0285 0074h |
UART6 | 0286 0074h |
MCU_UART0 | 04A0 0074h |
MCU_UART1 | 04A1 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FREQ_SEL | ||||||||||||||||||||||||||||||
R-0h | R/W-1Ah | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h |
RESERVED |
7-0 | FREQ_SEL | R/W | 1Ah |
Sets the sample per bit if nondefault frequency is used. UART_MDR3[1] must be set to 1 after this value is set. Must be equal to or higher than 6. |
UART_ABAUD_1ST_CHAR is shown in Figure 12-324 and described in Table 12-606.
Return to Summary Table.
Unused
Instance | Physical Address |
---|---|
UART0 | 0280 0078h |
UART1 | 0281 0078h |
UART2 | 0282 0078h |
UART3 | 0283 0078h |
UART4 | 0284 0078h |
UART5 | 0285 0078h |
UART6 | 0286 0078h |
MCU_UART0 | 04A0 0078h |
MCU_UART1 | 04A1 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h |
UART_BAUD_2ND_CHAR is shown in Figure 12-325 and described in Table 12-608.
Return to Summary Table.
Unused
Instance | Physical Address |
---|---|
UART0 | 0280 007Ch |
UART1 | 0281 007Ch |
UART2 | 0282 007Ch |
UART3 | 0283 007Ch |
UART4 | 0284 007Ch |
UART5 | 0285 007Ch |
UART6 | 0286 007Ch |
MCU_UART0 | 04A0 007Ch |
MCU_UART1 | 04A1 007Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h |
UART_MDR3 is shown in Figure 12-326 and described in Table 12-610.
Return to Summary Table.
Mode definition register 3
Instance | Physical Address |
---|---|
UART0 | 0280 0080h |
UART1 | 0281 0080h |
UART2 | 0282 0080h |
UART3 | 0283 0080h |
UART4 | 0284 0080h |
UART5 | 0285 0080h |
UART6 | 0286 0080h |
MCU_UART0 | 04A0 0080h |
MCU_UART1 | 04A1 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIR_EN | DIR_POL | SET_DMA_TX_THRESHOLD | NONDEFAULT_FREQ | DISABLE_CIR_RX_DEMOD | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-5 | RESERVED | R | 0h |
Reserved |
4 | DIR_EN | R/W | 0h |
RS-485 External Transceiver Direction Enable |
3 | DIR_POL | R/W | 0h | RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0, RX: RTS=1. 1h = TX: RTS=1, RX: RTS=0 |
2 | SET_DMA_TX_THRESHOLD | R/W | 0h |
Enable to set different TXDMA threshold in UART_TX_DMA_THRESHOLD register. |
1 | NONDEFAULT_FREQ | R/W | 0h |
Used to enable the
NONDEFAULT fclk frequencies. |
0 | DISABLE_CIR_RX_DEMOD | R/W | 0h |
Used to enable CIR
RX demodulation. |
UART_TX_DMA_THRESHOLD is shown in Figure 12-327 and described in Table 12-612.
Return to Summary Table.
Use to manually set the TX DMA threshold level. UART_MDR3[2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register.
Instance | Physical Address |
---|---|
UART0 | 0280 0084h |
UART1 | 0281 0084h |
UART2 | 0282 0084h |
UART3 | 0283 0084h |
UART4 | 0284 0084h |
UART5 | 0285 0084h |
UART6 | 0286 0084h |
MCU_UART0 | 04A0 0084h |
MCU_UART1 | 04A1 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_DMA_THRESHOLD | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | RESERVED | R | 0h | |
5-0 | TX_DMA_THRESHOLD | R/W | 0h |
Used to manually set the TX DMA threshold level |
UART_MDR4 is shown in Figure 12-328 and described in Table 12-614.
Return to Summary Table.
Mode definition register 4
Instance | Physical Address |
---|---|
UART0 | 0280 0088h |
UART1 | 0281 0088h |
UART2 | 0282 0088h |
UART3 | 0283 0088h |
UART4 | 0284 0088h |
UART5 | 0285 0088h |
UART6 | 0286 0088h |
MCU_UART0 | 04A0 0088h |
MCU_UART1 | 04A1 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODE9 | FREQ_SEL_H | MODE | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | RESERVED | R | 0h | |
6 | MODE9 | R/W | 0h | 9-bit character length When '1', overrides character length setting in UART_LCR |
5-3 | FREQ_SEL_H | R/W | 0h |
Upper 3 bits of UART_FREQ_SEL register for higher division values, as required for example for FI/Di in ISO7816 mode |
2-0 | MODE | R/W | 0h |
New modes [when set, overrides UART_MDR1 modes] 0h = Disabled (no override) 1h = Reserved 2h = Synchronous mode with external clock 3h = Synchronous mode with generated clock 4h = ISO 7816 mode T=0 5h = ISO 7816 mode T=1 6h = Reserved 7h = Reserved |
UART_EFR2 is shown in Figure 12-329 and described in Table 12-616.
Return to Summary Table.
Enhanced Features Register 2
Instance | Physical Address |
---|---|
UART0 | 0280 008Ch |
UART1 | 0281 008Ch |
UART2 | 0282 008Ch |
UART3 | 0283 008Ch |
UART4 | 0284 008Ch |
UART5 | 0285 008Ch |
UART6 | 0286 008Ch |
MCU_UART0 | 04A0 008Ch |
MCU_UART1 | 04A1 008Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BROADCAST | TIMEOUT_BEHAVE | C8 | C4 | C2 | MULTIDROP | RHR_OVERRUN | ENDIAN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | BROADCAST | R/W | 0h |
Enables broadcast address matching in multi-drop address match mode |
6 | TIMEOUT_BEHAVE | R/W | 0h |
Specifies how timeout is measured 0h = Timeout after at least one character has been received 1h = Periodic timeout even when no character has been received |
5 | C8 | R/W | 0h |
Value for ISO 7816 C8 pin for software control |
4 | C4 | R/W | 0h |
Value for ISO 7816 C4 pin for software control |
3 | C2 | R/W | 0h |
Value for ISO 7816 reset pin [software controllable] |
2 | MULTIDROP | R/W | 0h |
Enables parity Multi-drop mode [overrides UART_LCR[5..3]] when '1' |
1 | RHR_OVERRUN | R/W | 0h |
UART_RHR Overrun behavior when buffer full 0h = Data in RHR is not overwritten (standard) 1h = Data in RHR is overwritten when buffer full (and FIFO disabled) |
0 | ENDIAN | R/W | 0h |
Endianness 0h = Little Endian (LSB First) 1h = Big Endian (MSB First) |
UART_ECR is shown in Figure 12-330 and described in Table 12-618.
Return to Summary Table.
Enhanced Control register
Instance | Physical Address |
---|---|
UART0 | 0280 0090h |
UART1 | 0281 0090h |
UART2 | 0282 0090h |
UART3 | 0283 0090h |
UART4 | 0284 0090h |
UART5 | 0285 0090h |
UART6 | 0286 0090h |
MCU_UART0 | 04A0 0090h |
MCU_UART1 | 04A1 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLEAR_TX_PE | TX_EN | RX_EN | TX_RST | RX_RST | A_MULTIDROP | |
R-0h | W-0h | R/W-1h | R/W-1h | W-0h | W-0h | W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-6 | RESERVED | R | 0h | |
5 | CLEAR_TX_PE | W | 0h |
Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only] |
4 | TX_EN | R/W | 1h |
Enables/Disables the transmitter 0h = DISABLED (Transmitter is shut down) 1h = ENABLED (Transmitter is working) |
3 | RX_EN | R/W | 1h |
Enables/Disables the receiver 0h = DISABLED (Receiver is shut down) 1h = ENABLED (Receiver is operating) |
2 | TX_RST | W | 0h |
Writing 1h = resets the transmitter |
1 | RX_RST | W | 0h |
Writing 1h = resets the receiver |
0 | A_MULTIDROP | W | 0h |
In multi-drop mode, when written with the value '1' causes the next byte written into UART_THR to be transmitted with the parity bit set, signaling an address |
UART_TIMEGUARD is shown in Figure 12-331 and described in Table 12-620.
Return to Summary Table.
Timeguard
Instance | Physical Address |
---|---|
UART0 | 0280 0094h |
UART1 | 0281 0094h |
UART2 | 0282 0094h |
UART3 | 0283 0094h |
UART4 | 0284 0094h |
UART5 | 0285 0094h |
UART6 | 0286 0094h |
MCU_UART0 | 04A0 0094h |
MCU_UART1 | 04A1 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEGUARD | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | TIMEGUARD | R/W | 0h |
Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices |
UART_TIMEOUTL is shown in Figure 12-332 and described in Table 12-622.
Return to Summary Table.
Timeout lower byte
Instance | Physical Address |
---|---|
UART0 | 0280 0098h |
UART1 | 0281 0098h |
UART2 | 0282 0098h |
UART3 | 0283 0098h |
UART4 | 0284 0098h |
UART5 | 0285 0098h |
UART6 | 0286 0098h |
MCU_UART0 | 04A0 0098h |
MCU_UART1 | 04A1 0098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT_L | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | TIMEOUT_L | R/W | 0h |
Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value] |
UART_TIMEOUTH is shown in Figure 12-333 and described in Table 12-624.
Return to Summary Table.
Timeout higher byte
Instance | Physical Address |
---|---|
UART0 | 0280 009Ch |
UART1 | 0281 009Ch |
UART2 | 0282 009Ch |
UART3 | 0283 009Ch |
UART4 | 0284 009Ch |
UART5 | 0285 009Ch |
UART6 | 0286 009Ch |
MCU_UART0 | 04A0 009Ch |
MCU_UART1 | 04A1 009Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT_H | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | TIMEOUT_H | R/W | 0h |
Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value] |
UART_SCCR is shown in Figure 12-334 and described in Table 12-626.
Return to Summary Table.
Smartcard (ISO7816) mode Control Register
Instance | Physical Address |
---|---|
UART0 | 0280 00A0h |
UART1 | 0281 00A0h |
UART2 | 0282 00A0h |
UART3 | 0283 00A0h |
UART4 | 0284 00A0h |
UART5 | 0285 00A0h |
UART6 | 0286 00A0h |
MCU_UART0 | 04A0 00A0h |
MCU_UART1 | 04A1 00A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSNACK | INACK | RESERVED | MAX_ITERATION | ||||
R/W-0h | R/W-0h | R-0h | R/W-7h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7 | DSNACK | R/W | 0h |
Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it |
6 | INACK | R/W | 0h |
Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it |
5-3 | RESERVED | R | 0h | |
2-0 | MAX_ITERATION | R/W | 7h |
Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared |
UART_ERHR is shown in Figure 12-335 and described in Table 12-628.
Return to Summary Table.
Extended Receive Holding Register
Instance | Physical Address |
---|---|
UART0 | 0280 00A4h |
UART1 | 0281 00A4h |
UART2 | 0282 00A4h |
UART3 | 0283 00A4h |
UART4 | 0284 00A4h |
UART5 | 0285 00A4h |
UART6 | 0286 00A4h |
MCU_UART0 | 04A0 00A4h |
MCU_UART1 | 04A1 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERHR | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | |
8-0 | ERHR | R | 0h |
Extended Receive Holding Register - allows accessing the full 9bit UART_RHR |
UART_ETHR is shown in Figure 12-336 and described in Table 12-630.
Return to Summary Table.
Extended Transmit Holding Register
Instance | Physical Address |
---|---|
UART0 | 0280 00A4h |
UART1 | 0281 00A4h |
UART2 | 0282 00A4h |
UART3 | 0283 00A4h |
UART4 | 0284 00A4h |
UART5 | 0285 00A4h |
UART6 | 0286 00A4h |
MCU_UART0 | 04A0 00A4h |
MCU_UART1 | 04A1 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ETHR | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | |
8-0 | ETHR | W | 0h |
Extended Transmit Holding Register - allows writing the full 9bit UART_RHR |
UART_MAR is shown in Figure 12-337 and described in Table 12-632.
Return to Summary Table.
Multidrop Address Register
Instance | Physical Address |
---|---|
UART0 | 0280 00A8h |
UART1 | 0281 00A8h |
UART2 | 0282 00A8h |
UART3 | 0283 00A8h |
UART4 | 0284 00A8h |
UART5 | 0285 00A8h |
UART6 | 0286 00A8h |
MCU_UART0 | 04A0 00A8h |
MCU_UART1 | 04A1 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDRESS | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | ADDRESS | R/W | 0h |
Multidrop match address value |
UART_MMR is shown in Figure 12-338 and described in Table 12-634.
Return to Summary Table.
Multidrop Mask Register
Instance | Physical Address |
---|---|
UART0 | 0280 00ACh |
UART1 | 0281 00ACh |
UART2 | 0282 00ACh |
UART3 | 0283 00ACh |
UART4 | 0284 00ACh |
UART5 | 0285 00ACh |
UART6 | 0286 00ACh |
MCU_UART0 | 04A0 00ACh |
MCU_UART1 | 04A1 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MASK | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | MASK | R/W | 0h |
Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching |
UART_MBR is shown in Figure 12-339 and described in Table 12-636.
Return to Summary Table.
Multidrop Broadcast Address Register
Instance | Physical Address |
---|---|
UART0 | 0280 00B0h |
UART1 | 0281 00B0h |
UART2 | 0282 00B0h |
UART3 | 0283 00B0h |
UART4 | 0284 00B0h |
UART5 | 0285 00B0h |
UART6 | 0286 00B0h |
MCU_UART0 | 04A0 00B0h |
MCU_UART1 | 04A1 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BROADCAST_ADDRESS | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | BROADCAST_ADDRESS | R/W | 0h |
Broadcast address for address matching |