SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | PSC0 Physical Address | MCU_PSC0 Physical Address |
---|---|---|---|---|---|
0h | 32 | PSC0_PID | PID register | 0040 0000h | 0400 0000h |
10h | 32 | PSC0_GBLCTL | Global Control Register | 0040 0010h | 0400 0010h |
14h | 32 | PSC0_GBLSTAT | Global Status Register | 0040 0014h | 0400 0014h |
18h | 32 | PSC0_INTEVAL | Interrupt Evaluation Register | 0040 0018h | 0400 0018h |
40h | 32 | PSC0_MERRPR | Module Error Pending Register | 0040 0040h | 0400 0040h |
50h | 32 | PSC0_MERRCR | Module Error Clear Register | 0040 0050h | 0400 0050h |
60h | 32 | PSC0_PERRPR | Power Error Pending Register | 0040 0060h | 0400 0060h |
68h | 32 | PSC0_PERRCR | Power Error Clear Register | 0040 0068h | 0400 0068h |
70h | 32 | PSC0_EPCPR | External Power Error Pending Register | 0040 0070h | 0400 0070h |
78h | 32 | PSC0_EPCCR | External Power Control Clear Register | 0040 0078h | 0400 0078h |
100h | 32 | PSC0_RAILSTAT | Power Rail Status Register | 0040 0100h | 0400 0100h |
104h | 32 | PSC0_RAILCTL | Power Rail Counter Control Register | 0040 0104h | 0400 0104h |
108h | 32 | PSC0_RAILSEL | Power Rail Counter Select Register | 0040 0108h | 0400 0108h |
120h | 32 | PSC0_PTCMD | Power Domain Transition Command Register | 0040 0120h | 0400 0120h |
128h | 32 | PSC0_PTSTAT | Power Domain Transition Status Register | 0040 0128h | 0400 0128h |
200h | 32 | PSC0_PDSTAT | Power Domain Status Register | 0040 0200h | 0400 0200h |
300h | 32 | PSC0_PDCTL | Power Domain Control Register | 0040 0300h | 0400 0300h |
400h | 32 | PSC0_PDCFG | Power Domain Configuration Register | 0040 0400h | 0400 0400h |
600h | 32 | PSC0_MDCFG | Module Configuration Register | 0040 0600h | 0400 0600h |
800h | 32 | PSC0_MDSTAT | Module Status Register | 0040 0800h | 0400 0800h |
A00h | 32 | PSC0_MDCTL | Module Control Register | 0040 0A00h | 0400 0A00h |
Short Description: PID register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0000h |
MCU_PSC0 | 0400 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R | R | R | |||||||||||||
1 | 0 | 10010000010 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R | R | R | R | ||||||||||||
0 | 10 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | PID register scheme |
29 - 28 | BU | R | 0h | Business Unit |
27 - 16 | FUNC | R | 482h | Module ID |
15 - 11 | RTL | R | 0h | RTL revision. Will vary depending on release |
10 - 8 | MAJOR | R | 2h | Major revision |
7 - 6 | CUSTOM | R | 0h | Custom |
5 - 0 | MINOR | R | 0h | Minor revision |
Short Description: Global Control Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0010h |
MCU_PSC0 | 0400 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IO_ANA_CTL | RESERVED | ||||||||||||||
R | NONE | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | IO_ANA_CTL | R | 0h | General purpose IO/Analog PowerDown control. Directly drives io_ana_pdctl_po[7:0] outputs. |
RESERVED | NONE | Reserved |
Short Description: Global Status Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0014h |
MCU_PSC0 | 0400 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EF_SMRFLEX | ||||||||||||||
NONE | R | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OVRIDE | ||||||||||||||
NONE | R | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
27 - 16 | EF_SMRFLEX | R | 0h | Smart reflex class0 bits |
RESERVED | NONE | Reserved | ||
0 | OVRIDE | R | 0h | PSC Override Status |
Short Description: Interrupt Evaluation Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0018h |
MCU_PSC0 | 0400 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | GOSET | EPCSET | ERRSET | RESERVED | |||||||||||
NONE | W | W | W | NONE | |||||||||||
0 | 0 | 0 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPCEV | ERREV | ALLEV | ||||||||||||
NONE | W | W | W | ||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
19 | GOSET | W | 0h | GOSTAT Interrupt Set |
18 | EPCSET | W | 0h | External Power Control Interrupt Set |
17 | ERRSET | W | 0h | Combined Interrupt Set |
RESERVED | NONE | Reserved | ||
2 | EPCEV | W | 0h | External Power Control Interrupt Set |
1 | ERREV | W | 0h | Re_evaluate Error Interrupt |
0 | ALLEV | W | 0h | Re_evaluate combined PSC interrupt |
Short Description: Module Error Pending Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0040h |
MCU_PSC0 | 0400 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
M | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
M | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | M | R | 0h | Records pending error conditions. Each bit n represents a module. |
Short Description: Module Error Clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0050h |
MCU_PSC0 | 0400 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
M | |||||||||||||||
W1TC | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
M | |||||||||||||||
W1TC | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | M | W1TC | 0h | Write of 1 clears the corresponding MERRPR bit. |
Short Description: Power Error Pending Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0060h |
MCU_PSC0 | 0400 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
P | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | P | R | 0h | Power Domain n Error Condition. Each bit n represents a power domain. |
Short Description: Power Error Clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0068h |
MCU_PSC0 | 0400 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
P | |||||||||||||||
W1TC | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | |||||||||||||||
W1TC | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | P | W1TC | 0h | Write of 1 clears the corresponding PERRPR bit. |
Short Description: External Power Error Pending Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0070h |
MCU_PSC0 | 0400 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EPC | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPC | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | EPC | R | 0h | External Power Control Intervention Request for Power Domain n |
Short Description: External Power Control Clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0078h |
MCU_PSC0 | 0400 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EPC | |||||||||||||||
W1TC | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPC | |||||||||||||||
W1TC | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | EPC | W1TC | 0h | Write of 1 clears the corresponding EPCPR bit |
Short Description: Power Rail Status Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0100h |
MCU_PSC0 | 0400 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAILNUM | RESERVED | |||||||||||||
NONE | R | NONE | |||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAILCNT | ||||||||||||||
NONE | R | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
28 - 24 | RAILNUM | R | 0h | Indicates Current Rail Requestor being processed by GPSC |
RESERVED | NONE | Reserved | ||
7 - 0 | RAILCNT | R | 0h | Indicates the current rail counter value |
Short Description: Power Rail Counter Control Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0104h |
MCU_PSC0 | 0400 0104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAILCTR1 | RAILCTR0 | ||||||||||||||
R/W | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | RAILCTR1 | R/W | 0h | Rail Counter Value 1 |
7 - 0 | RAILCTR0 | R/W | 0h | Rail Counter Value 0 |
Short Description: Power Rail Counter Select Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0108h |
MCU_PSC0 | 0400 0108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
P | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | P | R/W | 0h | Rail Counter Select for Power Domain |
Short Description: Power Domain Transition Command Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0120h |
MCU_PSC0 | 0400 0120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GO | |||||||||||||||
W1TS | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GO | |||||||||||||||
W1TS | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | GO | W1TS | 0h | Power Domain n GO Transition |
Short Description: Power Domain Transition Status Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0128h |
MCU_PSC0 | 0400 0128h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GOSTAT | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GOSTAT | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | GOSTAT | R | 0h | Power Domain n Transition Command Status |
Short Description: Power Domain Status Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0200h |
MCU_PSC0 | 0400 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EMUIHB | PWRBAD | PORDONE | PORZ | RESERVED | STATE | |||||||||
NONE | R | R | R | R | NONE | R | |||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
11 | EMUIHB | R | 0h | Emulation Alters Domain State |
10 | PWRBAD | R | 0h | Power Bad error |
9 | PORDONE | R | 0h | POR Done Input Status |
8 | PORZ | R | 0h | PORz output actual status |
RESERVED | NONE | Reserved | ||
4 - 0 | STATE | R | 0h | Current Power Domain State |
Short Description: Power Domain Control Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0300h |
MCU_PSC0 | 0400 0300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FORCE | RESERVED | PWRSW | ISO | RESERVED | WAKECNT | ||||||||||
R/W | NONE | R/W | R/W | NONE | R/W | ||||||||||
0 | 0 | 0 | 0 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PDMODE | RESERVED | EMUIHBIE | EPCGOOD | RESERVED | NEXT | |||||||||
NONE | R/W | NONE | R/W | R/W | NONE | R/W | |||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | FORCE | R/W | 0h | Force Bit |
RESERVED | NONE | Reserved | ||
29 | PWRSW | R/W | 0h | Power shorting Switch Control |
28 | ISO | R/W | 0h | Isolation Cell control |
RESERVED | NONE | Reserved | ||
23 - 16 | WAKECNT | R/W | 0h | RAM wake count delay value |
RESERVED | NONE | Reserved | ||
14 - 12 | PDMODE | R/W | 0h | Power Down mode |
RESERVED | NONE | Reserved | ||
9 | EMUIHBIE | R/W | 0h | Emulation alters domain state |
8 | EPCGOOD | R/W | 0h | External Power Control Power Good Indication |
RESERVED | NONE | Reserved | ||
0 | NEXT | R/W | 0h | User_Desired Next Power Domain State |
Short Description: Power Domain Configuration Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0400h |
MCU_PSC0 | 0400 0400h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ICEPICK | RESERVED | MEMSLPKWK | ALWAYSON | |||||||||||
NONE | R | NONE | R | R | |||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 | ICEPICK | R | 0h | Icepick support |
RESERVED | NONE | Reserved | ||
1 | MEMSLPKWK | R | 0h | Memory sleep-wake domain |
0 | ALWAYSON | R | 0h | Always on power domain |
Short Description: Module Configuration Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0600h |
MCU_PSC0 | 0400 0600h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PWRDOM | ||||||||||||||
NONE | R | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOONLY | RESETISO | NEXTLOCK | ASYNC | ICEPICK | PERMDIS | PLLHANDSHAKE | NUMSCRDISBALE | NUMCLKEN | NUMCLK | ||||||
R | R | R | R | R | R | R | R | R | R | ||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
20 - 16 | PWRDOM | R | 0h | Indicates which power domain this module belongs to |
15 | AUTOONLY | R | 0h | 0: This LPSC supports all modes, 1: This LPSC supports Enable, AutoSleep or AutoWake only |
14 | RESETISO | R | 0h | 0: This LPSC does not support Reset Isolation, 1: This LPSC supports Reset Isolation |
13 | NEXTLOCK | R | 0h | 0: MDCTL.NEXT field is writable, 1: MDCTL.NEXT field is locked |
12 | ASYNC | R | 0h | Async Lpsc |
11 | ICEPICK | R | 0h | IcePick support |
10 | PERMDIS | R | 0h | Permanently disable |
9 | PLLHANDSHAKE | R | 0h | RTL parameter PLL_HANDSHAKE |
8 - 6 | NUMSCRDISBALE | R | 0h | Number of PWR_SCR_DISABLE interfaces required on LPSC |
5 - 3 | NUMCLKEN | R | 0h | Number of PWR_CLK_EN interfaces required on LPSC |
2 - 0 | NUMCLK | R | 0h | Number of PWR_CLKSTOP interfaces required on LPSC |
Short Description: Module Status Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0800h |
MCU_PSC0 | 0400 0800h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EMUIHB | EMURST | |||||||||||||
NONE | R | R | |||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCKOUT | MRSTDONE | MRSTZ | LRSTDONE | LRSTZ | RESERVED | STATE | ||||||||
NONE | R | R | R | R | R | NONE | R | ||||||||
0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
17 | EMUIHB | R | 0h | Emulation Alters Module State. Inhibits Module Inactive or Force Module Active. |
16 | EMURST | R | 0h | Emulation Alters Reset |
RESERVED | NONE | Reserved | ||
12 | MCKOUT | R | 0h | Actual modclk output to module |
11 | MRSTDONE | R | 0h | Module reset initialization done status |
10 | MRSTZ | R | 0h | Module reset actual status |
9 | LRSTDONE | R | 0h | Module local reset initialization done status |
8 | LRSTZ | R | 0h | Module local reset actual status |
RESERVED | NONE | Reserved | ||
5 - 0 | STATE | R | 0h | These bits indicate the current module state |
Short Description: Module Control Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
PSC0 | 0040 0A00h |
MCU_PSC0 | 0400 0A00h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FORCE | RESERVED | ||||||||||||||
R/W | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETISO | BLKCHIP1RST | EMUIHBIE | EMURSTIE | LRSTZ | RESERVED | NEXT | ||||||||
NONE | R/W | R/W | R/W | R/W | R/W | NONE | R/W | ||||||||
0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | FORCE | R/W | 0h | Force Bit |
RESERVED | NONE | Reserved | ||
12 | RESETISO | R/W | 0h | Reset Isolation |
11 | BLKCHIP1RST | R/W | 0h | Block Chip_1_Reset |
10 | EMUIHBIE | R/W | 0h | Emulation Alters Module State. Inhibits Module Inactive or Force Module Active. |
9 | EMURSTIE | R/W | 0h | Emulation Alter Reset Interrupt Enable |
8 | LRSTZ | R/W | 0h | Module local reset control |
RESERVED | NONE | Reserved | ||
4 - 0 | NEXT | R/W | 0h | Module Next State |
Access Type | Code | Description |
---|---|---|
R | R | Read |
W | W | Write |
W1TC | W1TC | Undefined |
R/W | R/W | Read / Write |
W1TS | W1TS | Undefined |