SPRUIM2H User guide

Table 6-567 lists the memory-mapped registers for the PRU_ICSSG_CFG registers. All register offset addresses not listed in Table 6-567 should be considered as reserved locations and the register contents should not be modified.

Table 6-566 PRU_ICSSG_CFG Instances

Instance	Base Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6000h
PRU_ICSSG1_PR1_CFG_SLV	300A 6000h

Table 6-567 PRU_ICSSG_CFG Registers

Offset	Acronym	Register Name	PRU_ICSSG0_PR1_CFG_SLV Physical Address	PRU_ICSSG1_PR1_CFG_SLV Physical Address
0h	ICSSG_PID_REG	PID Register	3002 6000h	300A 6000h
4h	ICSSG_HWDIS_REG	HW Disable Register	3002 6004h	300A 6004h
8h	ICSSG_GPCFG0_REG	GP Configuration 0 Register	3002 6008h	300A 6008h
Ch	ICSSG_GPCFG1_REG	GP Configuration 1 Register	3002 600Ch	300A 600Ch
10h	ICSSG_CGR_REG	Clock Gating Register	3002 6010h	300A 6010h
14h	ICSSG_GPECFG0_REG	GP Enc Configuration 0 Register	3002 6014h	300A 6014h
18h	ICSSG_GPECFG1_REG	GP Enc Configuration 1 Register	3002 6018h	300A 6018h
1Ch	ICSSG_RSTISO_REG	Reset Isolation Register	3002 601Ch	300A 601Ch
2Ch	ICSSG_MII_RT_REG	MII_RT Event Enable Register	3002 602Ch	300A 602Ch
30h	ICSSG_IEPCLK_REG	IEP Configuration Register	3002 6030h	300A 6030h
34h	ICSSG_SPP_REG	Scratchpad Priority and Shift Register	3002 6034h	300A 6034h
3Ch	ICSSG_CORE_SYNC_REG	CoreSync Configuration Register	3002 603Ch	300A 603Ch
40h	ICSSG_SA_MX_REG	SA Mux Selection Register	3002 6040h	300A 6040h
44h	ICSSG_PRU0_SD_CFG_REG	SD Config Register	3002 6044h	300A 6044h
48h	ICSSG_PRU0_SD_CLK_SEL_REG0	PRU0 FD, ACC and Clock Selection Register 0	3002 6048h	300A 6048h
4Ch	ICSSG_PRU0_SD_SAMPLE_SIZE_REG0	PRU0 FD and Over Sample Size Register 0	3002 604Ch	300A 604Ch
50h	ICSSG_PRU0_SD_CLK_SEL_REG1	PRU0 FD, ACC and Clock Selection Register 1	3002 6050h	300A 6050h
54h	ICSSG_PRU0_SD_SAMPLE_SIZE_REG1	PRU0 FD and Over Sample Size Register 1	3002 6054h	300A 6054h
58h	ICSSG_PRU0_SD_CLK_SEL_REG2	PRU0 FD, ACC and Clock Selection Register 2	3002 6058h	300A 6058h
5Ch	ICSSG_PRU0_SD_SAMPLE_SIZE_REG2	PRU0 FD and Over Sample Size Register 2	3002 605Ch	300A 605Ch
60h	ICSSG_PRU0_SD_CLK_SEL_REG3	PRU0 FD, ACC and Clock Selection Register 3	3002 6060h	300A 6060h
64h	ICSSG_PRU0_SD_SAMPLE_SIZE_REG3	PRU0 FD and Over Sample Size Register 3	3002 6064h	300A 6064h
68h	ICSSG_PRU0_SD_CLK_SEL_REG4	PRU0 FD, ACC and Clock Selection Register 4	3002 6068h	300A 6068h
6Ch	ICSSG_PRU0_SD_SAMPLE_SIZE_REG4	PRU0 FD and Over Sample Size Register 4	3002 606Ch	300A 606Ch
70h	ICSSG_PRU0_SD_CLK_SEL_REG5	PRU0 FD, ACC and Clock Selection Register 5	3002 6070h	300A 6070h
74h	ICSSG_PRU0_SD_SAMPLE_SIZE_REG5	PRU0 FD and Over Sample Size Register 5	3002 6074h	300A 6074h
78h	ICSSG_PRU0_SD_CLK_SEL_REG6	PRU0 FD, ACC and Clock Selection Register 6	3002 6078h	300A 6078h
7Ch	ICSSG_PRU0_SD_SAMPLE_SIZE_REG6	PRU0 FD and Over Sample Size Register 6	3002 607Ch	300A 607Ch
80h	ICSSG_PRU0_SD_CLK_SEL_REG7	PRU0 FD, ACC and Clock Selection Register 7	3002 6080h	300A 6080h
84h	ICSSG_PRU0_SD_SAMPLE_SIZE_REG7	PRU0 FD and Over Sample Size Register 7	3002 6084h	300A 6084h
88h	ICSSG_PRU0_SD_CLK_SEL_REG8	PRU0 FD, ACC and Clock Selection Register 8	3002 6088h	300A 6088h
8Ch	ICSSG_PRU0_SD_SAMPLE_SIZE_REG8	PRU0 FD and Over Sample Size Register 8	3002 608Ch	300A 608Ch
90h	ICSSG_PRU1_SD_CFG_REG	SD Config Register	3002 6090h	300A 6090h
94h	ICSSG_PRU1_SD_CLK_SEL_REG0	PRU1 FD, ACC and Clock Selection Register 0	3002 6094h	300A 6094h
98h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG0	PRU1 FD and Over Sample Size Register 0	3002 6098h	300A 6098h
9Ch	ICSSG_PRU1_SD_CLK_SEL_REG1	PRU1 FD, ACC and Clock Selection Register 1	3002 609Ch	300A 609Ch
A0h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG1	PRU1 FD and Over Sample Size Register 1	3002 60A0h	300A 60A0h
A4h	ICSSG_PRU1_SD_CLK_SEL_REG2	PRU1 FD, ACC and Clock Selection Register 2	3002 60A4h	300A 60A4h
A8h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG2	PRU1 FD and Over Sample Size Register 2	3002 60A8h	300A 60A8h
ACh	ICSSG_PRU1_SD_CLK_SEL_REG3	PRU1 FD, ACC and Clock Selection Register 3	3002 60ACh	300A 60ACh
B0h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG3	PRU1 FD and Over Sample Size Register 3	3002 60B0h	300A 60B0h
B4h	ICSSG_PRU1_SD_CLK_SEL_REG4	PRU1 FD, ACC and Clock Selection Register 4	3002 60B4h	300A 60B4h
B8h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG4	PRU1 FD and Over Sample Size Register 4	3002 60B8h	300A 60B8h
BCh	ICSSG_PRU1_SD_CLK_SEL_REG5	PRU1 FD, ACC and Clock Selection Register 5	3002 60BCh	300A 60BCh
C0h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG5	PRU1 FD and Over Sample Size Register 5	3002 60C0h	300A 60C0h
C4h	ICSSG_PRU1_SD_CLK_SEL_REG6	PRU1 FD, ACC and Clock Selection Register 6	3002 60C4h	300A 60C4h
C8h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG6	PRU1 FD and Over Sample Size Register 6	3002 60C8h	300A 60C8h
CCh	ICSSG_PRU1_SD_CLK_SEL_REG7	PRU1 FD, ACC and Clock Selection Register 7	3002 60CCh	300A 60CCh
D0h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG7	PRU1 FD and Over Sample Size Register 7	3002 60D0h	300A 60D0h
D4h	ICSSG_PRU1_SD_CLK_SEL_REG8	PRU1 FD, ACC and Clock Selection Register 8	3002 60D4h	300A 60D4h
D8h	ICSSG_PRU1_SD_SAMPLE_SIZE_REG8	PRU1 FD and Over Sample Size Register 8	3002 60D8h	300A 60D8h
E0h	ICSSG_PRU0_ED_RX_CFG_REG	PRU0 ED Receive Global Configuration Register	3002 60E0h	300A 60E0h
E4h	ICSSG_PRU0_ED_TX_CFG_REG	PRU0 ED Transmit Global Configuration Register	3002 60E4h	300A 60E4h
E8h	ICSSG_PRU0_ED_CH0_CFG0_REG	PRU0 ED Channel 0 Configuration 0 Register	3002 60E8h	300A 60E8h
ECh	ICSSG_PRU0_ED_CH0_CFG1_REG	PRU0 ED Channel 0 Configuration 1 Register	3002 60ECh	300A 60ECh
F0h	ICSSG_PRU0_ED_CH1_CFG0_REG	PRU0 ED Channel 1 Configuration 0 Register	3002 60F0h	300A 60F0h
F4h	ICSSG_PRU0_ED_CH1_CFG1_REG	PRU0 ED Channel 1 Configuration 1 Register	3002 60F4h	300A 60F4h
F8h	ICSSG_PRU0_ED_CH2_CFG0_REG	PRU0 ED Channel 2 Configuration 0 Register	3002 60F8h	300A 60F8h
FCh	ICSSG_PRU0_ED_CH2_CFG1_REG	PRU0 ED Channel 2 Configuration 1 Register	3002 60FCh	300A 60FCh
100h	ICSSG_PRU1_ED_RX_CFG_REG	PRU1 ED Receive Global Configuration Register	3002 6100h	300A 6100h
104h	ICSSG_PRU1_ED_TX_CFG_REG	PRU1 ED Transmit Global Configuration Register	3002 6104h	300A 6104h
108h	ICSSG_PRU1_ED_CH0_CFG0_REG	PRU1 ED Channel 0 Configuration 0 Register	3002 6108h	300A 6108h
10Ch	ICSSG_PRU1_ED_CH0_CFG1_REG	PRU1 ED Channel 0 Configuration 1 Register	3002 610Ch	300A 610Ch
110h	ICSSG_PRU1_ED_CH1_CFG0_REG	PRU1 ED Channel 1 Configuration 0 Register	3002 6110h	300A 6110h
114h	ICSSG_PRU1_ED_CH1_CFG1_REG	PRU1 ED Channel 1 Configuration 1 Register	3002 6114h	300A 6114h
118h	ICSSG_PRU1_ED_CH2_CFG0_REG	PRU1 ED Channel 2 Configuration 0 Register	3002 6118h	300A 6118h
11Ch	ICSSG_PRU1_ED_CH2_CFG1_REG	PRU1 ED Channel 2 Configuration 1 Register	3002 611Ch	300A 611Ch
124h	ICSSG_RTU0_POKE_EN0_REG	RTU0 Poke Enable 0 Register	3002 6124h	300A 6124h
12Ch	ICSSG_RTU1_POKE_EN0_REG	RTU1 Poke Enable 0 Register	3002 612Ch	300A 612Ch
130h	ICSSG_PWM0	PWM0 Trip Configuration Register	3002 6130h	300A 6130h
134h	ICSSG_PWM1	PWM1 Trip Configuration Register	3002 6134h	300A 6134h
138h	ICSSG_PWM2	PWM2 Trip Configuration Register	3002 6138h	300A 6138h
13Ch	ICSSG_PWM3	PWM3 Trip Configuration Register	3002 613Ch	300A 613Ch
140h	ICSSG_PWM0_0	PWM0 State Configuration 0 Register	3002 6140h	300A 6140h
144h	ICSSG_PWM0_1	PWM0 State Configuration 1 Register	3002 6144h	300A 6144h
148h	ICSSG_PWM0_2	PWM0 State Configuration 2 Register	3002 6148h	300A 6148h
14Ch	ICSSG_PWM1_0	PWM1 State Configuration 0 Register	3002 614Ch	300A 614Ch
150h	ICSSG_PWM1_1	PWM1 State Configuration 1 Register	3002 6150h	300A 6150h
154h	ICSSG_PWM1_2	PWM1 State Configuration 2 Register	3002 6154h	300A 6154h
158h	ICSSG_PWM2_0	PWM2 State Configuration 0 Register	3002 6158h	300A 6158h
15Ch	ICSSG_PWM2_1	PWM2 State Configuration 1 Register	3002 615Ch	300A 615Ch
160h	ICSSG_PWM2_2	PWM2 State Configuration 2 Register	3002 6160h	300A 6160h
164h	ICSSG_PWM3_0	PWM3 State Configuration 0 Register	3002 6164h	300A 6164h
168h	ICSSG_PWM3_1	PWM3 State Configuration 1 Register	3002 6168h	300A 6168h
16Ch	ICSSG_PWM3_2	PWM3 State Configuration 2 Register	3002 616Ch	300A 616Ch
170h	ICSSG_SPIN_LOCK0	Spin Lock 0 Register	3002 6170h	300A 6170h
174h	ICSSG_SPIN_LOCK1	Spin Lock 1 Register	3002 6174h	300A 6174h
178h	ICSSG_PA_STAT_PDSP_CFG0	PA STATS PDSP0 Vector 0 Register	3002 6178h	300A 6178h
17Ch	ICSSG_PA_STAT_PDSP_STAT0	PA STATS PDSP0 Status 0 Register	3002 617Ch	300A 617Ch
180h	ICSSG_PA_STAT_PDSP_CFG1	PA STATS PDSP0 Vector 1 Register	3002 6180h	300A 6180h
184h	ICSSG_PA_STAT_PDSP_STAT1	PA STATS PDSP0 Status 1 Register	3002 6184h	300A 6184h
188h	ICSSG_PA_STAT_PDSP_CFG2	PA STATS PDSP0 Vector 2 Register	3002 6188h	300A 6188h
18Ch	ICSSG_PA_STAT_PDSP_STAT2	PA STATS PDSP0 Status 2 Register	3002 618Ch	300A 618Ch
190h	ICSSG_PA_STAT_PDSP_CFG3	PA STATS PDSP0 Vector 3 Register	3002 6190h	300A 6190h
194h	ICSSG_PA_STAT_PDSP_STAT3	PA STATS PDSP0 Status 3 Register	3002 6194h	300A 6194h

4.14.5.1 ICSSG_PID_REG Register (Offset = 0h) [reset = Xh]

ICSSG_PID_REG is shown in Figure 6-296 and described in Table 6-569.

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PID Register.

Table 6-568 ICSSG_PID_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6000h
PRU_ICSSG1_PR1_CFG_SLV	300A 6000h

Figure 6-296 ICSSG_PID_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODID
6B00h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REVRTL					REVMAJ			CUSTOM		REVMIN
R-X					R-1h			R-0h		R-X

LEGEND: R = Read Only; -n = value after reset

Table 6-569 ICSSG_PID_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MODID	R	6B00h	Module ID field. ICSS_G.
15-11	REVRTL	R	0h	RTL revision. 190H in this device.
10-8	REVMAJ	R	1h	Major
7-6	CUSTOM	R	0h	Custom
5-0	REVMIN	R	3h	Minor. 03H in this device.

4.14.5.2 ICSSG_HWDIS_REG Register (Offset = 4h) [reset = X]

ICSSG_HWDIS_REG is shown in Figure 6-297 and described in Table 6-571.

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HW Disable Register

Table 6-570 ICSSG_HWDIS_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6004h
PRU_ICSSG1_PR1_CFG_SLV	300A 6004h

Figure 6-297 ICSSG_HWDIS_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								HWDIS
R-X																								R-X

LEGEND: R = Read Only; -n = value after reset

Table 6-571 ICSSG_HWDIS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	X
7-0	HWDIS	R	X	Read the state of the efuse bits which drive pr1_hw_disable[7:0]

4.14.5.3 ICSSG_GPCFG0_REG Register (Offset = 8h) [reset = X]

ICSSG_GPCFG0_REG is shown in Figure 6-298 and described in Table 6-573.

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GP Configuration 0 Register

Table 6-572 ICSSG_GPCFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6008h
PRU_ICSSG1_PR1_CFG_SLV	300A 6008h

Figure 6-298 ICSSG_GPCFG0_REG Register

31	30	29	28	27	26	25	24
RESERVED		PR1_PRU0_GP_MUX_SEL				PRU0_GPO_SH1_SEL	PRU0_GPO_DIV1
R/W-X		R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU0_GPO_DIV1				PRU0_GPO_DIV0
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
PRU0_GPO_DIV0	PRU0_GPO_MODE	PRU0_GPI_SB	PRU0_GPI_DIV1
R/W-0h	R/W-0h	R/W1C-0h	R/W-0h

7	6	5	4	3	2	1	0
PRU0_GPI_DIV0					PRU0_GPI_CLK_MODE	PRU0_GPI_MODE
R/W-0h					R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to clear Bit; -n = value after reset

Table 6-573 ICSSG_GPCFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-26	PR1_PRU0_GP_MUX_SEL	R/W	0h	Controls the icss_wrap mux sel 0h = GP selected 1h = EnDAT mode 2h = MII mode 3h = SD mode
25	PRU0_GPO_SH1_SEL	R	0h	This defines which shadow register is currently getting used for GPO shifting. 0h = gpo_sh0 is selected 1h = gpo_sh1 is selected
24-20	PRU0_GPO_DIV1	R/W	0h	Divisor value , divide by PRU0_GPO_DIV1 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
19-15	PRU0_GPO_DIV0	R/W	0h	Divisor value , divide by PRU0_GPO_DIV0 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
14	PRU0_GPO_MODE	R/W	0h	0h = Parallel output mode 1h = Serial output mode, pru<n>_r30[31] enables shift pru<n>r30[0] is shift data out pru<n>r30[1] is shift clock
13	PRU0_GPI_SB	R/W1C	0h	PRU0_GPI_SB set when first capture on 1 on r31_status[0] r31_status[29] == PRU0_GPI_SB Read 1 Start Bit event occurred Read 0 Start Bit event has not occurred Write 1 Will clear PRU0_GPI_SB, 28 bit shift register, and shift counter Write 0 No Effect
12-8	PRU0_GPI_DIV1	R/W	0h	Divisor value , divide by PRU0_GPI_DIV1 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
7-3	PRU0_GPI_DIV0	R/W	0h	Divisor value , divide by PRU0_GPI_DIV0 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
2	PRU0_GPI_CLK_MODE	R/W	0h	Parallel 16-bit capture mode clock edge 0h = Use the positive edge of pru<n>_r31_status[16] 1h = Use the negative edge of pru<n>_r31_status[16]
1-0	PRU0_GPI_MODE	R/W	0h	0h = Direct connect of pru<n>_r31_status[29:0] 1h = Parallel 16-bit capture mode. pru<n>_r31_status [15:0] is captured using pru<n>_r31_status [16] 2h = 29-bit shift. pru<n>_r31_status[0] -> r31_status[0] -> r31_status[1] -> r_status[28] -> bit bucket 3h = mii_rt mode. Selects mii_rt pru0 bus

4.14.5.4 ICSSG_GPCFG1_REG Register (Offset = Ch) [reset = X]

ICSSG_GPCFG1_REG is shown in Figure 6-299 and described in Table 6-575.

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GP Configuration 1 Register

Table 6-574 ICSSG_GPCFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 600Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 600Ch

Figure 6-299 ICSSG_GPCFG1_REG Register

31	30	29	28	27	26	25	24
RESERVED		PR1_PRU1_GP_MUX_SEL				PRU1_GPO_SH1_SEL	PRU1_GPO_DIV1
R/W-X		R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU1_GPO_DIV1				PRU1_GPO_DIV0
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
PRU1_GPO_DIV0	PRU1_GPO_MODE	PRU1_GPI_SB	PRU1_GPI_DIV1
R/W-0h	R/W-0h	R/W1C-0h	R/W-0h

7	6	5	4	3	2	1	0
PRU1_GPI_DIV0					PRU1_GPI_CLK_MODE	PRU1_GPI_MODE
R/W-0h					R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to clear Bit; -n = value after reset

Table 6-575 ICSSG_GPCFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-26	PR1_PRU1_GP_MUX_SEL	R/W	0h	Controls the icss_wrap mux sel 0h = GP selected 1h = EnDAT mode 2h = MII mode 3h = SD mode
25	PRU1_GPO_SH1_SEL	R	0h	This defines which shadow register is currently getting used for GPO shifting. 0h = gpo_sh0 is selected 1h = gpo_sh1 is selected
24-20	PRU1_GPO_DIV1	R/W	0h	Divisor value , divide by PRU1_GPO_DIV1 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
19-15	PRU1_GPO_DIV0	R/W	0h	Divisor value , divide by PRU1_GPO_DIV0 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
14	PRU1_GPO_MODE	R/W	0h	0hh = Parallel output mode 0x1h = Serial output mode, pru<n>_r30[31] enables shift pru<n>r30[0] is shift data out pru<n>r30[1] is shift clock
13	PRU1_GPI_SB	R/W1C	0h	PRU1_GPI_SB set when first capture on 1 on r31_status[0] r31_status[29] == PRU1_GPI_SB Read 1 Start Bit event occurred Read 0 Start Bit event has not occurred Write 1 Will clear PRU1_GPI_SB, 28 bit shift register, and shift counter Write 0 No Effect
12-8	PRU1_GPI_DIV1	R/W	0h	Divisor value , divide by PRU1_GPI_DIV1 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
7-3	PRU1_GPI_DIV0	R/W	0h	Divisor value , divide by PRU1_GPI_DIV0 + 1 0h = div 1.0 1h = div 1.5 2h = div 2.0 .. 1Eh = div 16.0 1Fh = reserved
2	PRU1_GPI_CLK_MODE	R/W	0h	Parallel 16-bit capture mode clock edge 0h = Use the positive edge of pru<n>_r31_status[16] 0x1h = Use the negative edge of pru<n>_r31_status[16]
1-0	PRU1_GPI_MODE	R/W	0h	0h = Direct connect of pru<n>_r31_status[29:0] 1h = Parallel 16-bit capture mode. pru<n>_r31_status [15:0] is captured using pru<n>_r31_status [16] 2h = 29-bit shift. pru<n>_r31_status[0] -> r31_status[0]->r31_status[1]..-> r_status[28] -> bit bucket 3h = mii_rt mode. Selects mii_rt pru1 bus

4.14.5.5 ICSSG_CGR_REG Register (Offset = 10h) [reset = X]

ICSSG_CGR_REG is shown in Figure 6-300 and described in Table 6-577.

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Clock Gating Register

Table 6-576 ICSSG_CGR_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6010h
PRU_ICSSG1_PR1_CFG_SLV	300A 6010h

Figure 6-300 ICSSG_CGR_REG Register

31	30	29	28	27	26	25	24
ICSS_STOP_ACK	ICSS_STOP_REQ	ICSS_PWR_IDLE	RESERVED
R/W-1h	R-0h	R/W-1h	R/W-X

23	22	21	20	19	18	17	16
RESERVED		BOTTTOM_HALF_CLK_GATE_EN	TOP_HALF_CLK_GATE_EN	AUTO_SLICE1_CLK_GATE_EN	AUTO_SLICE0_CLK_GATE_EN	IEP_CLK_EN	IEP_CLK_STOP_ACK
R/W-X		R/W-1h	R/W-1h	R/W-0h	R/W-0h	R/W-1h	R-0h

15	14	13	12	11	10	9	8
IEP_CLK_STOP_REQ	ECAP_CLK_EN	ECAP_CLK_STOP_ACK	ECAP_CLK_STOP_REQ	UART_CLK_EN	UART_CLK_STOP_ACK	UART_CLK_STOP_REQ	INTC_CLK_EN
R/W-0h	R/W-1h	R-0h	R/W-0h	R/W-1h	R-0h	R/W-0h	R/W-1h

7	6	5	4	3	2	1	0
INTC_CLK_STOP_ACK	INTC_CLK_STOP_REQ	RESERVED
R-0h	R/W-0h	R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-577 ICSSG_CGR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ICSS_STOP_ACK	R/W	1h	ICSS 0h = Not Ready to Gate Clock 1h = Ready to Gate Clock
30	ICSS_STOP_REQ	R	0h	ICSS 0h = No Gate Clock Request 1h = Gate Clock Request
29	ICSS_PWR_IDLE	R/W	1h	ICSS 0h = Not Idle 1h = Idle
28-22	RESERVED	R/W	X
21	BOTTTOM_HALF_CLK_GATE_EN	R/W	1h	Bottom Clock Gate for slice 0 and 1 0 = Disable Clock 1 = Enable Clock
20	TOP_HALF_CLK_GATE_EN	R/W	1h	Top Clock Gate for slice 0 and 1 0 = Disable Clock 1 = Enable Clock
19	AUTO_SLICE1_CLK_GATE_EN	R/W	0h	Auto Clock Gate for slice 1 Ethernet 0 = Disable Clock 1 = Enable Auto Clock
18	AUTO_SLICE0_CLK_GATE_EN	R/W	0h	Auto Clock Gate for slice 0 Ethernet 0 = Disable Clock 1 = Enable Clock
17	IEP_CLK_EN	R/W	1h	IEP 0h = Disable Clock 1h = Enable Clock
16	IEP_CLK_STOP_ACK	R	0h	IEP 0h = Not Ready to Gate Clock 1h = Ready to Gate Clock
15	IEP_CLK_STOP_REQ	R/W	0h	IEP 0h = do not request to stop clock 1h = request to stop clock
14	ECAP_CLK_EN	R/W	1h	ECAP 0h = Disable Clock 1h = Enable Clock
13	ECAP_CLK_STOP_ACK	R	0h	ECAP 0h = Not Ready to Gate Clock 1h = Ready to Gate Clock
12	ECAP_CLK_STOP_REQ	R/W	0h	ECAP 0h = do not request to stop clock 1h = request to stop clock
11	UART_CLK_EN	R/W	1h	UART 0h = Disable Clock 1h = Enable Clock
10	UART_CLK_STOP_ACK	R	0h	UART 0h = Not Ready to Gate Clock 1h = Ready to Gate Clock
9	UART_CLK_STOP_REQ	R/W	0h	UART 0h = do not request to stop clock 1h = request to stop clock
8	INTC_CLK_EN	R/W	1h	INTC 0h = Disable Clock 1h = Enable Clock
7	INTC_CLK_STOP_ACK	R	0h	INTC 0h = Not Ready to Gate Clock 1h = Ready to Gate Clock
6	INTC_CLK_STOP_REQ	R/W	0h	INTC 0h = do not request to stop clock 1h = request to stop clock
5-0	RESERVED	R/W	X

4.14.5.6 ICSSG_GPECFG0_REG Register (Offset = 14h) [reset = X]

ICSSG_GPECFG0_REG is shown in Figure 6-301 and described in Table 6-579.

Return to Summary Table.

GP Enc Configuration 0 Register

Table 6-578 ICSSG_GPECFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6014h
PRU_ICSSG1_PR1_CFG_SLV	300A 6014h

Figure 6-301 ICSSG_GPECFG0_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED						PRU0_GPO_SHIFT_CLK_DONE	PRU0_GPO_SHIFT_CLK_HIGH
R/W-X						R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
PRU0_GPO_SHIFT_CNT
R/W-0h

7	6	5	4	3	2	1	0
RESERVED	PRU0_GPO_SHIFT_GP_EN	PRU0_GPO_SHIFT_CLK_FREE	PRU0_GPO_SHIFT_SWAP	RESERVED		PRU0_GPI_SHIFT_EN	PRU0_GPI_SB_P
R/W-X	R/W-0h	R/W-1h	R/W-0h	R/W-X		R/W-1h	R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-579 ICSSG_GPECFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17	PRU0_GPO_SHIFT_CLK_DONE	R/W	0h	Shift Clock Done is active when PRU0_GPO_SHIFT_CNT is none zero 0h = Shift Bit Count has not expired 1h = Set when Shift Bit Count has expired Write 1 to clear. This is only valid when PRU0/1_GPO_SHIFT_CLK_FREE is not set
16	PRU0_GPO_SHIFT_CLK_HIGH	R/W	0h	Shift Clock Stop High 0h = Stop Low, if Stop is enabled 1h = Stop High,if Stop is enabled This is only active when PRU0/1_GPO_SHIFT_CLK_FREE is not set Also, you must define PRU0/1_GPO_SHIFT_CNT Note: Software can only update once during initial configuration
15-8	PRU0_GPO_SHIFT_CNT	R/W	0h	Shift Bit Count 0h – 0x3h = Reserved PRU0_GPO_SHIFT_CNT determine how many bits to shift out. After the count is reached it will stop shifting , the last bit will remain persistent. 0x4h = shift 4 bits 0x5h = shift 5 bits 0xff = shift 255 bits This is only active when PRU0/1_GPO_SHIFT_CLK_FREE is not set Note: first new shift data is before the first clock edge. Due to this fact, the number of shift_clk is one minus PRU0/1_GPO_SHIFT_CNT
7	RESERVED	R/W	X
6	PRU0_GPO_SHIFT_GP_EN	R/W	0h	Enable pru<n>r30[15:2] control during shift out mode 0h = direction connection pru<n>r30[15:2] is controlled by r30[15:2] 1h = shadow connection pru<n>r30[15:2] is controlled by r30_shadow[15:2] Note: r30_shadow[15:2] is updated by r30[15:2] when r30[28] is high
5	PRU0_GPO_SHIFT_CLK_FREE	R/W	1h	Free Running Clock Mode This controls the behavior of the Shift Clock Out 0h = Shift Clock Out only active when bits are shifted out Default state of Shift Clock Out is low before and after shift (Shift is enabled only when shift_enable is TRUE and PRU0_GPO_SHIFT_CNT has not expired 1h = Shift Clock Out Free running The clock will start and remain active independent of shifting out new data When shift_enable is de-asserted and shift data out is completed, data out will go low
4	PRU0_GPO_SHIFT_SWAP	R/W	0h	0h = No Swap The shadow copy gets loaded with R30[15:0] 1h = Swap The shadow copy gets loaded with R30[0:15]
3-2	RESERVED	R/W	X
1	PRU0_GPI_SHIFT_EN	R/W	1h	GPI Shift In Enable 0h = disable This will freeze the current shift in process This will also disable the looking for a SB if SB event has not occurred 1h = enable
0	PRU0_GPI_SB_P	R/W	1h	GPI Shift In Start Bit Polarity 0h = Active Low SB is set on the first “0” seen 1h = Active High SB is set on the first “1” seen

4.14.5.7 ICSSG_GPECFG1_REG Register (Offset = 18h) [reset = X]

ICSSG_GPECFG1_REG is shown in Figure 6-302 and described in Table 6-581.

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GP Enc Configuration 1 Register

Table 6-580 ICSSG_GPECFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6018h
PRU_ICSSG1_PR1_CFG_SLV	300A 6018h

Figure 6-302 ICSSG_GPECFG1_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED						PRU1_GPO_SHIFT_CLK_DONE	PRU1_GPO_SHIFT_CLK_HIGH
R/W-X						R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
PRU1_GPO_SHIFT_CNT
R/W-0h

7	6	5	4	3	2	1	0
RESERVED	PRU1_GPO_SHIFT_GP_EN	PRU1_GPO_SHIFT_CLK_FREE	PRU1_GPO_SHIFT_SWAP	RESERVED		PRU1_GPI_SHIFT_EN	PRU1_GPI_SB_P
R/W-X	R/W-0h	R/W-1h	R/W-0h	R/W-X		R/W-1h	R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-581 ICSSG_GPECFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17	PRU1_GPO_SHIFT_CLK_DONE	R/W	0h	Shift Clock Done is active when PRU1_GPO_SHIFT_CNT is none zero 0h = Shift Bit Count has not expired 1h = Set when Shift Bit Count has expired Write 1 to clear This is only valid when PRU0/1_GPO_SHIFT_CLK_FREE is not set
16	PRU1_GPO_SHIFT_CLK_HIGH	R/W	0h	Shift Clock Stop High 0h = Stop Low, if Stop is enabled 1h = Stop High,if Stop is enabled This is only valid when PRU0/1_GPO_SHIFT_CLK_FREE is not set Also, you must define PRU0/1_GPO_SHIFT_CNT Note: Software can only update once during intial configuration
15-8	PRU1_GPO_SHIFT_CNT	R/W	0h	Shift Bit Count 0h – 3h = Reserved PRU1_GPO_SHIFT_CNT determine how many bits to shift out. After the count is reached it will stop shifting , the last bit will remain presistant. 4h = shift 4 bits 5h = shift 5 bits ffh = shift 255 bits This is only active when PRU0/1_GPO_SHIFT_CLK_FREE is not set Note: first new shift data is before the first clock edge Do to this fact, the number of shift_clk is one minus PRU0/1_GPO_SHIFT_CNT
7	RESERVED	R/W	X
6	PRU1_GPO_SHIFT_GP_EN	R/W	0h	Enable pru<n>r30[15:2] control during shift out mode 0h = direction connection pru<n>r30[15:2] is controlled by r30[15:2] 1h = shadow connection pru<n>r30[15:2] is controlled by r30_shadow[15:2] Note: r30_shadow[15:2] is updated by r30[15:2] when r30[28] is high
5	PRU1_GPO_SHIFT_CLK_FREE	R/W	1h	Free Running Clock Mode This controls the behavior of the Shift Clock Out 0h = Shift Clock Out only active when bits are shifted out Default state of Shift Clock Out is low before and after shift 1h = Shift Clock Out Free running The clock will start and remain active independent of shifting out new data
4	PRU1_GPO_SHIFT_SWAP	R/W	0h	0h = No Swap The shadow copy gets loaded with R30[15:0] 1h = Swap The shadow copy gets loaded with R30[0:15]
3-2	RESERVED	R/W	X
1	PRU1_GPI_SHIFT_EN	R/W	1h	GPI Shift In Enable 0h = disable This will freeze the current shift in process This will also disable the looking for a SB if SB event has not occurred 1h = enable
0	PRU1_GPI_SB_P	R/W	1h	GPI Shift In Start Bit Polarity 0h = Active Low SB is set on the first “0” seen 1h = Active High SB is set on the first “1” seen

4.14.5.8 ICSSG_RSTISO_REG Register (Offset = 1Ch) [reset = X]

ICSSG_RSTISO_REG is shown in Figure 6-303 and described in Table 6-583.

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Reset Isolation Register

Table 6-582 ICSSG_RSTISO_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 601Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 601Ch

Figure 6-303 ICSSG_RSTISO_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED					RESET_EDGE	RESET_ISO_ACK	RESET_ISO_REQ
R/W-X					W-0h	W-0h	R/W1C-1h

LEGEND: R/W = Read/Write; W = Write Only; R/W1C = Read/Write 1 to Clear-n = value after reset

Table 6-583 ICSSG_RSTISO_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2	RESET_EDGE	W	0h	Reset Edge Assertion Write 1 will reset ALL xfr2vbux_rx/tx, xfr2psi, scr_ext_cbass, and icss_g_core_ksdma_psil_endpt widgets
1	RESET_ISO_ACK	W	0h	Reset ISO Ack Write 1 will cause to acknowledge the Reset ISO Request
0	RESET_ISO_REQ	R/W1C	0h	Reset ISO Request Read 0 = No Active Requested Read 1 = Active Requested Write 1 to clear This bit gets set and held when pr1_rst_reset_iso_req input is asserted. Note, this will also cause system_event[3] to assert to INTC

4.14.5.9 ICSSG_MII_RT_REG Register (Offset = 2Ch) [reset = X]

ICSSG_MII_RT_REG is shown in Figure 6-304 and described in Table 6-585.

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MII_RT Event Enable Register

Table 6-584 ICSSG_MII_RT_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 602Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 602Ch

Figure 6-304 ICSSG_MII_RT_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							MII_RT_EVENT_EN
R/W-X							R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-585 ICSSG_MII_RT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	MII_RT_EVENT_EN	R/W	1h	Enables the MII_RT Events to the INTC 0h = disabled Use external events 1h = enabled Use MII_RT events

4.14.5.10 ICSSG_IEPCLK_REG Register (Offset = 30h) [reset = X]

ICSSG_IEPCLK_REG is shown in Figure 6-305 and described in Table 6-587.

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IEP Configuration Register

Table 6-586 ICSSG_IEPCLK_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6030h
PRU_ICSSG1_PR1_CFG_SLV	300A 6030h

Figure 6-305 ICSSG_IEPCLK_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						IEP1_SLV_EN	IEP_OCP_CLK_EN
R/W-X						R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-587 ICSSG_IEPCLK_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1	IEP1_SLV_EN	R/W	0h	IEP1 Controller Counter Target enable 0h = disabled 1h = enabled When Enabled IEP1 counter[63:0] is from IEP0 during 64-bit mode IEP1 counter[31:0] is from IEP0 during 32-bit mode
0	IEP_OCP_CLK_EN	R/W	0h	Defines the source of the IEP CLK 0h = iep_clk is the source Async Mode 1h = ICSSGn_CORE_CLK is the source Sync Mode When this is selected the async IEP bridge is bypassed No transaction active when this bit get SET It can only get CLR by a HW reset Note: This means all PRU-ICSSG IOs which use internal IEP clock can use ether internal core clock or external IEP clock.

4.14.5.11 ICSSG_SPP_REG Register (Offset = 34h) [reset = X]

ICSSG_SPP_REG is shown in Figure 6-306 and described in Table 6-589.

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Scratchpad Priority and Shift Register

Table 6-588 ICSSG_SPP_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6034h
PRU_ICSSG1_PR1_CFG_SLV	300A 6034h

Figure 6-306 ICSSG_SPP_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED				RTU_XFR_SHIFT_EN	XFR_BYTE_SHIFT_EN	XFR_SHIFT_EN	PRU1_PAD_HP_EN
R/W-X				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-589 ICSSG_SPP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R/W	X
3	RTU_XFR_SHIFT_EN	R/W	0h	Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations. 0h = disabled 1h = enabled When enabled, R0[4:0] (internal to RTU) defines the number of 32-bits the XIN and XOUT operation to the scratch pad bank. R0[4:0] = 2 XIN/XOUT of R4 will read/write bank<n>.R6 Wrap is supported R0[4:0] = 4 XIN/XOUT of R18:29 will read/write bank<n>.R22:R3
2	XFR_BYTE_SHIFT_EN	R/W	0h	Shift enable using R0[6:0] to define the number of 8-bit offset for XIN and XOUT operations. 0h = disabled 1h = enabled When enabled, R0[6:0] (internal to PRU/RTU) defines the number of 8-bits the XIN and XOUT operation to the scratch pad bank.
1	XFR_SHIFT_EN	R/W	0h	Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations. 0h = disabled 1h = enabled When enabled, R0[4:0] (internal to PRU) defines the number of 32-bits the XIN and XOUT operation to the scratch pad bank. R0[4:0] = 2 XIN/XOUT of R4 will read/write bank<n>.R6 Wrap is supported R0[4:0] = 4 XIN/XOUT of R18:29 will read/write bank<n>.R22:R3
0	PRU1_PAD_HP_EN	R/W	0h	Reserved

4.14.5.12 ICSSG_CORE_SYNC_REG Register (Offset = 3Ch) [reset = X]

ICSSG_CORE_SYNC_REG is shown in Figure 6-307 and described in Table 6-591.

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CoreSync Configuration Register.

Table 6-590 ICSSG_CORE_SYNC_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 603Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 603Ch

Figure 6-307 ICSSG_CORE_SYNC_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							CORE_VBUSP_SYNC_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-591 ICSSG_CORE_SYNC_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	CORE_VBUSP_SYNC_EN	R/W	0h	Defines the source of the internal CORE CLK 0h = ICSSGn_CORE_CLK is the source Async Mode 1h = ICSSGn_ICLK is the source (Sync Mode) When this is selected the async vbusp controller bridge is bypassed No transaction active when this bit get SET It can only get CLR by a HW reset The user should enable to get the lowest latency and high speed, since ICSSGn_ICLK should be at 250 MHz Note: This means all PRU_ICSSG IOs which use internal core clock (CORE_CLK) can use ether external core clock or external ICSSGn_ICLK.

4.14.5.13 ICSSG_SA_MX_REG Register (Offset = 40h) [reset = X]

ICSSG_SA_MX_REG is shown in Figure 6-308 and described in Table 6-593.

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SA Mux Selection Register.

Table 6-592 ICSSG_SA_MX_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6040h
PRU_ICSSG1_PR1_CFG_SLV	300A 6040h

Figure 6-308 ICSSG_SA_MX_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							PWM_EFC_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED				PWM3_REMAP_EN		PWM0_REMAP_EN
R-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
G_MUX_EN	RESERVED
R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-593 ICSSG_SA_MX_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	X
16	PWM_EFC_EN	R/W	0h	PWM efficiency mode 0 Legacy mode 1 Efficiency mode In this mode PWM SM will go from IDLE to ACTIVE and the same time PWM output will get updated during this SM state transition And IEP CMP flags will get auto HW cleared
15-12	RESERVED	R	X
16-12	RESERVED	R	X
11-10	PWM3_REMAP_EN	R/W	0h	If enabled, ICSSG Host interrupt 7 (PRU_ICSSGn_PR1_HOST_INTR_REQ_7) now controls pwm3_sync_in Only PRU_ICSSG0 controls the remap 0h = pwm_in_pwm3_sync_in_intc_h7 = pwm3_sync_in(no remap) 1h = pwm_in_pwm3_sync_in_intc_h7 = pr0_host_intr7_intr_pend (PRU_ICSSG0) 2h = pwm_in_pwm3_sync_in_intc_h7 = pr1_host_intr7_intr_pend (PRU_ICSSG1) 3h = Reserved
9-8	PWM0_REMAP_EN	R/W	0h	If enabled, ICSSG Host interrupt 6 (PRU_ICSSGn_PR1_HOST_INTR_REQ_6) now controls pwm0_sync_in Only PRU_ICSSG0 controls the remap 0h = pwm_in_pwm0_sync_in_intc_h6 = pwm_in_pwm0_sync_in (no remap) 1h = pwm_in_pwm0_sync_in_intc_h6 = pr0_host_intr6_intr_pend (PRU_ICSSG0) 2h = pwm_in_pwm0_sync_in_intc_h6 = pr1_host_intr6_intr_pend (PRU_ICSSG1) 3h = Reserved
7	G_MUX_EN	R/W	0h	See Table 6-391 for details. 0 Default/Legacy 1 Few SD and EnDAT pins get remapped to enable different usecase
7	RESERVED	R/W	0h	Reserved
6-0	RESERVED	R/W	0h	Reserved

4.14.5.14 ICSSG_PRU0_SD_CFG_REG Register (Offset = 44h) [reset = X]

ICSSG_PRU0_SD_CFG_REG is shown in Figure 6-309 and described in Table 6-595.

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SD Config Register.

Table 6-594 ICSSG_PRU0_SD_CFG_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6044h
PRU_ICSSG1_PR1_CFG_SLV	300A 6044h

Figure 6-309 ICSSG_PRU0_SD_CFG_REG Register

31	30	29	28	27	26	25	24
MAN_CLK_PERIOD
R-0h

23	22	21	20	19	18	17	16
RESERVED							MAN_CLK_CAL_DONE
R-X							R-0h

15	14	13	12	11	10	9	8
MAN_STATUS	CH_SEL				MAN_DATA_NV_EN	MAN_SD_EN	SHARE_EN
R-0h	R/W-0h				R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-X

LEGEND: R/W = Read/Write; R = Read Only-n = value after reset

Table 6-595 ICSSG_PRU0_SD_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MAN_CLK_PERIOD	R	0h	Estimated Manchester clock period for SDx
23-17	RESERVED	R	X
16	MAN_CLK_CAL_DONE	R	0h	Manchester clock calibration status for SDx. Manchester logic internal signal that indicates first completion of clock decoding phase (calibration stage 2 in Manchester decoding flowchart); status is sticky and cleared by reset
15	MAN_STATUS	R	0h	Manchester status for SDx.
14-11	CH_SEL	R/W	0h	Manchester SD channel select for the 3 status fields above 0 = SD0 .. 8 = SD8
10	MAN_DATA_NV_EN	R/W	0h	Manchester Decode Mode Data Inversion 0 = rising edge is 1 1 = falling edge is 1
9	MAN_SD_EN	R/W	0h	Manchester Decode Mode 0 = disable 1 = enable If enabled, then you need to enable one clock per data channel
8	SHARE_EN	R/W	0h	Load Share Enable 0 = PRUx owns SD0 - SD8 1 = RTUx owns SD0 - SD2, PRUx owns SD3 - SD5, TX_PRUx owns SD6 - SD8
7-0	RESERVED	R	X

4.14.5.15 ICSSG_PRU0_SD_CLK_SEL_REG0 Register (Offset = 48h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG0 is shown in Figure 6-310 and described in Table 6-597.

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PRU0 FD, ACC and Clock Selection Register 0.

Table 6-596 ICSSG_PRU0_SD_CLK_SEL_REG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6048h
PRU_ICSSG1_PR1_CFG_SLV	300A 6048h

Figure 6-310 ICSSG_PRU0_SD_CLK_SEL_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_0	PRU0_FD_ZERO_MAX_LIMIT_0					PRU0_FD_ZERO_MIN_0
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_0					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL0		RESERVED	PRU0_SD_CLK_INV0	PRU0_SD_CLK_SEL0
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-597 ICSSG_PRU0_SD_CLK_SEL_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_0	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_0	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_0	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_0	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL0	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV0	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL0	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.16 ICSSG_PRU0_SD_SAMPLE_SIZE_REG0 Register (Offset = 4Ch) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG0 is shown in Figure 6-311 and described in Table 6-599.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 0.

Table 6-598 ICSSG_PRU0_SD_SAMPLE_SIZE_REG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 604Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 604Ch

Figure 6-311 ICSSG_PRU0_SD_SAMPLE_SIZE_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_0	PRU0_FD_ONE_MAX_0	PRU0_FD_ONE_MAX_LIMIT_0					PRU0_FD_ONE_MIN_0
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_0					PRU0_FD_WINDOW_SIZE_0
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-599 ICSSG_PRU0_SD_SAMPLE_SIZE_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_0	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_0	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_0	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_0	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_0	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_0	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE0	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) Note: the 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 .. Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3hh, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.17 ICSSG_PRU0_SD_CLK_SEL_REG1 Register (Offset = 50h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG1 is shown in Figure 6-312 and described in Table 6-601.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 1.

Table 6-600 ICSSG_PRU0_SD_CLK_SEL_REG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6050h
PRU_ICSSG1_PR1_CFG_SLV	300A 6050h

Figure 6-312 ICSSG_PRU0_SD_CLK_SEL_REG1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_1	PRU0_FD_ZERO_MAX_LIMIT_1					PRU0_FD_ZERO_MIN_1
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_1					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL1		RESERVED	PRU0_SD_CLK_INV1	PRU0_SD_CLK_SEL1
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-601 ICSSG_PRU0_SD_CLK_SEL_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_1	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_1	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_1	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_1	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL1	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV1	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL1	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.18 ICSSG_PRU0_SD_SAMPLE_SIZE_REG1 Register (Offset = 54h) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG1 is shown in Figure 6-313 and described in Table 6-603.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 1.

Table 6-602 ICSSG_PRU0_SD_SAMPLE_SIZE_REG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6054h
PRU_ICSSG1_PR1_CFG_SLV	300A 6054h

Figure 6-313 ICSSG_PRU0_SD_SAMPLE_SIZE_REG1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_1	PRU0_FD_ONE_MAX_1	PRU0_FD_ONE_MAX_LIMIT_1					PRU0_FD_ONE_MIN_1
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_1					PRU0_FD_WINDOW_SIZE_1
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-603 ICSSG_PRU0_SD_SAMPLE_SIZE_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_1	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_1	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_1	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_1	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_1	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_1	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE1	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) Note: the 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.19 ICSSG_PRU0_SD_CLK_SEL_REG2 Register (Offset = 58h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG2 is shown in Figure 6-314 and described in Table 6-605.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 2

Table 6-604 ICSSG_PRU0_SD_CLK_SEL_REG2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6058h
PRU_ICSSG1_PR1_CFG_SLV	300A 6058h

Figure 6-314 ICSSG_PRU0_SD_CLK_SEL_REG2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_2	PRU0_FD_ZERO_MAX_LIMIT_2					PRU0_FD_ZERO_MIN_2
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_2					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL2		RESERVED	PRU0_SD_CLK_INV2	PRU0_SD_CLK_SEL2
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-605 ICSSG_PRU0_SD_CLK_SEL_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_2	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_2	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_2	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_2	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL2	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV2	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL2	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1= pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.20 ICSSG_PRU0_SD_SAMPLE_SIZE_REG2 Register (Offset = 5Ch) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG2 is shown in Figure 6-315 and described in Table 6-607.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 2.

Table 6-606 ICSSG_PRU0_SD_SAMPLE_SIZE_REG2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 605Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 605Ch

Figure 6-315 ICSSG_PRU0_SD_SAMPLE_SIZE_REG2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_2	PRU0_FD_ONE_MAX_2	PRU0_FD_ONE_MAX_LIMIT_2					PRU0_FD_ONE_MIN_2
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_2					PRU0_FD_WINDOW_SIZE_2
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-607 ICSSG_PRU0_SD_SAMPLE_SIZE_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_2	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_2	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_2	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_2	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_2	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_2	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE2	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) Note: the 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.21 ICSSG_PRU0_SD_CLK_SEL_REG3 Register (Offset = 60h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG3 is shown in Figure 6-316 and described in Table 6-609.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 3.

Table 6-608 ICSSG_PRU0_SD_CLK_SEL_REG3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6060h
PRU_ICSSG1_PR1_CFG_SLV	300A 6060h

Figure 6-316 ICSSG_PRU0_SD_CLK_SEL_REG3 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_3	PRU0_FD_ZERO_MAX_LIMIT_3					PRU0_FD_ZERO_MIN_3
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_3					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL3		RESERVED	PRU0_SD_CLK_INV3	PRU0_SD_CLK_SEL3
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-609 ICSSG_PRU0_SD_CLK_SEL_REG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_3	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_3	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_3	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_3	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL3	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV3	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL3	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.22 ICSSG_PRU0_SD_SAMPLE_SIZE_REG3 Register (Offset = 64h) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG3 is shown in Figure 6-317 and described in Table 6-611.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 3.

Table 6-610 ICSSG_PRU0_SD_SAMPLE_SIZE_REG3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6064h
PRU_ICSSG1_PR1_CFG_SLV	300A 6064h

Figure 6-317 ICSSG_PRU0_SD_SAMPLE_SIZE_REG3 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_3	PRU0_FD_ONE_MAX_3	PRU0_FD_ONE_MAX_LIMIT_3					PRU0_FD_ONE_MIN_3
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_3					PRU0_FD_WINDOW_SIZE_3
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE3
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-611 ICSSG_PRU0_SD_SAMPLE_SIZE_REG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_3	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_3	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_3	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_3	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_3	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_3	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE3	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) Note: the 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.23 ICSSG_PRU0_SD_CLK_SEL_REG4 Register (Offset = 68h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG4 is shown in Figure 6-318 and described in Table 6-613.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 4.

Table 6-612 ICSSG_PRU0_SD_CLK_SEL_REG4 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6068h
PRU_ICSSG1_PR1_CFG_SLV	300A 6068h

Figure 6-318 ICSSG_PRU0_SD_CLK_SEL_REG4 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_4	PRU0_FD_ZERO_MAX_LIMIT_4					PRU0_FD_ZERO_MIN_4
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_4					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL4		RESERVED	PRU0_SD_CLK_INV4	PRU0_SD_CLK_SEL4
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-613 ICSSG_PRU0_SD_CLK_SEL_REG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_4	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_4	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_4	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_4	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL4	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV4	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL4	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.24 ICSSG_PRU0_SD_SAMPLE_SIZE_REG4 Register (Offset = 6Ch) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG4 is shown in Figure 6-319 and described in Table 6-615.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 4.

Table 6-614 ICSSG_PRU0_SD_SAMPLE_SIZE_REG4 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 606Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 606Ch

Figure 6-319 ICSSG_PRU0_SD_SAMPLE_SIZE_REG4 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_4	PRU0_FD_ONE_MAX_4	PRU0_FD_ONE_MAX_LIMIT_4					PRU0_FD_ONE_MIN_4
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_4					PRU0_FD_WINDOW_SIZE_4
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE4
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-615 ICSSG_PRU0_SD_SAMPLE_SIZE_REG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_4	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_4	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_4	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_4	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_4	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_4	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE4	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.25 ICSSG_PRU0_SD_CLK_SEL_REG5 Register (Offset = 70h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG5 is shown in Figure 6-320 and described in Table 6-617.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 5.

Table 6-616 ICSSG_PRU0_SD_CLK_SEL_REG5 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6070h
PRU_ICSSG1_PR1_CFG_SLV	300A 6070h

Figure 6-320 ICSSG_PRU0_SD_CLK_SEL_REG5 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_5	PRU0_FD_ZERO_MAX_LIMIT_5					PRU0_FD_ZERO_MIN_5
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_5					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL5		RESERVED	PRU0_SD_CLK_INV5	PRU0_SD_CLK_SEL5
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-617 ICSSG_PRU0_SD_CLK_SEL_REG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_5	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_5	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_5	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_5	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL5	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV5	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL5	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.26 ICSSG_PRU0_SD_SAMPLE_SIZE_REG5 Register (Offset = 74h) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG5 is shown in Figure 6-321 and described in Table 6-619.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 5.

Table 6-618 ICSSG_PRU0_SD_SAMPLE_SIZE_REG5 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6074h
PRU_ICSSG1_PR1_CFG_SLV	300A 6074h

Figure 6-321 ICSSG_PRU0_SD_SAMPLE_SIZE_REG5 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_5	PRU0_FD_ONE_MAX_5	PRU0_FD_ONE_MAX_LIMIT_5					PRU0_FD_ONE_MIN_5
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_5					PRU0_FD_WINDOW_SIZE_5
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE5
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-619 ICSSG_PRU0_SD_SAMPLE_SIZE_REG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_5	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_5	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_5	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_5	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_5	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_5	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE5	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.27 ICSSG_PRU0_SD_CLK_SEL_REG6 Register (Offset = 78h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG6 is shown in Figure 6-322 and described in Table 6-621.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 6.

Table 6-620 ICSSG_PRU0_SD_CLK_SEL_REG6 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6078h
PRU_ICSSG1_PR1_CFG_SLV	300A 6078h

Figure 6-322 ICSSG_PRU0_SD_CLK_SEL_REG6 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_6	PRU0_FD_ZERO_MAX_LIMIT_6					PRU0_FD_ZERO_MIN_6
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_6					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL6		RESERVED	PRU0_SD_CLK_INV6	PRU0_SD_CLK_SEL6
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-621 ICSSG_PRU0_SD_CLK_SEL_REG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_6	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_6	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_6	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_6	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL6	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV6	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL6	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.28 ICSSG_PRU0_SD_SAMPLE_SIZE_REG6 Register (Offset = 7Ch) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG6 is shown in Figure 6-323 and described in Table 6-623.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 6.

Table 6-622 ICSSG_PRU0_SD_SAMPLE_SIZE_REG6 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 607Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 607Ch

Figure 6-323 ICSSG_PRU0_SD_SAMPLE_SIZE_REG6 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_6	PRU0_FD_ONE_MAX_6	PRU0_FD_ONE_MAX_LIMIT_6					PRU0_FD_ONE_MIN_6
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_6					PRU0_FD_WINDOW_SIZE_6
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE6
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-623 ICSSG_PRU0_SD_SAMPLE_SIZE_REG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_6	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_6	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_6	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_6	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_6	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_6	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE6	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.29 ICSSG_PRU0_SD_CLK_SEL_REG7 Register (Offset = 80h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG7 is shown in Figure 6-324 and described in Table 6-625.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 7.

Table 6-624 ICSSG_PRU0_SD_CLK_SEL_REG7 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6080h
PRU_ICSSG1_PR1_CFG_SLV	300A 6080h

Figure 6-324 ICSSG_PRU0_SD_CLK_SEL_REG7 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_7	PRU0_FD_ZERO_MAX_LIMIT_7					PRU0_FD_ZERO_MIN_7
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_7					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL7		RESERVED	PRU0_SD_CLK_INV7	PRU0_SD_CLK_SEL7
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-625 ICSSG_PRU0_SD_CLK_SEL_REG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_7	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_7	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_7	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_7	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL7	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV7	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL7	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.30 ICSSG_PRU0_SD_SAMPLE_SIZE_REG7 Register (Offset = 84h) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG7 is shown in Figure 6-325 and described in Table 6-627.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 7.

Table 6-626 ICSSG_PRU0_SD_SAMPLE_SIZE_REG7 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6084h
PRU_ICSSG1_PR1_CFG_SLV	300A 6084h

Figure 6-325 ICSSG_PRU0_SD_SAMPLE_SIZE_REG7 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_7	PRU0_FD_ONE_MAX_7	PRU0_FD_ONE_MAX_LIMIT_7					PRU0_FD_ONE_MIN_7
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_7					PRU0_FD_WINDOW_SIZE_7
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE7
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-627 ICSSG_PRU0_SD_SAMPLE_SIZE_REG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_7	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_7	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_7	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_7	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_7	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_7	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE7	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.31 ICSSG_PRU0_SD_CLK_SEL_REG8 Register (Offset = 88h) [reset = X]

ICSSG_PRU0_SD_CLK_SEL_REG8 is shown in Figure 6-326 and described in Table 6-629.

Return to Summary Table.

PRU0 FD, ACC and Clock Selection Register 8.

Table 6-628 ICSSG_PRU0_SD_CLK_SEL_REG8 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6088h
PRU_ICSSG1_PR1_CFG_SLV	300A 6088h

Figure 6-326 ICSSG_PRU0_SD_CLK_SEL_REG8 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU0_FD_ZERO_MAX_8	PRU0_FD_ZERO_MAX_LIMIT_8					PRU0_FD_ZERO_MIN_8
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ZERO_MIN_LIMIT_8					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU0_SD_ACC_SEL8		RESERVED	PRU0_SD_CLK_INV8	PRU0_SD_CLK_SEL8
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-629 ICSSG_PRU0_SD_CLK_SEL_REG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU0_FD_ZERO_MAX_8	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ZERO_MAX_LIMIT_8	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ZERO_MIN_8	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ZERO_MIN_LIMIT_8	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU0_SD_ACC_SEL8	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU0_SD_CLK_INV8	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU0_SD_CLK_SEL8	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.32 ICSSG_PRU0_SD_SAMPLE_SIZE_REG8 Register (Offset = 8Ch) [reset = X]

ICSSG_PRU0_SD_SAMPLE_SIZE_REG8 is shown in Figure 6-327 and described in Table 6-631.

Return to Summary Table.

PRU0 FD and Over Sample Size Register 8.

Table 6-630 ICSSG_PRU0_SD_SAMPLE_SIZE_REG8 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 608Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 608Ch

Figure 6-327 ICSSG_PRU0_SD_SAMPLE_SIZE_REG8 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU0_FD_EN_8	PRU0_FD_ONE_MAX_8	PRU0_FD_ONE_MAX_LIMIT_8					PRU0_FD_ONE_MIN_8
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU0_FD_ONE_MIN_LIMIT_8					PRU0_FD_WINDOW_SIZE_8
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_SD_SAMPLE_SIZE8
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-631 ICSSG_PRU0_SD_SAMPLE_SIZE_REG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU0_FD_EN_8	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU0_FD_ONE_MAX_8	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU0_FD_ONE_MAX_LIMIT_8	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU0_FD_ONE_MIN_8	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU0_FD_ONE_MIN_LIMIT_8	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU0_FD_WINDOW_SIZE_8	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU0_SD_SAMPLE_SIZE8	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.33 ICSSG_PRU1_SD_CFG_REG Register (Offset = 90h) [reset = X]

ICSSG_PRU1_SD_CFG_REG is shown in Figure 6-328 and described in Table 6-633.

Return to Summary Table.

SD Register.

Table 6-632 ICSSG_PRU1_SD_CFG_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6090h
PRU_ICSSG1_PR1_CFG_SLV	300A 6090h

Figure 6-328 ICSSG_PRU1_SD_CFG_REG Register

31	30	29	28	27	26	25	24
MAN_CLK_PERIOD
R-0h

23	22	21	20	19	18	17	16
RESERVED							MAN_CLK_CAL_DONE
R-X							R-0h

15	14	13	12	11	10	9	8
MAN_STATUS	SH_SEL				MAN_DATA_NV_EN	MAN_SD_EN	SHARE_EN
R-0h	R/W-0h				R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-X

LEGEND: R/W = Read/Write; R = Read Only-n = value after reset

Table 6-633 ICSSG_PRU1_SD_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MAN_CLK_PERIOD	R	0h	Manchester clock period status for SDx
23-17	RESERVED	R	X
16	MAN_CLK_CAL_DONE	R	0h	Manchester clock calibration status for SDx
15	MAN_STATUS	R	0h	Manchester status for SDx
14-11	SH_SEL	R/W	0h	Manchester SD Ch select for the 3 status fields 0 = SD0 .. 8 = SD8
10	MAN_DATA_NV_EN	R/W	0h	Manchester Decode Mode Data Inversion 0 = rising edge is 1 1 = falling edge is 1
9	MAN_SD_EN	R/W	0h	Manchester Decode Mode 0 = disable 1 = enable If enabled, then you need to enable one clock per data channel
8	SHARE_EN	R/W	0h	Load Share Enable 0 = PRUx owns SD0 -> SD8 1 = RTUx owns SD0 -> SD2, PRUx owns SD3 ->SD5, TX_PRUx owns SD6->SD8
7-0	RESERVED	R	X

4.14.5.34 ICSSG_PRU1_SD_CLK_SEL_REG0 Register (Offset = 94h) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG0 is shown in Figure 6-329 and described in Table 6-635.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 0

Table 6-634 ICSSG_PRU1_SD_CLK_SEL_REG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6094h
PRU_ICSSG1_PR1_CFG_SLV	300A 6094h

Figure 6-329 ICSSG_PRU1_SD_CLK_SEL_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_0	PRU1_FD_ZERO_MAX_LIMIT_0					PRU1_FD_ZERO_MIN_0
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_0					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL0		RESERVED	PRU1_SD_CLK_INV0	PRU1_SD_CLK_SEL0
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-635 ICSSG_PRU1_SD_CLK_SEL_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_0	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_0	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_0	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_0	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL0	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV0	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL0	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.35 ICSSG_PRU1_SD_SAMPLE_SIZE_REG0 Register (Offset = 98h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG0 is shown in Figure 6-330 and described in Table 6-637.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 0.

Table 6-636 ICSSG_PRU1_SD_SAMPLE_SIZE_REG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6098h
PRU_ICSSG1_PR1_CFG_SLV	300A 6098h

Figure 6-330 ICSSG_PRU1_SD_SAMPLE_SIZE_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_0	PRU1_FD_ONE_MAX_0	PRU1_FD_ONE_MAX_LIMIT_0					PRU1_FD_ONE_MIN_0
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_0					PRU1_FD_WINDOW_SIZE_0
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-637 ICSSG_PRU1_SD_SAMPLE_SIZE_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_0	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_0	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_0	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_0	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_0	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_0	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE0	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.36 ICSSG_PRU1_SD_CLK_SEL_REG1 Register (Offset = 9Ch) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG1 is shown in Figure 6-331 and described in Table 6-639.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 1.

Table 6-638 ICSSG_PRU1_SD_CLK_SEL_REG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 609Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 609Ch

Figure 6-331 ICSSG_PRU1_SD_CLK_SEL_REG1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_1	PRU1_FD_ZERO_MAX_LIMIT_1					PRU1_FD_ZERO_MIN_1
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_1					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL1		RESERVED	PRU1_SD_CLK_INV1	PRU1_SD_CLK_SEL1
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-639 ICSSG_PRU1_SD_CLK_SEL_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_1	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_1	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1 = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_1	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_1	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL1	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV1	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL1	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.37 ICSSG_PRU1_SD_SAMPLE_SIZE_REG1 Register (Offset = A0h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG1 is shown in Figure 6-332 and described in Table 6-641.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 1.

Table 6-640 ICSSG_PRU1_SD_SAMPLE_SIZE_REG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60A0h
PRU_ICSSG1_PR1_CFG_SLV	300A 60A0h

Figure 6-332 ICSSG_PRU1_SD_SAMPLE_SIZE_REG1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_1	PRU1_FD_ONE_MAX_1	PRU1_FD_ONE_MAX_LIMIT_1					PRU1_FD_ONE_MIN_1
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_1					PRU1_FD_WINDOW_SIZE_1
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-641 ICSSG_PRU1_SD_SAMPLE_SIZE_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_1	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_1	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_1	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_1	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_1	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_1	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE1	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.38 ICSSG_PRU1_SD_CLK_SEL_REG2 Register (Offset = A4h) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG2 is shown in Figure 6-333 and described in Table 6-643.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 2.

Table 6-642 ICSSG_PRU1_SD_CLK_SEL_REG2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60A4h
PRU_ICSSG1_PR1_CFG_SLV	300A 60A4h

Figure 6-333 ICSSG_PRU1_SD_CLK_SEL_REG2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_2	PRU1_FD_ZERO_MAX_LIMIT_2					PRU1_FD_ZERO_MIN_2
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_2					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL2		RESERVED	PRU1_SD_CLK_INV2	PRU1_SD_CLK_SEL2
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-643 ICSSG_PRU1_SD_CLK_SEL_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_2	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_2	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_2	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_2	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL2	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV2	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL2	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.39 ICSSG_PRU1_SD_SAMPLE_SIZE_REG2 Register (Offset = A8h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG2 is shown in Figure 6-334 and described in Table 6-645.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 2.

Table 6-644 ICSSG_PRU1_SD_SAMPLE_SIZE_REG2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60A8h
PRU_ICSSG1_PR1_CFG_SLV	300A 60A8h

Figure 6-334 ICSSG_PRU1_SD_SAMPLE_SIZE_REG2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_2	PRU1_FD_ONE_MAX_2	PRU1_FD_ONE_MAX_LIMIT_2					PRU1_FD_ONE_MIN_2
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_2					PRU1_FD_WINDOW_SIZE_2
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-645 ICSSG_PRU1_SD_SAMPLE_SIZE_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_2	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_2	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_2	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_2	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_2	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_2	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE2	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.40 ICSSG_PRU1_SD_CLK_SEL_REG3 Register (Offset = ACh) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG3 is shown in Figure 6-335 and described in Table 6-647.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 3.

Table 6-646 ICSSG_PRU1_SD_CLK_SEL_REG3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60ACh
PRU_ICSSG1_PR1_CFG_SLV	300A 60ACh

Figure 6-335 ICSSG_PRU1_SD_CLK_SEL_REG3 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_3	PRU1_FD_ZERO_MAX_LIMIT_3					PRU1_FD_ZERO_MIN_3
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_3					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL3		RESERVED	PRU1_SD_CLK_INV3	PRU1_SD_CLK_SEL3
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-647 ICSSG_PRU1_SD_CLK_SEL_REG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_3	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_3	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_3	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_3	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL3	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV3	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL3	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.41 ICSSG_PRU1_SD_SAMPLE_SIZE_REG3 Register (Offset = B0h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG3 is shown in Figure 6-336 and described in Table 6-649.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 3.

Table 6-648 ICSSG_PRU1_SD_SAMPLE_SIZE_REG3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60B0h
PRU_ICSSG1_PR1_CFG_SLV	300A 60B0h

Figure 6-336 ICSSG_PRU1_SD_SAMPLE_SIZE_REG3 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_3	PRU1_FD_ONE_MAX_3	PRU1_FD_ONE_MAX_LIMIT_3					PRU1_FD_ONE_MIN_3
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_3					PRU1_FD_WINDOW_SIZE_3
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE3
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-649 ICSSG_PRU1_SD_SAMPLE_SIZE_REG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_3	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_3	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_3	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_3	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_3	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_3	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE3	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.42 ICSSG_PRU1_SD_CLK_SEL_REG4 Register (Offset = B4h) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG4 is shown in Figure 6-337 and described in Table 6-651.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 4.

Table 6-650 ICSSG_PRU1_SD_CLK_SEL_REG4 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60B4h
PRU_ICSSG1_PR1_CFG_SLV	300A 60B4h

Figure 6-337 ICSSG_PRU1_SD_CLK_SEL_REG4 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_4	PRU1_FD_ZERO_MAX_LIMIT_4					PRU1_FD_ZERO_MIN_4
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_4					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL4		RESERVED	PRU1_SD_CLK_INV4	PRU1_SD_CLK_SEL4
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-651 ICSSG_PRU1_SD_CLK_SEL_REG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_4	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_4	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_4	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_4	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL4	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV4	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL4	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.43 ICSSG_PRU1_SD_SAMPLE_SIZE_REG4 Register (Offset = B8h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG4 is shown in Figure 6-338 and described in Table 6-653.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 4.

Table 6-652 ICSSG_PRU1_SD_SAMPLE_SIZE_REG4 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60B8h
PRU_ICSSG1_PR1_CFG_SLV	300A 60B8h

Figure 6-338 ICSSG_PRU1_SD_SAMPLE_SIZE_REG4 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_4	PRU1_FD_ONE_MAX_4	PRU1_FD_ONE_MAX_LIMIT_4					PRU1_FD_ONE_MIN_4
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_4					PRU1_FD_WINDOW_SIZE_4
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE4
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-653 ICSSG_PRU1_SD_SAMPLE_SIZE_REG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_4	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_4	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_4	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_4	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_4	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_4	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE4	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.44 ICSSG_PRU1_SD_CLK_SEL_REG5 Register (Offset = BCh) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG5 is shown in Figure 6-339 and described in Table 6-655.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 5

Table 6-654 ICSSG_PRU1_SD_CLK_SEL_REG5 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60BCh
PRU_ICSSG1_PR1_CFG_SLV	300A 60BCh

Figure 6-339 ICSSG_PRU1_SD_CLK_SEL_REG5 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_5	PRU1_FD_ZERO_MAX_LIMIT_5					PRU1_FD_ZERO_MIN_5
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_5					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL5		RESERVED	PRU1_SD_CLK_INV5	PRU1_SD_CLK_SEL5
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-655 ICSSG_PRU1_SD_CLK_SEL_REG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_5	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_5	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_5	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_5	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL5	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV5	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL5	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.45 ICSSG_PRU1_SD_SAMPLE_SIZE_REG5 Register (Offset = C0h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG5 is shown in Figure 6-340 and described in Table 6-657.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 5

Table 6-656 ICSSG_PRU1_SD_SAMPLE_SIZE_REG5 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60C0h
PRU_ICSSG1_PR1_CFG_SLV	300A 60C0h

Figure 6-340 ICSSG_PRU1_SD_SAMPLE_SIZE_REG5 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_5	PRU1_FD_ONE_MAX_5	PRU1_FD_ONE_MAX_LIMIT_5					PRU1_FD_ONE_MIN_5
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_5					PRU1_FD_WINDOW_SIZE_5
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE5
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-657 ICSSG_PRU1_SD_SAMPLE_SIZE_REG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_5	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_5	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_5	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_5	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_5	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_5	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE5	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.46 ICSSG_PRU1_SD_CLK_SEL_REG6 Register (Offset = C4h) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG6 is shown in Figure 6-341 and described in Table 6-659.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 6

Table 6-658 ICSSG_PRU1_SD_CLK_SEL_REG6 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60C4h
PRU_ICSSG1_PR1_CFG_SLV	300A 60C4h

Figure 6-341 ICSSG_PRU1_SD_CLK_SEL_REG6 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_6	PRU1_FD_ZERO_MAX_LIMIT_6					PRU1_FD_ZERO_MIN_6
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_6					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL6		RESERVED	PRU1_SD_CLK_INV6	PRU1_SD_CLK_SEL6
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-659 ICSSG_PRU1_SD_CLK_SEL_REG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_6	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_6	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_6	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_6	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL6	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV6	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL6	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.47 ICSSG_PRU1_SD_SAMPLE_SIZE_REG6 Register (Offset = C8h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG6 is shown in Figure 6-342 and described in Table 6-661.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 6

Table 6-660 ICSSG_PRU1_SD_SAMPLE_SIZE_REG6 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60C8h
PRU_ICSSG1_PR1_CFG_SLV	300A 60C8h

Figure 6-342 ICSSG_PRU1_SD_SAMPLE_SIZE_REG6 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_6	PRU1_FD_ONE_MAX_6	PRU1_FD_ONE_MAX_LIMIT_6					PRU1_FD_ONE_MIN_6
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_6					PRU1_FD_WINDOW_SIZE_6
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE6
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-661 ICSSG_PRU1_SD_SAMPLE_SIZE_REG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_6	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_6	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_6	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_6	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_6	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_6	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE6	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.48 ICSSG_PRU1_SD_CLK_SEL_REG7 Register (Offset = CCh) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG7 is shown in Figure 6-343 and described in Table 6-663.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 7

Table 6-662 ICSSG_PRU1_SD_CLK_SEL_REG7 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60CCh
PRU_ICSSG1_PR1_CFG_SLV	300A 60CCh

Figure 6-343 ICSSG_PRU1_SD_CLK_SEL_REG7 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_7	PRU1_FD_ZERO_MAX_LIMIT_7					PRU1_FD_ZERO_MIN_7
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_7					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL7		RESERVED	PRU1_SD_CLK_INV7	PRU1_SD_CLK_SEL7
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-663 ICSSG_PRU1_SD_CLK_SEL_REG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_7	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_7	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_7	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_7	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL7	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV7	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL7	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.49 ICSSG_PRU1_SD_SAMPLE_SIZE_REG7 Register (Offset = D0h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG7 is shown in Figure 6-344 and described in Table 6-665.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 7

Table 6-664 ICSSG_PRU1_SD_SAMPLE_SIZE_REG7 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60D0h
PRU_ICSSG1_PR1_CFG_SLV	300A 60D0h

Figure 6-344 ICSSG_PRU1_SD_SAMPLE_SIZE_REG7 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_7	PRU1_FD_ONE_MAX_7	PRU1_FD_ONE_MAX_LIMIT_7					PRU1_FD_ONE_MIN_7
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_7					PRU1_FD_WINDOW_SIZE_7
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE7
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-665 ICSSG_PRU1_SD_SAMPLE_SIZE_REG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_7	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_7	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_7	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_7	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_7	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_7	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE7	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.50 ICSSG_PRU1_SD_CLK_SEL_REG8 Register (Offset = D4h) [reset = X]

ICSSG_PRU1_SD_CLK_SEL_REG8 is shown in Figure 6-345 and described in Table 6-667.

Return to Summary Table.

PRU1 FD, ACC and Clock Selection Register 8

Table 6-666 ICSSG_PRU1_SD_CLK_SEL_REG8 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60D4h
PRU_ICSSG1_PR1_CFG_SLV	300A 60D4h

Figure 6-345 ICSSG_PRU1_SD_CLK_SEL_REG8 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED	PRU1_FD_ZERO_MAX_8	PRU1_FD_ZERO_MAX_LIMIT_8					PRU1_FD_ZERO_MIN_8
R/W-X	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ZERO_MIN_LIMIT_8					RESERVED
R/W-0h					R/W-X

7	6	5	4	3	2	1	0
RESERVED		PRU1_SD_ACC_SEL8		RESERVED	PRU1_SD_CLK_INV8	PRU1_SD_CLK_SEL8
R/W-X		R/W-0h		R/W-X	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-667 ICSSG_PRU1_SD_CLK_SEL_REG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22	PRU1_FD_ZERO_MAX_8	R/W	0h	Fast Detect Zero Count Max Threshold Hit The number of zeros in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ZERO_MAX_LIMIT_8	R/W	0h	Fast Detect Zero Count Max Threshold More than or Equal will assert fd_max_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ZERO_MIN_8	R/W	0h	Fast Detect Zero Count Min Threshold Hit The number of zeros in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ZERO_MIN_LIMIT_8	R/W	0h	Fast Detect Zero Count Min Threshold Less than or Equal will assert fd_min_zero_hit 0h = 1 1h = 2 .. 1Fh = 32
10-6	RESERVED	R/W	X
5-4	PRU1_SD_ACC_SEL8	R/W	0h	0h = acc3 is selected 1h = acc2 is selected 2h = acc1 is selected
3	RESERVED	R/W	X
2	PRU1_SD_CLK_INV8	R/W	0h	Optional clock inversion post clock selection multiplexer 0h = No inversion 1h = Inversion
1-0	PRU1_SD_CLK_SEL8	R/W	0h	Selects the clock source 0h = pr1_pru<n>_pru_r31_in[16] Primary Input 1h = pr1_pru<n>_sd<m>_clk Primary Input 2h = pr1_pru<n>_sd0_clk Primary Input For sd0,sd1, and sd2 pr1_pru<n>_sd3_clk Primary Input For sd3,sd4, and sd5 pr1_pru<n>_sd6_clk Primary Input For sd6,sd7, and sd8 3h = Reserved

4.14.5.51 ICSSG_PRU1_SD_SAMPLE_SIZE_REG8 Register (Offset = D8h) [reset = X]

ICSSG_PRU1_SD_SAMPLE_SIZE_REG8 is shown in Figure 6-346 and described in Table 6-669.

Return to Summary Table.

PRU1 FD and Over Sample Size Register 8

Table 6-668 ICSSG_PRU1_SD_SAMPLE_SIZE_REG8 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60D8h
PRU_ICSSG1_PR1_CFG_SLV	300A 60D8h

Figure 6-346 ICSSG_PRU1_SD_SAMPLE_SIZE_REG8 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
PRU1_FD_EN_8	PRU1_FD_ONE_MAX_8	PRU1_FD_ONE_MAX_LIMIT_8					PRU1_FD_ONE_MIN_8
R/W-0h	R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PRU1_FD_ONE_MIN_LIMIT_8					PRU1_FD_WINDOW_SIZE_8
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_SD_SAMPLE_SIZE8
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-669 ICSSG_PRU1_SD_SAMPLE_SIZE_REG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23	PRU1_FD_EN_8	R/W	0h	Fast Detect One Enable 0h = Disable The events will not assert 1h = Enabled The events can assert, the monitor/shift is active
22	PRU1_FD_ONE_MAX_8	R/W	0h	Fast Detect One Count Max Threshold Hit The number of ones in the sliding window is greater than or equal to threshold Write 1 to clear
21-17	PRU1_FD_ONE_MAX_LIMIT_8	R/W	0h	Fast Detect One Count Max Threshold Less than or Equal will assert fd_max_one_hit 0h = 1 1h = 2 .. 1Fh = 32
16	PRU1_FD_ONE_MIN_8	R/W	0h	Fast Detect One Count Min Threshold Hit The number of ones in the sliding window is less than or equal to threshold Write 1 to clear
15-11	PRU1_FD_ONE_MIN_LIMIT_8	R/W	0h	Fast Detect One Count Min Threshold Less than or Equal will assert fd_min_one_hit 0h = 1 1h = 2 .. 1Fh = 32
10-8	PRU1_FD_WINDOW_SIZE_8	R/W	0h	Fast Detect Window Size The number of contiguous samples to monitor A 32-bit shift register is used for the monitor This defines the mask size of the count logic 0h = 4 1h = 8 .. 7h = 32
7-0	PRU1_SD_SAMPLE_SIZE8	R/W	0h	Over Sample Rate Sample size; how many samples to take before shadow register updated and flag set. The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 Nh = Over Sample of N + 1 Note: SB detection uses OVER_SAMPLE_SIZE to determine when to set first VAL flag after first 1 is sampled. It will be set after Over Sample Rate count For example, if OSR is set to 3h, then the third clock after first 1 is detected, the VAL will get set.

4.14.5.52 ICSSG_PRU0_ED_RX_CFG_REG Register (Offset = E0h) [reset = X]

ICSSG_PRU0_ED_RX_CFG_REG is shown in Figure 6-347 and described in Table 6-671.

Return to Summary Table.

PRU0 ED Receive Global Configuration Register

Table 6-670 ICSSG_PRU0_ED_RX_CFG_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60E0h
PRU_ICSSG1_PR1_CFG_SLV	300A 60E0h

Figure 6-347 ICSSG_PRU0_ED_RX_CFG_REG Register

31	30	29	28	27	26	25	24
PRU0_ED_RX_DIV_FACTOR
R/W-0h

23	22	21	20	19	18	17	16
PRU0_ED_RX_DIV_FACTOR
R/W-0h

15	14	13	12	11	10	9	8
PRU0_ED_RX_DIV_FACTOR_FRAC	RESERVED
R/W-0h	R/W-X

7	6	5	4	3	2	1	0
RESERVED			PRU0_ED_RX_CLK_SEL	PRU0_ED_RX_SB_POL	PRU0_ED_RX_SAMPLE_SIZE
R/W-X			R/W-0h	R/W-1h	R/W-7h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-671 ICSSG_PRU0_ED_RX_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU0_ED_RX_DIV_FACTOR	R/W	0h	Div factor for divh16 0h = div 1 1h = div 2 Nh = div (N+1) This divh16 is post divfrac, the effective rate will be Effective rate is 1.5 X main div if frac enabled Effective rate is 1.0 X main div if frac disabled For example , divh16 set to 3h Div by 6 if frac enabled Div by 4 if frac enabled For example , divh16 set to 4 Div by 7.5 if frac enabled Div by 5 if frac enabled
15	PRU0_ED_RX_DIV_FACTOR_FRAC	R/W	0h	Enable Fractional division before the divh16 0h = div 1 1h = div 1.5
14-5	RESERVED	R/W	X
4	PRU0_ED_RX_CLK_SEL	R/W	0h	Selects the clock source for the divh16fr 0 =192 MHz, the uart_clk 1h = 200 MHz, the ICSSGn_CORE_CLK
3	PRU0_ED_RX_SB_POL	R/W	1h	Defines the polarity of the RX Start Bit 0h = 0 1h = 1 Reset/default state
2-0	PRU0_ED_RX_SAMPLE_SIZE	R/W	7h	Over Sample size This defines the number of samples before the shadow copy gets updated and the VAL flag gets set The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 6 = Over Sample of 7 7 = Over Sample of 8 Note: the Over Sample Clock rate divided by the 1x Clock rate must equal the Over Sample size.

4.14.5.53 ICSSG_PRU0_ED_TX_CFG_REG Register (Offset = E4h) [reset = X]

ICSSG_PRU0_ED_TX_CFG_REG is shown in Figure 6-348 and described in Table 6-673.

Return to Summary Table.

PRU0 ED Transmit Global Configuration Register

Table 6-672 ICSSG_PRU0_ED_TX_CFG_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60E4h
PRU_ICSSG1_PR1_CFG_SLV	300A 60E4h

Figure 6-348 ICSSG_PRU0_ED_TX_CFG_REG Register

31	30	29	28	27	26	25	24
PRU0_ED_TX_DIV_FACTOR
R/W-0h

23	22	21	20	19	18	17	16
PRU0_ED_TX_DIV_FACTOR
R/W-0h

15	14	13	12	11	10	9	8
PRU0_ED_TX_DIV_FACTOR_FRAC	RESERVED			SHARE_EN	PRU0_ENDAT2_CLK_SYNC	PRU0_ENDAT1_CLK_SYNC	PRU0_ENDAT0_CLK_SYNC
R/W-0h	R/W-X			R/W-0h	R-1h	R-1h	R-1h

7	6	5	4	3	2	1	0
PRU0_ED_BUSY_2	PRU0_ED_BUSY_1	PRU0_ED_BUSY_0	PRU0_ED_TX_CLK_SEL	RESERVED
R-0h	R-0h	R-0h	R/W-0h	R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-673 ICSSG_PRU0_ED_TX_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU0_ED_TX_DIV_FACTOR	R/W	0h	Div factor for divh16 0h = div 1 1h = div 2 Nh = div (N+1) This divh16 is post divfrac, the effective rate will be Effective rate is 1.5 X main div if frac enabled Effective rate is 1.0 X main div if frac disabled For example , divh16 set to 3h Div by 6 if frac enabled Div by 4 if frac enabled For example , divh16 set to 4 Div by 7.5 if frac enabled Div by 5 if frac enabled
15	PRU0_ED_TX_DIV_FACTOR_FRAC	R/W	0h	Enable Fractional division before the divh16 0h = div 1 1h = div 1.5
14-11	RESERVED	R/W	X
14-12	RESERVED	R/W	X
11	SHARE_EN	R/W	0h	Load Share Enable 0 PRU owns ED0/ED1/ED2 1 RTU owns ED0, PRU owns ED1, and TS_PRU owns ED2
10	PRU0_ENDAT2_CLK_SYNC	R	1h	Observation of pru<n>_endat2_clk pin state
9	PRU0_ENDAT1_CLK_SYNC	R	1h	Observation of pru<n>_endat1_clk pin state
8	PRU0_ENDAT0_CLK_SYNC	R	1h	Observation of pru<n>_endat0_clk pin state
7	PRU0_ED_BUSY_2	R	0h	Determines when you can assert tx go for channel 2 0h = Not busy ready to go 1h = Busy not ready to go Can be used to determine when it issue a new TX frame
6	PRU0_ED_BUSY_1	R	0h	Determines when you can assert tx go for channel 1 0h = Not busy ready to go 1h = Busy not ready to go Can be used to determine when it issue a new TX frame
5	PRU0_ED_BUSY_0	R	0h	Determines when you can assert tx go for channel 0 0h = Not busy ready to go 1h = Busy not ready to go Can be used to determine when it issue a new TX frame
4	PRU0_ED_TX_CLK_SEL	R/W	0h	Selects the clock source for the divh16fr 0h = 192 MHz, the uart_clk 1h = 200 MHz, the ICSSGn_CORE_CLK
3-0	RESERVED	R/W	X

4.14.5.54 ICSSG_PRU0_ED_CH0_CFG0_REG Register (Offset = E8h) [reset = 0h]

ICSSG_PRU0_ED_CH0_CFG0_REG is shown in Figure 6-349 and described in Table 6-675.

Return to Summary Table.

PRU0 ED Channel 0 Configuration 0 Register

Table 6-674 ICSSG_PRU0_ED_CH0_CFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60E8h
PRU_ICSSG1_PR1_CFG_SLV	300A 60E8h

Figure 6-349 ICSSG_PRU0_ED_CH0_CFG0_REG Register

31	30	29	28	27	26	25	24
PRU0_ED_TX_FIFO_SWAP_BITS0	PRU0_ED_SW_CLK_OUT0	PRU0_ED_CLK_OUT_OVR_EN0	PRU0_ED_RX_SNOOP0	PRU0_ED_RX_FRAME_SIZE0
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU0_ED_RX_FRAME_SIZE0
R/W-0h

15	14	13	12	11	10	9	8
PRU0_ED_TX_FRAME_SIZE0					PRU0_ED_TX_WDLY0
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_ED_TX_WDLY0
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-675 ICSSG_PRU0_ED_CH0_CFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRU0_ED_TX_FIFO_SWAP_BITS0	R/W	0h	This enables the swapping of the bits when they are loaded into the TX FIFO. 0h = no swap [7:0] -> [7:0] 1h = swap [7:0] -> [0:7]
30	PRU0_ED_SW_CLK_OUT0	R/W	0h	This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set
29	PRU0_ED_CLK_OUT_OVR_EN0	R/W	0h	When set, this gives the software the ability to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation.
28	PRU0_ED_RX_SNOOP0	R	0h	Direct Read of pru<n>_ endat<m>_in state
27-16	PRU0_ED_RX_FRAME_SIZE0	R/W	0h	RX frame size, after SB is detected 0h = Special case for TX only phase, ignores SB, in this case tx_clk out will stop after last TX 1h = tx_clk out will stop after 1 X Over Sample 8 = tx_clk out will stop after 8 X Over Sample 9 = tx_clk out will stop after 9 X Over Sample . . 4095 tx_clk out will stop after 2047 X Over Sample Note: X Over Sample means the number of VAL events 1 VAL per Over Sample event When the TX CLOCK MODE is either 00 or 01, when this rx frame size is reached the tx controller clock out will remain high or low RULE: The software should not de-assert rx_en before rx_frame_size expires
15-11	PRU0_ED_TX_FRAME_SIZE0	R/W	0h	TX frame size 0h = disabled, the FIFO will transmit until empty then stop 1h = TX FIFO will transmit 1 bits then stop 2h = TX FIFO will transmit 2 bits then stop 8 = TX FIFO will transmit 8 bits then stop 9 = TX FIFO will transmit 9 bits then stop . . 31h = TX FIFO will transmit 31 bits then stop Note: when TX stop. Then endat<n>_out_en will de-assert
10-0	PRU0_ED_TX_WDLY0	R/W	0h	EnDAT TX wire delay using 200 MHz steps (CORE clock). Software should program a number divisible by 5. (Hw) 0h = no delay 5h = 5 ns delay Ah = 10 ns delay Fh = 15 ns delay 7FDh = 2.045 us delay This is used during TX state when CLK_OUT goes from high to low, this transmission can be compensated Hardware will keep count of clocks and add 5 each time. Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.55 ICSSG_PRU0_ED_CH0_CFG1_REG Register (Offset = ECh) [reset = 0h]

ICSSG_PRU0_ED_CH0_CFG1_REG is shown in Figure 6-350 and described in Table 6-677.

Return to Summary Table.

PRU0 ED Channel 0 Configuration 1 Register

Table 6-676 ICSSG_PRU0_ED_CH0_CFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60ECh
PRU_ICSSG1_PR1_CFG_SLV	300A 60ECh

Figure 6-350 ICSSG_PRU0_ED_CH0_CFG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRU0_ED_RX_EN_COUNTER0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRU0_ED_TST_DELAY_COUNTER0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-677 ICSSG_PRU0_ED_CH0_CFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU0_ED_RX_EN_COUNTER0	R/W	0h	This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1). Program to 0 if hardware support is not required. Counts in CORE cycles. Software should program value in increments of 5 (hardware will count by 5 s) For example 30, will be 6 ICSSGn_CORE_CLK cycles All channels must be use this feature if enabled. The HW does not allow support of some channels with auto enable and others manual enable. They can have different values , but all must be 0h or all none 0h
15-0	PRU0_ED_TST_DELAY_COUNTER0	R/W	0h	This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5. For example 30, will be 6 ICSSGn_CORE_CLK cycles Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.56 ICSSG_PRU0_ED_CH1_CFG0_REG Register (Offset = F0h) [reset = 0h]

ICSSG_PRU0_ED_CH1_CFG0_REG is shown in Figure 6-351 and described in Table 6-679.

Return to Summary Table.

PRU0 ED Channel 1 Configuration 0 Register

Table 6-678 ICSSG_PRU0_ED_CH1_CFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60F0h
PRU_ICSSG1_PR1_CFG_SLV	300A 60F0h

Figure 6-351 ICSSG_PRU0_ED_CH1_CFG0_REG Register

31	30	29	28	27	26	25	24
PRU0_ED_TX_FIFO_SWAP_BITS1	PRU0_ED_SW_CLK_OUT1	PRU0_ED_CLK_OUT_OVR_EN1	PRU0_ED_RX_SNOOP1	PRU0_ED_RX_FRAME_SIZE1
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU0_ED_RX_FRAME_SIZE1
R/W-0h

15	14	13	12	11	10	9	8
PRU0_ED_TX_FRAME_SIZE1					PRU0_ED_TX_WDLY1
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_ED_TX_WDLY1
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-679 ICSSG_PRU0_ED_CH1_CFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRU0_ED_TX_FIFO_SWAP_BITS1	R/W	0h	This enables the swapping of the bits when they are loaded into the TX FIFO. 0h = no swap [7:0] -> [7:0] 1h = swap [7:0] -> [0:7]
30	PRU0_ED_SW_CLK_OUT1	R/W	0h	This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set
29	PRU0_ED_CLK_OUT_OVR_EN1	R/W	0h	When set, this gives the software the abilty to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation.
28	PRU0_ED_RX_SNOOP1	R	0h	Direct Read of pru<n>_ endat<m>_in state
27-16	PRU0_ED_RX_FRAME_SIZE1	R/W	0h	RX frame size, after SB is detected 0 = Special case for TX only phase, ignores SB, in this case tx_clk out will stop after last TX 1 = tx_clk out will stop after 1 X Over Sample 8 = tx_clk out will stop after 8 X Over Sample 9 = tx_clk out will stop after 9 X Over Sample . . 4095 tx_clk out will stop after 2047 X Over Sample Note: X Over Sample means the number of VAL events 1 VAL per Over Sample event When the TX CLOCK MODE is either 00 or 01, when this rx frame size is reached the tx controller clock out will remain high or low RULE: The software should not de-assert rx_en before rx_frame_size expires
15-11	PRU0_ED_TX_FRAME_SIZE1	R/W	0h	TX frame size 0h = disabled, the FIFO will transmit until empty then stop 1h = TX FIFO will transmit 1 bits then stop 2h = TX FIFO will transmit 2 bits then stop 8h = TX FIFO will transmit 8 bits then stop 9h = TX FIFO will transmit 9 bits then stop . . 31h = TX FIFO will transmit 31 bits then stop Note: when TX stop. Then endat<n>_out_en will de-assert
10-0	PRU0_ED_TX_WDLY1	R/W	0h	EnDAT TX wire delay using 200 MHz steps (CORE clock). Software should program a number divisible by 5. (Hw) 0h = no delay 5h = 5 ns delay Ah = 10 ns delay Fh = 15 ns delay 7FDh = 2.045 us delay This is used during TX state when CLK_OUT goes from high to low, this transmission can be compensated Hardware will keep count of clocks and add 5 each time. Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.57 ICSSG_PRU0_ED_CH1_CFG1_REG Register (Offset = F4h) [reset = 0h]

ICSSG_PRU0_ED_CH1_CFG1_REG is shown in Figure 6-352 and described in Table 6-681.

Return to Summary Table.

PRU0 ED Channel 1 Configuration 1 Register

Table 6-680 ICSSG_PRU0_ED_CH1_CFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60F4h
PRU_ICSSG1_PR1_CFG_SLV	300A 60F4h

Figure 6-352 ICSSG_PRU0_ED_CH1_CFG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRU0_ED_RX_EN_COUNTER1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRU0_ED_TST_DELAY_COUNTER1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-681 ICSSG_PRU0_ED_CH1_CFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU0_ED_RX_EN_COUNTER1	R/W	0h	This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1). Program to 0 if hardware support is not required. Counts in CORE cycles. Software should program value in increments of 5 (hardware will count by 5 s) For example 30, will be 6 ICSSGn_CORE_CLK cycles All channels must be use this feature if enabled. The HW does not allow support of some channels with auto enable and others manual enable. They can have different values , but all must be 0h or all none 0h
15-0	PRU0_ED_TST_DELAY_COUNTER1	R/W	0h	This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5. For example 30, will be 6 ICSSGn_CORE_CLK cycles Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.58 ICSSG_PRU0_ED_CH2_CFG0_REG Register (Offset = F8h) [reset = 0h]

ICSSG_PRU0_ED_CH2_CFG0_REG is shown in Figure 6-353 and described in Table 6-683.

Return to Summary Table.

PRU0 ED Channel 2 Configuration 0 Register

Table 6-682 ICSSG_PRU0_ED_CH2_CFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60F8h
PRU_ICSSG1_PR1_CFG_SLV	300A 60F8h

Figure 6-353 ICSSG_PRU0_ED_CH2_CFG0_REG Register

31	30	29	28	27	26	25	24
PRU0_ED_TX_FIFO_SWAP_BITS2	PRU0_ED_SW_CLK_OUT2	PRU0_ED_CLK_OUT_OVR_EN2	PRU0_ED_RX_SNOOP2	PRU0_ED_RX_FRAME_SIZE2
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU0_ED_RX_FRAME_SIZE2
R/W-0h

15	14	13	12	11	10	9	8
PRU0_ED_TX_FRAME_SIZE2					PRU0_ED_TX_WDLY2
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU0_ED_TX_WDLY2
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-683 ICSSG_PRU0_ED_CH2_CFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRU0_ED_TX_FIFO_SWAP_BITS2	R/W	0h	This enables the swapping of the bits when they are loaded into the TX FIFO. 0h = no swap [7:0] -> [7:0] 1h = swap [7:0] -> [0:7]
30	PRU0_ED_SW_CLK_OUT2	R/W	0h	This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set
29	PRU0_ED_CLK_OUT_OVR_EN2	R/W	0h	When set, this gives the software the ability to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation.
28	PRU0_ED_RX_SNOOP2	R	0h	Direct Read of pru<n>_ endat<m>_in state
27-16	PRU0_ED_RX_FRAME_SIZE2	R/W	0h	RX frame size, after SB is detected 0 = Special case for TX only phase, ignores SB, in this case tx_clk out will stop after last TX 1 = tx_clk out will stop after 1 X Over Sample 8 = tx_clk out will stop after 8 X Over Sample 9 = tx_clk out will stop after 9 X Over Sample . . 4095 tx_clk out will stop after 2047 X Over Sample Note: X Over Sample means the number of VAL events 1 VAL per Over Sample event When the TX CLOCK MODE is either 00 or 01, when this rx frame size is reached the tx controller clock out will remain high or low RULE: The software should not de-assert rx_en before rx_frame_size expires
15-11	PRU0_ED_TX_FRAME_SIZE2	R/W	0h	TX frame size 0h = disabled, the FIFO will transmit until empty then stop 1h = TX FIFO will transmit 1 bits then stop 2h = TX FIFO will transmit 2 bits then stop 8h = TX FIFO will transmit 8 bits then stop 9h = TX FIFO will transmit 9 bits then stop . . 31h = TX FIFO will transmit 31 bits then stop Note: when TX stop. Then endat<n>_out_en will de-assert
10-0	PRU0_ED_TX_WDLY2	R/W	0h	EnDAT TX wire delay using 200 MHz steps (CORE clock). Software should program a number divisible by 5. (Hw) 0h = no delay 5h = 5 ns delay Ah = 10 ns delay Fh = 15 ns delay 7FDh = 2.045 us delay This is used during TX state when CLK_OUT goes from high to low, this transmission can be compensated Hardware will keep count of clocks and add 5 each time. Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.59 ICSSG_PRU0_ED_CH2_CFG1_REG Register (Offset = FCh) [reset = 0h]

ICSSG_PRU0_ED_CH2_CFG1_REG is shown in Figure 6-354 and described in Table 6-685.

Return to Summary Table.

PRU0 ED Channel 2 Configuration 1 Register

Table 6-684 ICSSG_PRU0_ED_CH2_CFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 60FCh
PRU_ICSSG1_PR1_CFG_SLV	300A 60FCh

Figure 6-354 ICSSG_PRU0_ED_CH2_CFG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRU0_ED_RX_EN_COUNTER2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRU0_ED_TST_DELAY_COUNTER2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-685 ICSSG_PRU0_ED_CH2_CFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU0_ED_RX_EN_COUNTER2	R/W	0h	This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1). Program to 0 if hardware support is not required. Counts in CORE cycles. Software should program value in increments of 5 (hardware will count by 5s) For example 30, will be 6 ICSSGn_CORE_CLK cycles All channels must be use this feature if enabled. The HW does not allow support of some channels with auto enable and others manual enable. They can have different values , but all must be 0h or all none 0h
15-0	PRU0_ED_TST_DELAY_COUNTER2	R/W	0h	This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5. For example 30, will be 6 ICSSGn_CORE_CLK cycles Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.60 ICSSG_PRU1_ED_RX_CFG_REG Register (Offset = 100h) [reset = X]

ICSSG_PRU1_ED_RX_CFG_REG is shown in Figure 6-355 and described in Table 6-687.

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PRU1 ED Receive Global Configuration Register.

Table 6-686 ICSSG_PRU1_ED_RX_CFG_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6100h
PRU_ICSSG1_PR1_CFG_SLV	300A 6100h

Figure 6-355 ICSSG_PRU1_ED_RX_CFG_REG Register

31	30	29	28	27	26	25	24
PRU1_ED_RX_DIV_FACTOR
R/W-0h

23	22	21	20	19	18	17	16
PRU1_ED_RX_DIV_FACTOR
R/W-0h

15	14	13	12	11	10	9	8
PRU1_ED_RX_DIV_FACTOR_FRAC	RESERVED
R/W-0h	R/W-X

7	6	5	4	3	2	1	0
RESERVED			PRU1_ED_RX_CLK_SEL	PRU1_ED_RX_SB_POL	PRU1_ED_RX_SAMPLE_SIZE
R/W-X			R/W-0h	R/W-1h	R/W-7h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-687 ICSSG_PRU1_ED_RX_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU1_ED_RX_DIV_FACTOR	R/W	0h	div factor for divh16 0h = div 1 1h = div 2 Nh = div (N+1) This divh16 is post divfrac, the effective rate will be Effective rate is 1.5 X main div if frac enabled Effective rate is 1.0 X main div if frac disabled For example , divh16 set to 3h Div by 6 if frac enabled Div by 4 if frac enabled For example , divh16 set to 4 Div by 7.5 if frac enabled Div by 5 if frac enabled
15	PRU1_ED_RX_DIV_FACTOR_FRAC	R/W	0h	Enable Fractional division before the divh16 0h = div 1 1h = div 1.5
14-5	RESERVED	R/W	X
4	PRU1_ED_RX_CLK_SEL	R/W	0h	Selects the clock source for the divh16fr 0h = 192 MHz, the uart_clk 1h = 200 MHz, the ICSSGn_CORE_CLK
3	PRU1_ED_RX_SB_POL	R/W	1h	Defines the polarity of the RX Start Bit 0h = 0 1h = 1 Reset/default state
2-0	PRU1_ED_RX_SAMPLE_SIZE	R/W	7h	Over Sample size This defines the number of samples before the shadow copy gets updated and the VAL flag gets set The effect count is (sample_size + 1) 0h = Reserved 1h = Reserved 2h = Reserved 3h = Over Sample of 4 4h = Over Sample of 5 5h = Over Sample of 6 6h = Over Sample of 7 7h = Over Sample of 8 Note: the Over Sample Clock rate divided by the 1x Clock rate must equal the Over Sample size.

4.14.5.61 ICSSG_PRU1_ED_TX_CFG_REG Register (Offset = 104h) [reset = X]

ICSSG_PRU1_ED_TX_CFG_REG is shown in Figure 6-356 and described in Table 6-689.

Return to Summary Table.

PRU1 ED Transmit Global Configuration Register.

Table 6-688 ICSSG_PRU1_ED_TX_CFG_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6104h
PRU_ICSSG1_PR1_CFG_SLV	300A 6104h

Figure 6-356 ICSSG_PRU1_ED_TX_CFG_REG Register

31	30	29	28	27	26	25	24
PRU01_ED_TX_DIV_FACTOR
R/W-0h

23	22	21	20	19	18	17	16
PRU01_ED_TX_DIV_FACTOR
R/W-0h

15	14	13	12	11	10	9	8
PRU1_ED_TX_DIV_FACTOR_FRAC	RESERVED			SHARE_EN	PRU1_ENDAT2_CLK_SYNC	PRU1_ENDAT1_CLK_SYNC	PRU1_ENDAT0_CLK_SYNC
R/W-0h	R/W-X			R/W-0h	R-1h	R-1h	R-1h

7	6	5	4	3	2	1	0
PRU1_ED_BUSY_2	PRU1_ED_BUSY_1	PRU1_ED_BUSY_0	PRU1_ED_TX_CLK_SEL	RESERVED
R-0h	R-0h	R-0h	R/W-0h	R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-689 ICSSG_PRU1_ED_TX_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU1_ED_TX_DIV_FACTOR	R/W	0h	Div factor for divh16 0h = div 1 1h = div 2 Nh = div (N+1) This divh16 is post divfrac, the effective rate will be Effective rate is 1.5 X main div if frac enabled Effective rate is 1.0 X main div if frac disabled For example , divh16 set to 3h Div by 6 if frac enabled Div by 4 if frac enabled For example , divh16 set to 4 Div by 7.5 if frac enabled Div by 5 if frac enabled
15	PRU1_ED_TX_DIV_FACTOR_FRAC	R/W	0h	Enable Fractional division before the divh16 0h = div 1 1h = div 1.5
14-11	RESERVED	R/W	X
14-12	RESERVED	R/W	X
11	SHARE_EN	R/W	0h	Load Share Enable 0 PRU owns ED0/ED1/ED2 1 RTU owns ED0, PRU owns ED1, and TS_PRU owns ED2
10	PRU1_ENDAT2_CLK_SYNC	R	1h	Observation of pru<n>_endat2_clk pin state
9	PRU1_ENDAT1_CLK_SYNC	R	1h	Observation of pru<n>_endat1_clk pin state
8	PRU1_ENDAT0_CLK_SYNC	R	1h	Observation of pru<n>_endat0_clk pin state
7	PRU1_ED_BUSY_2	R	0h	Determines when you can assert tx go for channel 2 0h = Not busy ready to go 1h = Busy not ready to go Can be used to determine when it issue a new TX frame
6	PRU1_ED_BUSY_1	R	0h	Determines when you can assert tx go for channel 1 0h = Not busy ready to go 1h = Busy not ready to go Can be used to determine when it issue a new TX frame
5	PRU1_ED_BUSY_0	R	0h	Determines when you can assert tx go for channel 0 0h = Not busy ready to go 1h = Busy not ready to go Can be used to determine when it issue a new TX frame
4	PRU1_ED_TX_CLK_SEL	R/W	0h	Selects the clock source for the divh16fr 0h = 192 MHz, the uart_clk 1h = 200 MHz, the ICSSGn_CORE_CLK
3-0	RESERVED	R/W	X

4.14.5.62 ICSSG_PRU1_ED_CH0_CFG0_REG Register (Offset = 108h) [reset = 0h]

ICSSG_PRU1_ED_CH0_CFG0_REG is shown in Figure 6-357 and described in Table 6-691.

Return to Summary Table.

PRU1 ED Channel 0 Configuration 0 Register.

Table 6-690 ICSSG_PRU1_ED_CH0_CFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6108h
PRU_ICSSG1_PR1_CFG_SLV	300A 6108h

Figure 6-357 ICSSG_PRU1_ED_CH0_CFG0_REG Register

31	30	29	28	27	26	25	24
PRU1_ED_TX_FIFO_SWAP_BITS0	PRU1_ED_SW_CLK_OUT0	PRU1_ED_CLK_OUT_OVR_EN0	PRU1_ED_RX_SNOOP0	PRU1_ED_RX_FRAME_SIZE0
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU1_ED_RX_FRAME_SIZE0
R/W-0h

15	14	13	12	11	10	9	8
PRU1_ED_TX_FRAME_SIZE0					PRU1_ED_TX_WDLY0
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_ED_TX_WDLY0
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-691 ICSSG_PRU1_ED_CH0_CFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRU1_ED_TX_FIFO_SWAP_BITS0	R/W	0h	This enables the swapping of the bits when they are loaded into the TX FIFO. 0h = no swap [7:0] -> [7:0] 1h = swap [7:0] -> [0:7]
30	PRU1_ED_SW_CLK_OUT0	R/W	0h	This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set
29	PRU1_ED_CLK_OUT_OVR_EN0	R/W	0h	When set, this gives the software the ability to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation.
28	PRU1_ED_RX_SNOOP0	R	0h	Direct Read of pru<n>_ endat<m>_in state
27-16	PRU1_ED_RX_FRAME_SIZE0	R/W	0h	RX frame size, after SB is detected 0h = Special case for TX only phase, ignores SB, in this case tx_clk out will stop after last TX 1h = tx_clk out will stop after 1 X Over Sample 8 = tx_clk out will stop after 8 X Over Sample 9 = tx_clk out will stop after 9 X Over Sample . . 4095 tx_clk out will stop after 4095 X Over Sample Note: X Over Sample means the number of VAL events 1 VAL per Over Sample event When the TX CLOCK MODE is either 00 or 01, when this rx frame size is reached the tx controller clock out will remain high or low RULE: The software should not de-assert rx_en before rx_frame_size expires
15-11	PRU1_ED_TX_FRAME_SIZE0	R/W	0h	TX frame size 0h = disabled, the FIFO will transmit until empty then stop 1h = TX FIFO will transmit 1 bits then stop 2h = TX FIFO will transmit 2 bits then stop 8 = TX FIFO will transmit 8 bits then stop 9 = TX FIFO will transmit 9 bits then stop . . 31h = TX FIFO will transmit 31 bits then stop Note: when TX stop. Then endat<n>_out_en will de-assert
10-0	PRU1_ED_TX_WDLY0	R/W	0h	EnDAT TX wire delay using 200 MHz steps (CORE clock). Software should program a number divisible by 5. (Hw) 0h = no delay 5h = 5 ns delay Ah = 10 ns delay Fh = 15 ns delay 7FDh = 2.045 us delay This is used during TX state when CLK_OUT goes from high to low, this transmission can be compensated Hardware will keep count of clocks and add 5 each time. Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.63 ICSSG_PRU1_ED_CH0_CFG1_REG Register (Offset = 10Ch) [reset = 0h]

ICSSG_PRU1_ED_CH0_CFG1_REG is shown in Figure 6-358 and described in Table 6-693.

Return to Summary Table.

PRU1 ED Channel 0 Configuration 1 Register.

Table 6-692 ICSSG_PRU1_ED_CH0_CFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 610Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 610Ch

Figure 6-358 ICSSG_PRU1_ED_CH0_CFG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRU1_ED_RX_EN_COUNTER0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRU1_ED_TST_DELAY_COUNTER0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-693 ICSSG_PRU1_ED_CH0_CFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU1_ED_RX_EN_COUNTER0	R/W	0h	This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1). Program to 0h if hardware support is not required. Counts in CORE cycles. Software should program value in increments of 5 (hardware will count by 5 s) For example 30, will be 6 ICSSGn_CORE_CLK cycles All channels must use this feature if enabled. The HW does not allow support of some channels with auto enable and others manual enable. They can have different values , but all must be 0h or all none 0h
15-0	PRU1_ED_TST_DELAY_COUNTER0	R/W	0h	This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5. For example 30, will be 6 ICSSGn_CORE_CLK cycles Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.64 ICSSG_PRU1_ED_CH1_CFG0_REG Register (Offset = 110h) [reset = 0h]

ICSSG_PRU1_ED_CH1_CFG0_REG is shown in Figure 6-359 and described in Table 6-695.

Return to Summary Table.

PRU1 ED Channel 1 Configuration 0 Register.

Table 6-694 ICSSG_PRU1_ED_CH1_CFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6110h
PRU_ICSSG1_PR1_CFG_SLV	300A 6110h

Figure 6-359 ICSSG_PRU1_ED_CH1_CFG0_REG Register

31	30	29	28	27	26	25	24
PRU1_ED_TX_FIFO_SWAP_BITS1	PRU1_ED_SW_CLK_OUT1	PRU1_ED_CLK_OUT_OVR_EN1	PRU1_ED_RX_SNOOP1	PRU1_ED_RX_FRAME_SIZE1
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU1_ED_RX_FRAME_SIZE1
R/W-0h

15	14	13	12	11	10	9	8
PRU1_ED_TX_FRAME_SIZE1					PRU1_ED_TX_WDLY1
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_ED_TX_WDLY1
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-695 ICSSG_PRU1_ED_CH1_CFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRU1_ED_TX_FIFO_SWAP_BITS1	R/W	0h	This enables the swapping of the bits when they are loaded into the TX FIFO. 0h = no swap [7:0] -> [7:0] 1h = swap [7:0] -> [0:7]
30	PRU1_ED_SW_CLK_OUT1	R/W	0h	This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set
29	PRU1_ED_CLK_OUT_OVR_EN1	R/W	0h	When set, this gives the software the ability to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation.
28	PRU1_ED_RX_SNOOP1	R	0h	Direct Read of pru<n>_ endat<m>_in state
27-16	PRU1_ED_RX_FRAME_SIZE1	R/W	0h	RX frame size, after SB is detected 0h = Special case for TX only phase, ignores SB, in this case tx_clk out will stop after last TX 1 = tx_clk out will stop after 1 X Over Sample 8 = tx_clk out will stop after 8 X Over Sample 9 = tx_clk out will stop after 9 X Over Sample . . 4095 tx_clk out will stop after 2047 X Over Sample Note: X Over Sample means the number of VAL events 1 VAL per Over Sample event When the TX CLOCK MODE is either 00 or 01, when this rx frame size is reached the tx controller clock out will remain high or low RULE: The software should not de-assert rx_en before rx_frame_size expires
15-11	PRU1_ED_TX_FRAME_SIZE1	R/W	0h	TX frame size 0h = disabled, the FIFO will transmit until empty then stop 1h = TX FIFO will transmit 1 bits then stop 2h = TX FIFO will transmit 2 bits then stop 8h = TX FIFO will transmit 8 bits then stop 9h = TX FIFO will transmit 9 bits then stop . . 31h = TX FIFO will transmit 31 bits then stop Note: when TX stop. Then endat<n>_out_en will de-assert
10-0	PRU1_ED_TX_WDLY1	R/W	0h	EnDAT TX wire delay using 200 MHz steps (CORE clock). Software should program a number divisible by 5. (Hw) 0h = no delay 5h = 5 ns delay Ah = 10 ns delay Fh = 15 ns delay 7FDh = 2.045 us delay This is used during TX state when CLK_OUT goes from high to low, this transmission can be compensated Hardware will keep count of clocks and add 5 each time. Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.65 ICSSG_PRU1_ED_CH1_CFG1_REG Register (Offset = 114h) [reset = 0h]

ICSSG_PRU1_ED_CH1_CFG1_REG is shown in Figure 6-360 and described in Table 6-697.

Return to Summary Table.

PRU1 ED Channel 1 Configuration 1 Register.

Table 6-696 ICSSG_PRU1_ED_CH1_CFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6114h
PRU_ICSSG1_PR1_CFG_SLV	300A 6114h

Figure 6-360 ICSSG_PRU1_ED_CH1_CFG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRU1_ED_RX_EN_COUNTER1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRU1_ED_TST_DELAY_COUNTER1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-697 ICSSG_PRU1_ED_CH1_CFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU1_ED_RX_EN_COUNTER1	R/W	0h	This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1). Program to 0 if hardware support is not required. Counts in CORE cycles. Software should program value in increments of 5 (hardware will count by 5s) For example 30, will be 6 ICSSGn_CORE_CLK cycles All channels must use this feature if enabled. The HW does not allow support of some channels with auto enable and others manual enable. They can have different values , but all must be 0h or all none 0h
15-0	PRU1_ED_TST_DELAY_COUNTER1	R/W	0h	This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5. For example 30, will be 6 ICSSGn_CORE_CLK cycles Note the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.66 ICSSG_PRU1_ED_CH2_CFG0_REG Register (Offset = 118h) [reset = 0h]

ICSSG_PRU1_ED_CH2_CFG0_REG is shown in Figure 6-361 and described in Table 6-699.

Return to Summary Table.

PRU1 ED Channel 2 Configuration 0 Register.

Table 6-698 ICSSG_PRU1_ED_CH2_CFG0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6118h
PRU_ICSSG1_PR1_CFG_SLV	300A 6118h

Figure 6-361 ICSSG_PRU1_ED_CH2_CFG0_REG Register

31	30	29	28	27	26	25	24
PRU1_ED_TX_FIFO_SWAP_BITS2	PRU1_ED_SW_CLK_OUT2	PRU1_ED_CLK_OUT_OVR_EN2	PRU1_ED_RX_SNOOP2	PRU1_ED_RX_FRAME_SIZE2
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
PRU1_ED_RX_FRAME_SIZE2
R/W-0h

15	14	13	12	11	10	9	8
PRU1_ED_TX_FRAME_SIZE2					PRU1_ED_TX_WDLY2
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
PRU1_ED_TX_WDLY2
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-699 ICSSG_PRU1_ED_CH2_CFG0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRU1_ED_TX_FIFO_SWAP_BITS2	R/W	0h	This enables the swapping of the bits when they are loaded into the TX FIFO. 0h = no swap [7:0] -> [7:0] 1h = swap [7:0] -> [0:7]
30	PRU1_ED_SW_CLK_OUT2	R/W	0h	This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set
29	PRU1_ED_CLK_OUT_OVR_EN2	R/W	0h	When set, this gives the software the ability to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation.
28	PRU1_ED_RX_SNOOP2	R	0h	Direct Read of pru<n>_ endat<m>_in state
27-16	PRU1_ED_RX_FRAME_SIZE2	R/W	0h	RX frame size, after SB is detected 0h = Special case for TX only phase, ignores SB, in this case tx_clk out will stop after last TX 1 = tx_clk out will stop after 1 X Over Sample 8 = tx_clk out will stop after 8 X Over Sample 9 = tx_clk out will stop after 9 X Over Sample . . 4095 tx_clk out will stop after 2047 X Over Sample Note: X Over Sample means the number of VAL events 1 VAL per Over Sample event When the TX CLOCK MODE is either 00 or 01, when this rx frame size is reached the tx controller clock out will remain high or low RULE: The software should not de-assert rx_en before rx_frame_size expires
15-11	PRU1_ED_TX_FRAME_SIZE2	R/W	0h	TX frame size 0h = disabled, the FIFO will transmit until empty then stop 1h = TX FIFO will transmit 1 bits then stop 2h = TX FIFO will transmit 2 bits then stop 8h = TX FIFO will transmit 8 bits then stop 9h = TX FIFO will transmit 9 bits then stop . . 31h = TX FIFO will transmit 31 bits then stop Note: when TX stop. Then endat<n>_out_en will de-assert
10-0	PRU1_ED_TX_WDLY2	R/W	0h	EnDAT TX wire delay using 200 MHz steps (CORE clock). Software should program a number divisible by 5. (Hw) 0h = no delay 5h = 5 ns delay Ah = 10 ns delay Fh = 15 ns delay 7FDh = 2.045 us delay This is used during TX state when CLK_OUT goes from high to low, this transmission can be compensated Hardware will keep count of clocks and add 5 each time. Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.67 ICSSG_PRU1_ED_CH2_CFG1_REG Register (Offset = 11Ch) [reset = 0h]

ICSSG_PRU1_ED_CH2_CFG1_REG is shown in Figure 6-362 and described in Table 6-701.

Return to Summary Table.

PRU1 ED Channel 2 Configuration 1 Register.

Table 6-700 ICSSG_PRU1_ED_CH2_CFG1_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 611Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 611Ch

Figure 6-362 ICSSG_PRU1_ED_CH2_CFG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRU1_ED_RX_EN_COUNTER2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRU1_ED_TST_DELAY_COUNTER2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-701 ICSSG_PRU1_ED_CH2_CFG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PRU1_ED_RX_EN_COUNTER2	R/W	0h	This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1). Program to 0 if hardware support is no required. Counts in CORE cycles. Software should program value in increments of 5 (hardware will count by 5 s) For example 30, will be 6 ICSSGn_CORE_CLK cycles All channels must use this feature if enabled. The HW does not allow support of some channels with auto enable and others manual enable. They can have different values , but all must be 0h or all none 0h
15-0	PRU1_ED_TST_DELAY_COUNTER2	R/W	0h	This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5. For example 30, will be 6 ICSSGn_CORE_CLK cycles Note: the first rising edge of EnDAT CLK from a TX GO event is ED_TX_WDLY + ED_TST_DELAY_COUNTER + ½ EnDAT CLK period +/- 15 ns

4.14.5.68 ICSSG_RTU0_POKE_EN0_REG Register (Offset = 124h) [reset = 0h]

ICSSG_RTU0_POKE_EN0_REG is shown in Figure 6-363 and described in Table 6-703.

Return to Summary Table.

RTU0 Poke Enable 0 Register.

Table 6-702 ICSSG_RTU0_POKE_EN0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6124h
PRU_ICSSG1_PR1_CFG_SLV	300A 6124h

Figure 6-363 ICSSG_RTU0_POKE_EN0_REG Register

31	30	29	28	27	26	25	24
RTU0_POKE_R27_EN				RTU0_POKE_R26_EN
R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
RTU0_POKE_R25_EN				RTU0_POKE_R24_EN
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
RTU0_POKE_R23_EN				RTU0_POKE_R22_EN
R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
RTU0_POKE_R21_EN				RTU0_POKE_R20_EN
R/W-0h				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-703 ICSSG_RTU0_POKE_EN0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RTU0_POKE_R27_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
27-24	RTU0_POKE_R26_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
23-20	RTU0_POKE_R25_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
19-16	RTU0_POKE_R24_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
15-12	RTU0_POKE_R23_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
11-8	RTU0_POKE_R22_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
7-4	RTU0_POKE_R21_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
3-0	RTU0_POKE_R20_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte

4.14.5.69 ICSSG_RTU1_POKE_EN0_REG Register (Offset = 12Ch) [reset = 0h]

ICSSG_RTU1_POKE_EN0_REG is shown in Figure 6-364 and described in Table 6-705.

Return to Summary Table.

RTU1 Poke Enable 0 Register.

Table 6-704 ICSSG_RTU1_POKE_EN0_REG Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 612Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 612Ch

Figure 6-364 ICSSG_RTU1_POKE_EN0_REG Register

31	30	29	28	27	26	25	24
RTU1_POKE_R27_EN				RTU1_POKE_R26_EN
R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
RTU1_POKE_R25_EN				RTU1_POKE_R24_EN
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
RTU1_POKE_R23_EN				RTU1_POKE_R22_EN
R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
RTU1_POKE_R21_EN				RTU1_POKE_R20_EN
R/W-0h				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-705 ICSSG_RTU1_POKE_EN0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RTU1_POKE_R27_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
27-24	RTU1_POKE_R26_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
23-20	RTU1_POKE_R25_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
19-16	RTU1_POKE_R24_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
15-12	RTU1_POKE_R23_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
11-8	RTU1_POKE_R22_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
7-4	RTU1_POKE_R21_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte
3-0	RTU1_POKE_R20_EN	R/W	0h	This enables the external values to get poked into PRU’s internal register [x] = 0 Disable poke for that byte [x] = 1 Enable poke for that byte

4.14.5.70 ICSSG_PWM0 Register (Offset = 130h) [reset = X]

ICSSG_PWM0 is shown in Figure 6-365 and described in Table 6-707.

Return to Summary Table.

PWM0 Trip Configuration Register.

Table 6-706 ICSSG_PWM0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6130h
PRU_ICSSG1_PR1_CFG_SLV	300A 6130h

Figure 6-365 ICSSG_PWM0 Register

31	30	29	28	27	26	25	24
RESERVED	PWM0_TRIP_S	PWM0_TRIP_VEC
R/W-X	R/W-0h	R-0h

23	22	21	20	19	18	17	16
PWM0_TRIP_VEC			PWM0_POS_ERR_TRIP	PWM0_OVER_ERR_TRIP	PWM0_TRIP_RESET	PWM0_TRIP_CMP0_EN	PWM0_TRIP_MASK
R-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
PWM0_TRIP_MASK
R/W-0h

7	6	5	4	3	2	1	0
PWM0_DEBOUNCE_VALUE
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-707 ICSSG_PWM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30	PWM0_TRIP_S	R/W	0h	Trip status. Cleared by trip reset.
29-21	PWM0_TRIP_VEC	R	0h	Trip trigger cause vector. Cleared by trip reset. 0h: PWM0_POS_ERR_TRIP (trip_e5) 1h: PWM0_OVER_ERR_TRIP (trip_e4) 2h: PWM0_0_SD_SHORT_ERR_TRIP (trip_e3_0) 3h: PWM0_1_SD_SHORT_ERR_TRIP (trip_e3_1) 4h: PWM0_2_SD_SHORT_ERR_TRIP (trip_e3_2) 5h: PWM0_DEBOUNCE_TRIP_IN (trip_e2) 6h: PWM0_0_DEBOUNCE_TRIP (trip_e1_0) 7h: PWM0_1_DEBOUNCE_TRIP (trip_e1_1) 8h: PWM0_2_DEBOUNCE_TRIP (trip_e1_2)
20	PWM0_POS_ERR_TRIP	R/W	0h	Software position feedback error trip
19	PWM0_OVER_ERR_TRIP	R/W	0h	Software overcurrent error trip
18	PWM0_TRIP_RESET	R/W	0h	Software trip reset
17	PWM0_TRIP_CMP0_EN	R/W	0h	CMP0 reset trip clear enable
16-8	PWM0_TRIP_MASK	R/W	0h	Software mask for trip, one hot
7-0	PWM0_DEBOUNCE_VALUE	R/W	0h	Debounce counter , defines the number of core_clk required for the pulse not to get rejected

4.14.5.71 ICSSG_PWM1 Register (Offset = 134h) [reset = X]

ICSSG_PWM1 is shown in Figure 6-366 and described in Table 6-709.

Return to Summary Table.

PWM1 Trip Configuration Register.

Table 6-708 ICSSG_PWM1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6134h
PRU_ICSSG1_PR1_CFG_SLV	300A 6134h

Figure 6-366 ICSSG_PWM1 Register

31	30	29	28	27	26	25	24
RESERVED	PWM1_TRIP_S	PWM1_TRIP_VEC
R/W-X	R/W-0h	R-0h

23	22	21	20	19	18	17	16
PWM1_TRIP_VEC			PWM1_POS_ERR_TRIP	PWM1_OVER_ERR_TRIP	PWM1_TRIP_RESET	PWM1_TRIP_CMP0_EN	PWM1_TRIP_MASK
R-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
PWM1_TRIP_MASK
R/W-0h

7	6	5	4	3	2	1	0
PWM1_DEBOUNCE_VALUE
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-709 ICSSG_PWM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30	PWM1_TRIP_S	R/W	0h	Trip status. Cleared by trip reset.
29-21	PWM1_TRIP_VEC	R	0h	Trip trigger cause vector. Cleared by trip reset. 0h: PWM1_POS_ERR_TRIP (trip_e5) 1h: PWM1_OVER_ERR_TRIP (trip_e4) 2h: PWM1_0_SD_SHORT_ERR_TRIP (trip_e3_0) 3h: PWM1_1_SD_SHORT_ERR_TRIP (trip_e3_1) 4h: PWM1_2_SD_SHORT_ERR_TRIP (trip_e3_2) 5h: PWM1_DEBOUNCE_TRIP_IN (trip_e2) 6h: PWM1_0_DEBOUNCE_TRIP (trip_e1_0) 7h: PWM1_1_DEBOUNCE_TRIP (trip_e1_1) 8h: PWM1_2_DEBOUNCE_TRIP (trip_e1_2)
20	PWM1_POS_ERR_TRIP	R/W	0h	Software position feedback error trip
19	PWM1_OVER_ERR_TRIP	R/W	0h	Software overcurrent error trip
18	PWM1_TRIP_RESET	R/W	0h	Software trip reset
17	PWM1_TRIP_CMP0_EN	R/W	0h	CMP0 reset trip clear enable
16-8	PWM1_TRIP_MASK	R/W	0h	Software mask for trip, one hot
7-0	PWM1_DEBOUNCE_VALUE	R/W	0h	Debounce counter, defines the number of core_clk required for the pulse not to get rejected

4.14.5.72 ICSSG_PWM2 Register (Offset = 138h) [reset = X]

ICSSG_PWM2 is shown in Figure 6-367 and described in Table 6-711.

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PWM2 Trip Configuration Register.

Table 6-710 ICSSG_PWM2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6138h
PRU_ICSSG1_PR1_CFG_SLV	300A 6138h

Figure 6-367 ICSSG_PWM2 Register

31	30	29	28	27	26	25	24
RESERVED	PWM2_TRIP_S	PWM2_TRIP_VEC
R/W-X	R/W-0h	R-0h

23	22	21	20	19	18	17	16
PWM2_TRIP_VEC			PWM2_POS_ERR_TRIP	PWM2_OVER_ERR_TRIP	PWM2_TRIP_RESET	PWM2_TRIP_CMP0_EN	PWM2_TRIP_MASK
R-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
PWM2_TRIP_MASK
R/W-0h

7	6	5	4	3	2	1	0
PWM2_DEBOUNCE_VALUE
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-711 ICSSG_PWM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30	PWM2_TRIP_S	R/W	0h	Trip status. Cleared by trip reset.
29-21	PWM2_TRIP_VEC	R	0h	Trip trigger cause vector. Cleared by trip reset. 0h: PWM2_POS_ERR_TRIP (trip_e5) 1h: PWM2_OVER_ERR_TRIP (trip_e4) 2h: PWM2_0_SD_SHORT_ERR_TRIP (trip_e3_0) 3h: PWM2_1_SD_SHORT_ERR_TRIP (trip_e3_1) 4h: PWM2_2_SD_SHORT_ERR_TRIP (trip_e3_2) 5h: PWM2_DEBOUNCE_TRIP_IN (trip_e2) 6h: PWM2_0_DEBOUNCE_TRIP (trip_e1_0) 7h: PWM2_1_DEBOUNCE_TRIP (trip_e1_1) 8h: PWM2_2_DEBOUNCE_TRIP (trip_e1_2)
20	PWM2_POS_ERR_TRIP	R/W	0h	Software position feedback error trip
19	PWM2_OVER_ERR_TRIP	R/W	0h	Software overcurrent error trip
18	PWM2_TRIP_RESET	R/W	0h	Software trip reset
17	PWM2_TRIP_CMP0_EN	R/W	0h	CMP0 reset trip clear enable
16-8	PWM2_TRIP_MASK	R/W	0h	Software mask for trip, one hot
7-0	PWM2_DEBOUNCE_VALUE	R/W	0h	Debounce counter, defines the number of core_clk required for the pulse not to get rejected

4.14.5.73 ICSSG_PWM3 Register (Offset = 13Ch) [reset = X]

ICSSG_PWM3 is shown in Figure 6-368 and described in Table 6-713.

Return to Summary Table.

PWM3 Trip Configuration Register

Table 6-712 ICSSG_PWM3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 613Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 613Ch

Figure 6-368 ICSSG_PWM3 Register

31	30	29	28	27	26	25	24
RESERVED	PWM3_TRIP_S	PWM3_TRIP_VEC
R/W-X	R/W-0h	R-0h

23	22	21	20	19	18	17	16
PWM3_TRIP_VEC			PWM3_POS_ERR_TRIP	PWM3_OVER_ERR_TRIP	PWM3_TRIP_RESET	PWM3_TRIP_CMP0_EN	PWM3_TRIP_MASK
R-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
PWM3_TRIP_MASK
R/W-0h

7	6	5	4	3	2	1	0
PWM3_DEBOUNCE_VALUE
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-713 ICSSG_PWM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30	PWM3_TRIP_S	R/W	0h	Trip status.
29-21	PWM3_TRIP_VEC	R	0h	Trip trigger cause vector. Cleared by trip reset. 0h: PWM3_POS_ERR_TRIP (trip_e5) 1h: PWM3_OVER_ERR_TRIP (trip_e4) 2h: PWM3_0_SD_SHORT_ERR_TRIP (trip_e3_0) 3h: PWM3_1_SD_SHORT_ERR_TRIP (trip_e3_1) 4h: PWM3_2_SD_SHORT_ERR_TRIP (trip_e3_2) 5h: PWM3_DEBOUNCE_TRIP_IN (trip_e2) 6h: PWM3_0_DEBOUNCE_TRIP (trip_e1_0) 7h: PWM3_1_DEBOUNCE_TRIP (trip_e1_1) 8h: PWM3_2_DEBOUNCE_TRIP (trip_e1_2)
20	PWM3_POS_ERR_TRIP	R/W	0h	Software position feedback error trip
19	PWM3_OVER_ERR_TRIP	R/W	0h	Software overcurrent error trip
18	PWM3_TRIP_RESET	R/W	0h	Software trip reset
17	PWM3_TRIP_CMP0_EN	R/W	0h	CMP0 reset trip clear enable
16-8	PWM3_TRIP_MASK	R/W	0h	Software mask for trip, one hot
7-0	PWM3_DEBOUNCE_VALUE	R/W	0h	Debounce counter, defines the number of core_clk required for the pulse not to get rejected

4.14.5.74 ICSSG_PWM0_0 Register (Offset = 140h) [reset = X]

ICSSG_PWM0_0 is shown in Figure 6-369 and described in Table 6-715.

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PWM0 State Configuration 0 Register.

Table 6-714 ICSSG_PWM0_0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6140h
PRU_ICSSG1_PR1_CFG_SLV	300A 6140h

Figure 6-369 ICSSG_PWM0_0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM0_0_NEG_ACT		PWM0_0_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM0_0_NEG_TRIP		PWM0_0_POS_TRIP		PWM0_0_NEG_INIT		PWM0_0_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-715 ICSSG_PWM0_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM0_0_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM0_0_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM0_0_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM0_0_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM0_0_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM0_0_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.75 ICSSG_PWM0_1 Register (Offset = 144h) [reset = X]

ICSSG_PWM0_1 is shown in Figure 6-370 and described in Table 6-717.

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PWM0 State Configuration 1 Register.

Table 6-716 ICSSG_PWM0_1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6144h
PRU_ICSSG1_PR1_CFG_SLV	300A 6144h

Figure 6-370 ICSSG_PWM0_1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM0_1_NEG_ACT		PWM0_1_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM0_1_NEG_TRIP		PWM0_1_POS_TRIP		PWM0_1_NEG_INIT		PWM0_1_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-717 ICSSG_PWM0_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM0_1_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM0_1_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM0_1_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM0_1_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM0_1_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM0_1_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.76 ICSSG_PWM0_2 Register (Offset = 148h) [reset = X]

ICSSG_PWM0_2 is shown in Figure 6-371 and described in Table 6-719.

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PWM0 State Configuration 2 Register.

Table 6-718 ICSSG_PWM0_2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6148h
PRU_ICSSG1_PR1_CFG_SLV	300A 6148h

Figure 6-371 ICSSG_PWM0_2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM0_2_NEG_ACT		PWM0_2_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM0_2_NEG_TRIP		PWM0_2_POS_TRIP		PWM0_2_NEG_INIT		PWM0_2_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-719 ICSSG_PWM0_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM0_2_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM0_2_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM0_2_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM0_2_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM0_2_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM0_2_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.77 ICSSG_PWM1_0 Register (Offset = 14Ch) [reset = X]

ICSSG_PWM1_0 is shown in Figure 6-372 and described in Table 6-721.

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PWM1 State Configuration 0 Register.

Table 6-720 ICSSG_PWM1_0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 614Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 614Ch

Figure 6-372 ICSSG_PWM1_0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM1_0_NEG_ACT		PWM1_0_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM1_0_NEG_TRIP		PWM1_0_POS_TRIP		PWM1_0_NEG_INIT		PWM1_0_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-721 ICSSG_PWM1_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM1_0_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM1_0_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM1_0_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM1_0_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM1_0_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM1_0_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.78 ICSSG_PWM1_1 Register (Offset = 150h) [reset = X]

ICSSG_PWM1_1 is shown in Figure 6-373 and described in Table 6-723.

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PWM1 State Configuration 1 Register.

Table 6-722 ICSSG_PWM1_1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6150h
PRU_ICSSG1_PR1_CFG_SLV	300A 6150h

Figure 6-373 ICSSG_PWM1_1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM1_1_NEG_ACT		PWM1_1_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM1_1_NEG_TRIP		PWM1_1_POS_TRIP		PWM1_1_NEG_INIT		PWM1_1_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-723 ICSSG_PWM1_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM1_1_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM1_1_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM1_1_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM1_1_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM1_1_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM1_1_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.79 ICSSG_PWM1_2 Register (Offset = 154h) [reset = X]

ICSSG_PWM1_2 is shown in Figure 6-374 and described in Table 6-725.

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PWM1 State Configuration 2 Register.

Table 6-724 ICSSG_PWM1_2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6154h
PRU_ICSSG1_PR1_CFG_SLV	300A 6154h

Figure 6-374 ICSSG_PWM1_2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM1_2_NEG_ACT		PWM1_2_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM1_2_NEG_TRIP		PWM1_2_POS_TRIP		PWM1_2_NEG_INIT		PWM1_2_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-725 ICSSG_PWM1_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM1_2_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM1_2_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM1_2_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM1_2_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM1_2_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM1_2_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.80 ICSSG_PWM2_0 Register (Offset = 158h) [reset = X]

ICSSG_PWM2_0 is shown in Figure 6-375 and described in Table 6-727.

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PWM2 State Configuration 0 Register.

Table 6-726 ICSSG_PWM2_0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6158h
PRU_ICSSG1_PR1_CFG_SLV	300A 6158h

Figure 6-375 ICSSG_PWM2_0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM2_0_NEG_ACT		PWM2_0_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM2_0_NEG_TRIP		PWM2_0_POS_TRIP		PWM2_0_NEG_INIT		PWM2_0_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-727 ICSSG_PWM2_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM2_0_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM2_0_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM2_0_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM2_0_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM2_0_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM2_0_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.81 ICSSG_PWM2_1 Register (Offset = 15Ch) [reset = X]

ICSSG_PWM2_1 is shown in Figure 6-376 and described in Table 6-729.

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PWM2 State Configuration 1 Register.

Table 6-728 ICSSG_PWM2_1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 615Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 615Ch

Figure 6-376 ICSSG_PWM2_1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM2_1_NEG_ACT		PWM2_1_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM2_1_NEG_TRIP		PWM2_1_POS_TRIP		PWM2_1_NEG_INIT		PWM2_1_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-729 ICSSG_PWM2_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM2_1_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM2_1_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM2_1_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM2_1_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM2_1_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM2_1_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.82 ICSSG_PWM2_2 Register (Offset = 160h) [reset = X]

ICSSG_PWM2_2 is shown in Figure 6-377 and described in Table 6-731.

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PWM2 State Configuration 2 Register.

Table 6-730 ICSSG_PWM2_2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6160h
PRU_ICSSG1_PR1_CFG_SLV	300A 6160h

Figure 6-377 ICSSG_PWM2_2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM2_2_NEG_ACT		PWM2_2_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM2_2_NEG_TRIP		PWM2_2_POS_TRIP		PWM2_2_NEG_INIT		PWM2_2_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-731 ICSSG_PWM2_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM2_2_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM2_2_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM2_2_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM2_2_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM2_2_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM2_2_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.83 ICSSG_PWM3_0 Register (Offset = 164h) [reset = X]

ICSSG_PWM3_0 is shown in Figure 6-378 and described in Table 6-733.

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PWM3 State Configuration 0 Register.

Table 6-732 ICSSG_PWM3_0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6164h
PRU_ICSSG1_PR1_CFG_SLV	300A 6164h

Figure 6-378 ICSSG_PWM3_0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM3_0_NEG_ACT		PWM3_0_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM3_0_NEG_TRIP		PWM3_0_POS_TRIP		PWM3_0_NEG_INIT		PWM3_0_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-733 ICSSG_PWM3_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM3_0_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM3_0_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM3_0_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM3_0_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM3_0_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM3_0_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.84 ICSSG_PWM3_1 Register (Offset = 168h) [reset = X]

ICSSG_PWM3_1 is shown in Figure 6-379 and described in Table 6-735.

Return to Summary Table.

PWM3 State Configuration 1 Register.

Table 6-734 ICSSG_PWM3_1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6168h
PRU_ICSSG1_PR1_CFG_SLV	300A 6168h

Figure 6-379 ICSSG_PWM3_1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM3_1_NEG_ACT		PWM3_1_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM3_1_NEG_TRIP		PWM3_1_POS_TRIP		PWM3_1_NEG_INIT		PWM3_1_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-735 ICSSG_PWM3_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM3_1_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM3_1_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM3_1_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM3_1_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM3_1_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM3_1_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.85 ICSSG_PWM3_2 Register (Offset = 16Ch) [reset = X]

ICSSG_PWM3_2 is shown in Figure 6-380 and described in Table 6-737.

Return to Summary Table.

PWM3 State Configuration 2 Register.

Table 6-736 ICSSG_PWM3_2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 616Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 616Ch

Figure 6-380 ICSSG_PWM3_2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED				PWM3_2_NEG_ACT		PWM3_2_POS_ACT
R/W-X				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PWM3_2_NEG_TRIP		PWM3_2_POS_TRIP		PWM3_2_NEG_INIT		PWM3_2_POS_INIT
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-737 ICSSG_PWM3_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R/W	X
11-10	PWM3_2_NEG_ACT	R/W	0h	Active negative state 0h = Toggle 1h = L 2h = H
9-8	PWM3_2_POS_ACT	R/W	0h	Active positive state 0h = Toggle 1h = L 2h = H
7-6	PWM3_2_NEG_TRIP	R/W	0h	Trip negative state 0h = Z 1h = L 2h = H
5-4	PWM3_2_POS_TRIP	R/W	0h	Trip positive state 0h = Z 1h = L 2h = H
3-2	PWM3_2_NEG_INIT	R/W	0h	Initial negative state 0h = Z 1h = L 2h = H
1-0	PWM3_2_POS_INIT	R/W	0h	Initial positive state 0h = Z 1h = L 2h = H

4.14.5.86 ICSSG_SPIN_LOCK0 Register (Offset = 170h) [reset = X]

ICSSG_SPIN_LOCK0 is shown in Figure 6-381 and described in Table 6-739.

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Spin Lock 0 Register.

Table 6-738 ICSSG_SPIN_LOCK0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6170h
PRU_ICSSG1_PR1_CFG_SLV	300A 6170h

Figure 6-381 ICSSG_SPIN_LOCK0 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED		MMR_OWN_REQ_VECTOR_0
R/W-X		R/W-0h

7	6	5	4	3	2	1	0
RESERVED						MMR_OWN_REQ_CLR_0	MMR_OWN_REQ_STATUS_0
R/W-X						W-0h	R-X

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 6-739 ICSSG_SPIN_LOCK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R/W	X
13-8	MMR_OWN_REQ_VECTOR_0	R/W	0h	Spin Lock flag Vector
7-2	RESERVED	R/W	X
1	MMR_OWN_REQ_CLR_0	W	0h	Spin Lock Status Clear
0	MMR_OWN_REQ_STATUS_0	R	X	Spin Lock Status

4.14.5.87 ICSSG_SPIN_LOCK1 Register (Offset = 174h) [reset = X]

ICSSG_SPIN_LOCK1 is shown in Figure 6-382 and described in Table 6-741.

Return to Summary Table.

Spin Lock 1 Register.

Table 6-740 ICSSG_SPIN_LOCK1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6174h
PRU_ICSSG1_PR1_CFG_SLV	300A 6174h

Figure 6-382 ICSSG_SPIN_LOCK1 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED		MMR_OWN_REQ_VECTOR_1
R/W-X		R/W-0h

7	6	5	4	3	2	1	0
RESERVED						MMR_OWN_REQ_CLR_1	MMR_OWN_REQ_STATUS_1
R/W-X						W-0h	R-X

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 6-741 ICSSG_SPIN_LOCK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R/W	X
13-8	MMR_OWN_REQ_VECTOR_1	R/W	0h	Spin Lock flag Vector
7-2	RESERVED	R/W	X
1	MMR_OWN_REQ_CLR_1	W	0h	Spin Lock Status Clear
0	MMR_OWN_REQ_STATUS_1	R	X	Spin Lock Status

4.14.5.88 ICSSG_PA_STAT_PDSP_CFG0 Register (Offset = 178h) [reset = 0h]

ICSSG_PA_STAT_PDSP_CFG0 is shown in Figure 6-383 and described in Table 6-743.

Return to Summary Table.

PA STATS PRU Vector 0 Register.

Table 6-742 ICSSG_PA_STAT_PDSP_CFG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6178h
PRU_ICSSG1_PR1_CFG_SLV	300A 6178h

Figure 6-383 ICSSG_PA_STAT_PDSP_CFG0 Register

31	30	29	28	27	26	25	24
PA_PDSP0_INC_TYPE	PA_PDSP0_INC_VAL
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
PA_PDSP0_INC_VAL
R/W-0h

15	14	13	12	11	10	9	8
PA_PDSP0_INC_VAL		PA_PDSP0_INDEX
R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PA_PDSP0_INDEX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-743 ICSSG_PA_STAT_PDSP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PA_PDSP0_INC_TYPE	R/W	0h	pa_pdsp0_inc_type
30-14	PA_PDSP0_INC_VAL	R/W	0h	pa_pdsp0_inc_val
13-0	PA_PDSP0_INDEX	R/W	0h	pa_pdsp0_index

4.14.5.89 ICSSG_PA_STAT_PDSP_STAT0 Register (Offset = 17Ch) [reset = X]

ICSSG_PA_STAT_PDSP_STAT0 is shown in Figure 6-384 and described in Table 6-745.

Return to Summary Table.

PA STATS PRU Status 0 Register.

Table 6-744 ICSSG_PA_STAT_PDSP_STAT0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 617Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 617Ch

Figure 6-384 ICSSG_PA_STAT_PDSP_STAT0 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED				PA_PDSP0_STATUS			PA_PDSP0_READY
R-X				R-0h			R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-745 ICSSG_PA_STAT_PDSP_STAT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	X
3-1	PA_PDSP0_STATUS	R	0h	pa_pdsp0_status
0	PA_PDSP0_READY	R	0h	pa_pdsp0_ready

4.14.5.90 ICSSG_PA_STAT_PDSP_CFG1 Register (Offset = 180h) [reset = 0h]

ICSSG_PA_STAT_PDSP_CFG1 is shown in Figure 6-385 and described in Table 6-747.

Return to Summary Table.

PA STATS PRU Vector 1 Register.

Table 6-746 ICSSG_PA_STAT_PDSP_CFG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6180h
PRU_ICSSG1_PR1_CFG_SLV	300A 6180h

Figure 6-385 ICSSG_PA_STAT_PDSP_CFG1 Register

31	30	29	28	27	26	25	24
PA_PDSP1_INC_TYPE	PA_PDSP1_INC_VAL
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
PA_PDSP1_INC_VAL
R/W-0h

15	14	13	12	11	10	9	8
PA_PDSP1_INC_VAL		PA_PDSP1_INDEX
R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PA_PDSP1_INDEX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-747 ICSSG_PA_STAT_PDSP_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PA_PDSP1_INC_TYPE	R/W	0h	pa_pdsp1_inc_type
30-14	PA_PDSP1_INC_VAL	R/W	0h	pa_pdsp1_inc_val
13-0	PA_PDSP1_INDEX	R/W	0h	pa_pdsp1_index

4.14.5.91 ICSSG_PA_STAT_PDSP_STAT1 Register (Offset = 184h) [reset = X]

ICSSG_PA_STAT_PDSP_STAT1 is shown in Figure 6-386 and described in Table 6-749.

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PA STATS PRU Status 1 Register.

Table 6-748 ICSSG_PA_STAT_PDSP_STAT1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6184h
PRU_ICSSG1_PR1_CFG_SLV	300A 6184h

Figure 6-386 ICSSG_PA_STAT_PDSP_STAT1 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED				PA_PDSP1_STATUS			PA_PDSP1_READY
R-X				R-0h			R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-749 ICSSG_PA_STAT_PDSP_STAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	X
3-1	PA_PDSP1_STATUS	R	0h	pa_pdsp1_status
0	PA_PDSP1_READY	R	0h	pa_pdsp1_ready

4.14.5.92 ICSSG_PA_STAT_PDSP_CFG2 Register (Offset = 188h) [reset = 0h]

ICSSG_PA_STAT_PDSP_CFG2 is shown in Figure 6-387 and described in Table 6-751.

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PA STATS PRU Vector 2 Register.

Table 6-750 ICSSG_PA_STAT_PDSP_CFG2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6188h
PRU_ICSSG1_PR1_CFG_SLV	300A 6188h

Figure 6-387 ICSSG_PA_STAT_PDSP_CFG2 Register

31	30	29	28	27	26	25	24
PA_PDSP2_INC_TYPE	PA_PDSP2_INC_VAL
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
PA_PDSP2_INC_VAL
R/W-0h

15	14	13	12	11	10	9	8
PA_PDSP2_INC_VAL		PA_PDSP2_INDEX
R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PA_PDSP2_INDEX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-751 ICSSG_PA_STAT_PDSP_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PA_PDSP2_INC_TYPE	R/W	0h	pa_pdsp2_inc_type
30-14	PA_PDSP2_INC_VAL	R/W	0h	pa_pdsp2_inc_val
13-0	PA_PDSP2_INDEX	R/W	0h	pa_pdsp2_index

4.14.5.93 ICSSG_PA_STAT_PDSP_STAT2 Register (Offset = 18Ch) [reset = X]

ICSSG_PA_STAT_PDSP_STAT2 is shown in Figure 6-388 and described in Table 6-753.

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PA STATS PRU Status 2 Register.

Table 6-752 ICSSG_PA_STAT_PDSP_STAT2 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 618Ch
PRU_ICSSG1_PR1_CFG_SLV	300A 618Ch

Figure 6-388 ICSSG_PA_STAT_PDSP_STAT2 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED				PA_PDSP2_STATUS			PA_PDSP2_READY
R-X				R-0h			R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-753 ICSSG_PA_STAT_PDSP_STAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	X
3-1	PA_PDSP2_STATUS	R	0h	pa_pdsp2_status
0	PA_PDSP2_READY	R	0h	pa_pdsp2_ready

4.14.5.94 ICSSG_PA_STAT_PDSP_CFG3 Register (Offset = 190h) [reset = 0h]

ICSSG_PA_STAT_PDSP_CFG3 is shown in Figure 6-389 and described in Table 6-755.

Return to Summary Table.

PA STATS PRU Vector 3 Register.

Table 6-754 ICSSG_PA_STAT_PDSP_CFG3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6190h
PRU_ICSSG1_PR1_CFG_SLV	300A 6190h

Figure 6-389 ICSSG_PA_STAT_PDSP_CFG3 Register

31	30	29	28	27	26	25	24
PA_PDSP3_INC_TYPE	PA_PDSP3_INC_VAL
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
PA_PDSP3_INC_VAL
R/W-0h

15	14	13	12	11	10	9	8
PA_PDSP3_INC_VAL		PA_PDSP3_INDEX
R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
PA_PDSP3_INDEX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-755 ICSSG_PA_STAT_PDSP_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PA_PDSP3_INC_TYPE	R/W	0h	pa_pdsp3_inc_type
30-14	PA_PDSP3_INC_VAL	R/W	0h	pa_pdsp3_inc_val
13-0	PA_PDSP3_INDEX	R/W	0h	pa_pdsp3_index

4.14.5.95 ICSSG_PA_STAT_PDSP_STAT3 Register (Offset = 194h) [reset = X]

ICSSG_PA_STAT_PDSP_STAT3 is shown in Figure 6-390 and described in Table 6-757.

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PA STATS PRU Status 3 Register.

Table 6-756 ICSSG_PA_STAT_PDSP_STAT3 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_CFG_SLV	3002 6194h
PRU_ICSSG1_PR1_CFG_SLV	300A 6194h

Figure 6-390 ICSSG_PA_STAT_PDSP_STAT3 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED				PA_PDSP3_STATUS			PA_PDSP3_READY
R-X				R-0h			R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-757 ICSSG_PA_STAT_PDSP_STAT3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	X
3-1	PA_PDSP3_STATUS	R	0h	pa_pdsp3_status
0	PA_PDSP3_READY	R	0h	pa_pdsp3_ready

6.4.14.5 PRU_ICSSG_CFG Registers

4.14.5.1 ICSSG_PID_REG Register (Offset = 0h) [reset = Xh]

4.14.5.2 ICSSG_HWDIS_REG Register (Offset = 4h) [reset = X]

4.14.5.3 ICSSG_GPCFG0_REG Register (Offset = 8h) [reset = X]

4.14.5.4 ICSSG_GPCFG1_REG Register (Offset = Ch) [reset = X]

4.14.5.5 ICSSG_CGR_REG Register (Offset = 10h) [reset = X]

4.14.5.6 ICSSG_GPECFG0_REG Register (Offset = 14h) [reset = X]

4.14.5.7 ICSSG_GPECFG1_REG Register (Offset = 18h) [reset = X]

4.14.5.8 ICSSG_RSTISO_REG Register (Offset = 1Ch) [reset = X]

4.14.5.9 ICSSG_MII_RT_REG Register (Offset = 2Ch) [reset = X]

4.14.5.10 ICSSG_IEPCLK_REG Register (Offset = 30h) [reset = X]

4.14.5.11 ICSSG_SPP_REG Register (Offset = 34h) [reset = X]

4.14.5.12 ICSSG_CORE_SYNC_REG Register (Offset = 3Ch) [reset = X]

4.14.5.13 ICSSG_SA_MX_REG Register (Offset = 40h) [reset = X]

4.14.5.14 ICSSG_PRU0_SD_CFG_REG Register (Offset = 44h) [reset = X]

4.14.5.15 ICSSG_PRU0_SD_CLK_SEL_REG0 Register (Offset = 48h) [reset = X]

4.14.5.16 ICSSG_PRU0_SD_SAMPLE_SIZE_REG0 Register (Offset = 4Ch) [reset = X]

4.14.5.17 ICSSG_PRU0_SD_CLK_SEL_REG1 Register (Offset = 50h) [reset = X]

4.14.5.18 ICSSG_PRU0_SD_SAMPLE_SIZE_REG1 Register (Offset = 54h) [reset = X]

4.14.5.19 ICSSG_PRU0_SD_CLK_SEL_REG2 Register (Offset = 58h) [reset = X]

4.14.5.20 ICSSG_PRU0_SD_SAMPLE_SIZE_REG2 Register (Offset = 5Ch) [reset = X]

4.14.5.21 ICSSG_PRU0_SD_CLK_SEL_REG3 Register (Offset = 60h) [reset = X]

4.14.5.22 ICSSG_PRU0_SD_SAMPLE_SIZE_REG3 Register (Offset = 64h) [reset = X]

4.14.5.23 ICSSG_PRU0_SD_CLK_SEL_REG4 Register (Offset = 68h) [reset = X]

4.14.5.24 ICSSG_PRU0_SD_SAMPLE_SIZE_REG4 Register (Offset = 6Ch) [reset = X]

4.14.5.25 ICSSG_PRU0_SD_CLK_SEL_REG5 Register (Offset = 70h) [reset = X]

4.14.5.26 ICSSG_PRU0_SD_SAMPLE_SIZE_REG5 Register (Offset = 74h) [reset = X]

4.14.5.27 ICSSG_PRU0_SD_CLK_SEL_REG6 Register (Offset = 78h) [reset = X]

4.14.5.28 ICSSG_PRU0_SD_SAMPLE_SIZE_REG6 Register (Offset = 7Ch) [reset = X]

4.14.5.29 ICSSG_PRU0_SD_CLK_SEL_REG7 Register (Offset = 80h) [reset = X]

4.14.5.30 ICSSG_PRU0_SD_SAMPLE_SIZE_REG7 Register (Offset = 84h) [reset = X]

4.14.5.31 ICSSG_PRU0_SD_CLK_SEL_REG8 Register (Offset = 88h) [reset = X]

4.14.5.32 ICSSG_PRU0_SD_SAMPLE_SIZE_REG8 Register (Offset = 8Ch) [reset = X]

4.14.5.33 ICSSG_PRU1_SD_CFG_REG Register (Offset = 90h) [reset = X]

4.14.5.34 ICSSG_PRU1_SD_CLK_SEL_REG0 Register (Offset = 94h) [reset = X]

4.14.5.35 ICSSG_PRU1_SD_SAMPLE_SIZE_REG0 Register (Offset = 98h) [reset = X]

4.14.5.36 ICSSG_PRU1_SD_CLK_SEL_REG1 Register (Offset = 9Ch) [reset = X]

4.14.5.37 ICSSG_PRU1_SD_SAMPLE_SIZE_REG1 Register (Offset = A0h) [reset = X]

4.14.5.38 ICSSG_PRU1_SD_CLK_SEL_REG2 Register (Offset = A4h) [reset = X]

4.14.5.39 ICSSG_PRU1_SD_SAMPLE_SIZE_REG2 Register (Offset = A8h) [reset = X]

4.14.5.40 ICSSG_PRU1_SD_CLK_SEL_REG3 Register (Offset = ACh) [reset = X]

4.14.5.41 ICSSG_PRU1_SD_SAMPLE_SIZE_REG3 Register (Offset = B0h) [reset = X]

4.14.5.42 ICSSG_PRU1_SD_CLK_SEL_REG4 Register (Offset = B4h) [reset = X]

4.14.5.43 ICSSG_PRU1_SD_SAMPLE_SIZE_REG4 Register (Offset = B8h) [reset = X]

4.14.5.44 ICSSG_PRU1_SD_CLK_SEL_REG5 Register (Offset = BCh) [reset = X]

4.14.5.45 ICSSG_PRU1_SD_SAMPLE_SIZE_REG5 Register (Offset = C0h) [reset = X]

4.14.5.46 ICSSG_PRU1_SD_CLK_SEL_REG6 Register (Offset = C4h) [reset = X]

4.14.5.47 ICSSG_PRU1_SD_SAMPLE_SIZE_REG6 Register (Offset = C8h) [reset = X]

4.14.5.48 ICSSG_PRU1_SD_CLK_SEL_REG7 Register (Offset = CCh) [reset = X]

4.14.5.49 ICSSG_PRU1_SD_SAMPLE_SIZE_REG7 Register (Offset = D0h) [reset = X]

4.14.5.50 ICSSG_PRU1_SD_CLK_SEL_REG8 Register (Offset = D4h) [reset = X]

4.14.5.51 ICSSG_PRU1_SD_SAMPLE_SIZE_REG8 Register (Offset = D8h) [reset = X]

4.14.5.52 ICSSG_PRU0_ED_RX_CFG_REG Register (Offset = E0h) [reset = X]

4.14.5.53 ICSSG_PRU0_ED_TX_CFG_REG Register (Offset = E4h) [reset = X]

4.14.5.54 ICSSG_PRU0_ED_CH0_CFG0_REG Register (Offset = E8h) [reset = 0h]

4.14.5.55 ICSSG_PRU0_ED_CH0_CFG1_REG Register (Offset = ECh) [reset = 0h]

4.14.5.56 ICSSG_PRU0_ED_CH1_CFG0_REG Register (Offset = F0h) [reset = 0h]

4.14.5.57 ICSSG_PRU0_ED_CH1_CFG1_REG Register (Offset = F4h) [reset = 0h]

4.14.5.58 ICSSG_PRU0_ED_CH2_CFG0_REG Register (Offset = F8h) [reset = 0h]

4.14.5.59 ICSSG_PRU0_ED_CH2_CFG1_REG Register (Offset = FCh) [reset = 0h]

4.14.5.60 ICSSG_PRU1_ED_RX_CFG_REG Register (Offset = 100h) [reset = X]

4.14.5.61 ICSSG_PRU1_ED_TX_CFG_REG Register (Offset = 104h) [reset = X]

4.14.5.62 ICSSG_PRU1_ED_CH0_CFG0_REG Register (Offset = 108h) [reset = 0h]

4.14.5.63 ICSSG_PRU1_ED_CH0_CFG1_REG Register (Offset = 10Ch) [reset = 0h]

4.14.5.64 ICSSG_PRU1_ED_CH1_CFG0_REG Register (Offset = 110h) [reset = 0h]

4.14.5.65 ICSSG_PRU1_ED_CH1_CFG1_REG Register (Offset = 114h) [reset = 0h]

4.14.5.66 ICSSG_PRU1_ED_CH2_CFG0_REG Register (Offset = 118h) [reset = 0h]

4.14.5.67 ICSSG_PRU1_ED_CH2_CFG1_REG Register (Offset = 11Ch) [reset = 0h]

4.14.5.68 ICSSG_RTU0_POKE_EN0_REG Register (Offset = 124h) [reset = 0h]

4.14.5.69 ICSSG_RTU1_POKE_EN0_REG Register (Offset = 12Ch) [reset = 0h]

4.14.5.70 ICSSG_PWM0 Register (Offset = 130h) [reset = X]

4.14.5.71 ICSSG_PWM1 Register (Offset = 134h) [reset = X]

4.14.5.72 ICSSG_PWM2 Register (Offset = 138h) [reset = X]

4.14.5.73 ICSSG_PWM3 Register (Offset = 13Ch) [reset = X]

4.14.5.74 ICSSG_PWM0_0 Register (Offset = 140h) [reset = X]

4.14.5.75 ICSSG_PWM0_1 Register (Offset = 144h) [reset = X]

4.14.5.76 ICSSG_PWM0_2 Register (Offset = 148h) [reset = X]

4.14.5.77 ICSSG_PWM1_0 Register (Offset = 14Ch) [reset = X]

4.14.5.78 ICSSG_PWM1_1 Register (Offset = 150h) [reset = X]

4.14.5.79 ICSSG_PWM1_2 Register (Offset = 154h) [reset = X]