SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-298 lists the R5FSS_EVNT_BUS_VBUSP_MMRS registers. All register offset addresses not listed in Table 6-298 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8000h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8000h |
Offset | Acronym | Register Name | R5FSS0_EVNT_BUS_ VBUSP_MMRS Physical Address |
---|---|---|---|
0h | R5FSS_DISABLE_CR | Disable change requests logic register | 3C01 8000h |
4h | R5FSS_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS | CPU0 event bus SB error counter status register | 3C01 8004h |
8h | R5FSS_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS | CPU1 event bus SB error counter status register | 3C01 8008h |
Ch | R5FSS_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS | CPU0 event bus MB error counter status register | 3C01 800Ch |
10h | R5FSS_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS | CPU1 event bus MB error counter status register | 3C01 8010h |
14h | R5FSS_EVNT_BUS_ESM_STATUS | Event bus ESM status register | 3C01 8014h |
18h | R5FSS_EVNT_BUS_ESM_SET | Event bus ESM set register | 3C01 8018h |
1Ch | R5FSS_EVNT_BUS_ESM_CLR | Event bus ESM clear register | 3C01 801Ch |
20h | R5FSS_EVNT_BUS_MASK_ESM_SET | Event bus ESM mask register | 3C01 8020h |
24h | R5FSS_EVNT_BUS_MASK_ESM_CLR | Event bus ESM unmask register | 3C01 8024h |
Offset | Acronym | Register Name | R5FSS0_EVNT_BUS_ VBUSP_MMRS Physical Address |
---|---|---|---|
0h | R5FSS_DISABLE_CR | Disable change requests logic register | 3C03 8000h |
4h | R5FSS_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS | CPU0 event bus SB error counter status register | 3C03 8004h |
8h | R5FSS_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS | CPU1 event bus SB error counter status register | 3C03 8008h |
Ch | R5FSS_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS | CPU0 event bus MB error counter status register | 3C03 800Ch |
10h | R5FSS_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS | CPU1 event bus MB error counter status register | 3C03 8010h |
14h | R5FSS_EVNT_BUS_ESM_STATUS | Event bus ESM status register | 3C03 8014h |
18h | R5FSS_EVNT_BUS_ESM_SET | Event bus ESM set register | 3C03 8018h |
1Ch | R5FSS_EVNT_BUS_ESM_CLR | Event bus ESM clear register | 3C03 801Ch |
20h | R5FSS_EVNT_BUS_MASK_ESM_SET | Event bus ESM mask register | 3C03 8020h |
24h | R5FSS_EVNT_BUS_MASK_ESM_CLR | Event bus ESM unmask register | 3C03 8024h |
R5FSS_DISABLE_CR is shown in Figure 6-143 and described in Table 6-301.
Return to the Summary Table.
This register contains config bits to enable or disable change requests added to the IP.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8000h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMBINE_TCM_LOCKSTEP_MODE | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | COMBINE_TCM_LOCKSTEP_MODE | R/W | 0h | This bit disables the CR logic to combine TCM in lockstep mode |
R5FSS_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS is shown in Figure 6-144 and described in Table 6-303.
Return to the Summary Table.
Status bits showing the R5FSS CPU0 EVNT BUS single-bit error counters.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8004h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EVNT_BUS8 | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EVNT_BUS7 | EVNT_BUS6 | EVNT_BUS5 | EVNT_BUS4 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVNT_BUS3 | EVNT_BUS2 | EVNT_BUS1 | EVNT_BUS0 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17-16 | EVNT_BUS8 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 8 single-bit error counter |
15-14 | EVNT_BUS7 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 7 single-bit error counter |
13-12 | EVNT_BUS6 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 6 single-bit error counter |
11-10 | EVNT_BUS5 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 5 single-bit error counter |
9-8 | EVNT_BUS4 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 4 single-bit error counter |
7-6 | EVNT_BUS3 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 3 single-bit error counter |
5-4 | EVNT_BUS2 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 2 single-bit error counter |
3-2 | EVNT_BUS1 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 1 single-bit error counter |
1-0 | EVNT_BUS0 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 0 single-bit error counter |
R5FSS_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS is shown in Figure 6-145 and described in Table 6-305.
Return to the Summary Table.
Status bits showing the R5FSS CPU1 EVNT BUS single-bit error counters.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8008h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EVNT_BUS8 | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EVNT_BUS7 | EVNT_BUS6 | EVNT_BUS5 | EVNT_BUS4 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVNT_BUS3 | EVNT_BUS2 | EVNT_BUS1 | EVNT_BUS0 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17-16 | EVNT_BUS8 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 8 single-bit error counter |
15-14 | EVNT_BUS7 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 7 single-bit error counter |
13-12 | EVNT_BUS6 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 6 single-bit error counter |
11-10 | EVNT_BUS5 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 5 single-bit error counter |
9-8 | EVNT_BUS4 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 4 single-bit error counter |
7-6 | EVNT_BUS3 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 3 single-bit error counter |
5-4 | EVNT_BUS2 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 2 single-bit error counter |
3-2 | EVNT_BUS1 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 1 single-bit error counter |
1-0 | EVNT_BUS0 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 0 single-bit error counter |
R5FSS_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS is shown in Figure 6-146 and described in Table 6-307.
Return to the Summary Table.
Status bits showing the R5FSS CPU0 EVNT BUS multi-bit error counters.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 800Ch |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 800Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | EVNT_BUS6 | EVNT_BUS5 | EVNT_BUS4 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVNT_BUS3 | EVNT_BUS2 | EVNT_BUS1 | EVNT_BUS0 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R | 0h | Reserved |
13-12 | EVNT_BUS6 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 6 multi-bit error counter |
11-10 | EVNT_BUS5 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 5 multi-bit error counter |
9-8 | EVNT_BUS4 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 4 multi-bit error counter |
7-6 | EVNT_BUS3 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 3 multi-bit error counter |
5-4 | EVNT_BUS2 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 2 multi-bit error counter |
3-2 | EVNT_BUS1 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 1 multi-bit error counter |
1-0 | EVNT_BUS0 | R | 0h | Status bits showing the R5FSS CPU0 EVNT 0 multi-bit error counter |
R5FSS_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS is shown in Figure 6-147 and described in Table 6-309.
Return to the Summary Table.
Status bits showing the R5FSS CPU1 EVNT BUS multi-bit error counters.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8010h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | EVNT_BUS6 | EVNT_BUS5 | EVNT_BUS4 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVNT_BUS3 | EVNT_BUS2 | EVNT_BUS1 | EVNT_BUS0 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R | 0h | Reserved |
13-12 | EVNT_BUS6 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 6 multi-bit error counter |
11-10 | EVNT_BUS5 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 5 multi-bit error counter |
9-8 | EVNT_BUS4 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 4 multi-bit error counter |
7-6 | EVNT_BUS3 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 3 multi-bit error counter |
5-4 | EVNT_BUS2 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 2 multi-bit error counter |
3-2 | EVNT_BUS1 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 1 multi-bit error counter |
1-0 | EVNT_BUS0 | R | 0h | Status bits showing the R5FSS CPU1 EVNT 0 multi-bit error counter |
R5FSS_EVNT_BUS_ESM_STATUS is shown in Figure 6-148 and described in Table 6-311.
Return to the Summary Table.
ESM status bits for the R5FSS EVNT BUS.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8014h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_MULTIPLE_BIT_ERROR | CPU1_SINGLE_BIT_ERROR | CPU0_MULTIPLE_BIT_ERROR | CPU0_SINGLE_BIT_ERROR | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU1_MULTIPLE_BIT_ERROR | R | 0h | ESM status of CPU1 multi-bit errors on EVNT BUS |
2 | CPU1_SINGLE_BIT_ERROR | R | 0h | ESM status of CPU1 single-bit errors on EVNT BUS |
1 | CPU0_MULTIPLE_BIT_ERROR | R | 0h | ESM status of CPU0 multi-bit errors on EVNT BUS |
0 | CPU0_SINGLE_BIT_ERROR | R | 0h | ESM status of CPU0 single-bit errors on EVNT BUS |
R5FSS_EVNT_BUS_ESM_SET is shown in Figure 6-149 and described in Table 6-313.
Return to the Summary Table.
Set the R5FSS EVNT BUS ESM events.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8018h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_MULTIPLE_BIT_ERROR | CPU1_SINGLE_BIT_ERROR | CPU0_MULTIPLE_BIT_ERROR | CPU0_SINGLE_BIT_ERROR | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU1_MULTIPLE_BIT_ERROR | R/W1S | 0h | Set CPU1 multi-bit errors ESM event |
2 | CPU1_SINGLE_BIT_ERROR | R/W1S | 0h | Set CPU1 single-bit errors ESM event |
1 | CPU0_MULTIPLE_BIT_ERROR | R/W1S | 0h | Set CPU0 multi-bit error ESM event |
0 | CPU0_SINGLE_BIT_ERROR | R/W1S | 0h | Set CPU0 single-bit error ESM event |
R5FSS_EVNT_BUS_ESM_CLR is shown in Figure 6-150 and described in Table 6-315.
Return to the Summary Table.
RESET the R5FSS EVNT BUS ESM events.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 801Ch |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 801Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_EB6_MULTIPLE_BIT_ERROR | CPU1_EB5_MULTIPLE_BIT_ERROR | CPU1_EB4_MULTIPLE_BIT_ERROR | CPU1_EB3_MULTIPLE_BIT_ERROR | CPU1_EB2_MULTIPLE_BIT_ERROR | CPU1_EB1_MULTIPLE_BIT_ERROR | CPU1_EB0_MULTIPLE_BIT_ERROR | CPU1_EB8_SINGLE_BIT_ERROR |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_EB7_SINGLE_BIT_ERROR | CPU1_EB6_SINGLE_BIT_ERROR | CPU1_EB5_SINGLE_BIT_ERROR | CPU1_EB4_SINGLE_BIT_ERROR | CPU1_EB3_SINGLE_BIT_ERROR | CPU1_EB2_SINGLE_BIT_ERROR | CPU1_EB1_SINGLE_BIT_ERROR | CPU1_EB0_SINGLE_BIT_ERROR |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_EB6_MULTIPLE_BIT_ERROR | CPU0_EB5_MULTIPLE_BIT_ERROR | CPU0_EB4_MULTIPLE_BIT_ERROR | CPU0_EB3_MULTIPLE_BIT_ERROR | CPU0_EB2_MULTIPLE_BIT_ERROR | CPU0_EB1_MULTIPLE_BIT_ERROR | CPU0_EB0_MULTIPLE_BIT_ERROR | CPU0_EB8_SINGLE_BIT_ERROR |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_EB7_SINGLE_BIT_ERROR | CPU0_EB6_SINGLE_BIT_ERROR | CPU0_EB5_SINGLE_BIT_ERROR | CPU0_EB4_SINGLE_BIT_ERROR | CPU0_EB3_SINGLE_BIT_ERROR | CPU0_EB2_SINGLE_BIT_ERROR | CPU0_EB1_SINGLE_BIT_ERROR | CPU0_EB0_SINGLE_BIT_ERROR |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_EB6_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 31 multi-bit error counter |
30 | CPU1_EB5_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 30 multi-bit error counter |
29 | CPU1_EB4_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 29 multi-bit error counter |
28 | CPU1_EB3_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 28 multi-bit error counter |
27 | CPU1_EB2_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 27 multi-bit error counter |
26 | CPU1_EB1_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 26 multi-bit error counter |
25 | CPU1_EB0_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 25 multi-bit error counter |
24 | CPU1_EB8_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 24 single-bit error counter |
23 | CPU1_EB7_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 23 single-bit error counter |
22 | CPU1_EB6_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 22 single-bit error counter |
21 | CPU1_EB5_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 21 single-bit error counter |
20 | CPU1_EB4_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 20 single-bit error counter |
19 | CPU1_EB3_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 19 single-bit error counter |
18 | CPU1_EB2_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 18 single-bit error counter |
17 | CPU1_EB1_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 17 single-bit error counter |
16 | CPU1_EB0_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU1 EVNT BUS 16 single-bit error counter |
15 | CPU0_EB6_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 15 multi-bit error counter |
14 | CPU0_EB5_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 14 multi-bit error counter |
13 | CPU0_EB4_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 13 multi-bit error counter |
12 | CPU0_EB3_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 12 multi-bit error counter |
11 | CPU0_EB2_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 11 multi-bit error counter |
10 | CPU0_EB1_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 10 multi-bit error counter |
9 | CPU0_EB0_MULTIPLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 9 multi-bit error counter |
8 | CPU0_EB8_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 8 single-bit error counter |
7 | CPU0_EB7_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 7 single-bit error counter |
6 | CPU0_EB6_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 6 single-bit error counter |
5 | CPU0_EB5_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 5 single-bit error counter |
4 | CPU0_EB4_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 4 single-bit error counter |
3 | CPU0_EB3_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 3 single-bit error counter |
2 | CPU0_EB2_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 2 single-bit error counter |
1 | CPU0_EB1_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 1 single-bit error counter |
0 | CPU0_EB0_SINGLE_BIT_ERROR | R/W | 0h | Decrement CPU0 EVNT BUS 0 single-bit error counter |
R5FSS_EVNT_BUS_MASK_ESM_SET is shown in Figure 6-151 and described in Table 6-317.
Return to the Summary Table.
Mask the R5FSS EVNT BUS ESM events.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8020h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_MULTIPLE_BIT_ERROR | CPU1_SINGLE_BIT_ERROR | CPU0_MULTIPLE_BIT_ERROR | CPU0_SINGLE_BIT_ERROR | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU1_MULTIPLE_BIT_ERROR | R/W1S | 0h | Mask CPU1 multi-bit errors ESM event |
2 | CPU1_SINGLE_BIT_ERROR | R/W1S | 0h | Mask CPU1 single-bit errors ESM event |
1 | CPU0_MULTIPLE_BIT_ERROR | R/W1S | 0h | Mask CPU0 multi-bit error ESM event |
0 | CPU0_SINGLE_BIT_ERROR | R/W1S | 0h | Mask CPU0 single-bit error ESM event |
R5FSS_EVNT_BUS_MASK_ESM_CLR is shown in Figure 6-152 and described in Table 6-319.
Return to the Summary Table.
Unmask the R5FSS EVNT BUS ESM events.
Instance | Base Address |
---|---|
R5FSS0_EVNT_BUS_VBUSP_MMRS | 3C01 8024h |
R5FSS1_EVNT_BUS_VBUSP_MMRS | 3C03 8024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_MULTIPLE_BIT_ERROR | CPU1_SINGLE_BIT_ERROR | CPU0_MULTIPLE_BIT_ERROR | CPU0_SINGLE_BIT_ERROR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU1_MULTIPLE_BIT_ERROR | R/W1C | 0h | Unmask CPU1 multi-bit errors ESM event |
2 | CPU1_SINGLE_BIT_ERROR | R/W1C | 0h | Unmask CPU1 single-bit errors ESM event |
1 | CPU0_MULTIPLE_BIT_ERROR | R/W1C | 0h | Unmask CPU0 multi-bit error ESM event |
0 | CPU0_SINGLE_BIT_ERROR | R/W1C | 0h | Unmask CPU0 single-bit error ESM event |