12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 80 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 440 Architecture Pipeline SNR (dB) 71.7 ENOB (Bits) 11.5 SFDR (dB) 80 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RHA) 40 36 mm² 6 x 6 open-in-new Find other High-speed ADCs (>10MSPS)


  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate of 1.6 Gbps
    • Meets JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA – 32 mA
  • Power Dissipation:
    • 440 mW at 80 MSPS in Single Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • 71.7 dBFS SNR at 70 MHz IF
  • Analog Input FSR: 2 Vpp
  • External and Internal (trimmed) Reference Support
  • 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
  • Programmable Digital Gain: 0dB – 6dB
  • Straight Offset Binary or Twos Complement Output
  • Package:
    • 6 mm × 6 mm QFN-40
open-in-new Find other High-speed ADCs (>10MSPS)


The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet Dec. 01, 2012
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
User guide ADS61JBxx EVM User's Guide (Rev. A) Sep. 30, 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).


The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

  • Simple 16-bit waveform capture from many of TI’s high speed ADC EVM’s
  • Supports 64k sample depth at up to 1.0 GSPS LVDS I/O rates
  • LatticeECP3 high speed mini FPGA
  • Analyzes up to 8 channels concurrently
  • Single mini USB cable for power and data
  • Utilizes an intuitive/easy-to-use GUI package
  • Industry’s (...)
  • Software development

    FIRMWARE Download
    JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
    TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
    • Compatible with JEDEC JESD204a/b/c protocols
    • Supports subclass 1 deterministic latency and multidevice synchronization
    • Supported lane rates
      • Up to 16.375 Gbps in 8b/10b mode
      • Up to 20 Gbps in 64b/66b mode
    • Supports all protocol related error detection and reporting features
    • Integrated transport layer (...)
    SLAC530.ZIP (82937 KB)
    SBAC120.ZIP (262219 KB)

    Design tools & simulation

    SLOM341.ZIP (110 KB) - IBIS Model
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    DESIGN TOOL Download
    SBAC119B.ZIP (3547 KB)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RHA) 40 View options

    Ordering & quality

    Information included:
    • RoHS
    • REACH
    • Device marking
    • Lead finish/Ball material
    • MSL rating/Peak reflow
    • MTBF/FIT estimates
    • Material content
    • Qualification summary
    • Ongoing reliability monitoring

    Support & training

    TI E2E™ forums with technical support from TI engineers

    Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

    If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​