Home Data converters Analog-to-digital converters (ADCs) High-speed ADCs (≥10 MSPS)
Home
Data converters
Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADS61JB23

ACTIVE

12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

Order now
Data sheet

ADS61JB23

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 80 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 440 Architecture Pipeline SNR (dB) 71.7 ENOB (Bits) 11.5 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 80 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 440 Architecture Pipeline SNR (dB) 71.7 ENOB (Bits) 11.5 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RHA) 40 36 mm² 6 x 6
  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate of 1.6 Gbps
    • Meets JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA – 32 mA
  • Power Dissipation:
    • 440 mW at 80 MSPS in Single Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • 71.7 dBFS SNR at 70 MHz IF
  • Analog Input FSR: 2 Vpp
  • External and Internal (trimmed) Reference Support
  • 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
  • Programmable Digital Gain: 0dB – 6dB
  • Straight Offset Binary or Twos Complement Output
  • Package:
    • 6 mm × 6 mm QFN-40
  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate of 1.6 Gbps
    • Meets JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA – 32 mA
  • Power Dissipation:
    • 440 mW at 80 MSPS in Single Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • 71.7 dBFS SNR at 70 MHz IF
  • Analog Input FSR: 2 Vpp
  • External and Internal (trimmed) Reference Support
  • 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
  • Programmable Digital Gain: 0dB – 6dB
  • Straight Offset Binary or Twos Complement Output
  • Package:
    • 6 mm × 6 mm QFN-40

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).
filter Find other High-speed ADCs (≥10 MSPS)
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 3
Top documentation Type Title Format options Date
* Data sheet 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet 01 Dec 2012
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Firmware

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

Supported products & hardware

Supported products & hardware
Request
GUI for evaluation module (EVM)

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware
Download
GUI for evaluation module (EVM)

SLAC530 — ADS61JB23 SPI GUI Installer

Supported products & hardware

Supported products & hardware
Download
Support software

SBAC120 — TIGAR Support Files

Supported products & hardware

Supported products & hardware
Download
Simulation model

ADS61JBXX IBIS Model

SLOM341.ZIP (110 KB) - IBIS Model
Download
Calculation tool

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Supported products & hardware

Supported products & hardware
Launch Download
Design tool

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Supported products & hardware

Supported products & hardware
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins CAD symbols, footprints & 3D models
VQFN (RHA) 40 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos