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Product details

Parameters

Sample rate (Max) (MSPS) 50 Resolution (Bits) 12 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 281 Architecture Pipeline SNR (dB) 70.3 ENOB (Bits) 11.4 SFDR (dB) 95 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Dual Channel
  • 12-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 70.3 dBFS, SFDR = 88 dBc at
    fIN = 70 MHz
  • Ultralow Power Consumption:
    • 227 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multichip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
    (ADC32J4X)
  • Package: VQFN-48 (7 mm × 7 mm)
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC32J2x is a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

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Technical documentation

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Type Title Date
* Data sheet ADC32J2x Dual-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface datasheet (Rev. A) May 21, 2015
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
User guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) Aug. 24, 2018
Technical article RF sampling: Learning more about latency Feb. 09, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406, TSW14J10, TSW14J50, TSW14J56, TSW14J57 and TSW14J58 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SIMULATION MODEL Download
SBAM204.ZIP (79 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

REFERENCE DESIGNS Download
High Perf Single Ended to Diff Active Interface for High Speed ADC Developed by Dallas Logic Corp
Provided by Dallas Logic Corporation This reference design uses the ADC34J22 12b 50Msps JESD204B data converter and the THS4541 fully differential amplifer to demonstrate how to design a high performance active interface for high speed ADCs.  This type of circuit can be used in sensor front end, motor control, and test and (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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