Dual-Channel, 14-Bit, 9-GSPS, 12x-24x Interpolating, 9 GHz GSM PLL Digital-to-Analog Converter (DAC)
Product details
Parameters
Package | Pins | Size
Features
- 14-Bit Resolution
- Maximum DAC Sample Rate:
- 9.0 GSPS (DAC38RF86, DAC38RF96)
- 6.2 GSPS (DAC38RF87, DAC38RF97)
- Key Specifications:
- RF Full-Scale Output Power at 2.1 GHz:0 dBm
- Spectral Performance, DAC38RF87/97
- fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
- WCDMA ACLR: 73 dBc
- WCDMA alt-ACLR: 77 dBc
- fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
- Spectral Performance, DAC38RF86/96
- fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
- 20 MHz LTE ACLR: 66 dBc
- fDAC = 9 GSPS, fOUT = 1.8 GHz, –6 dBFS
- IMD3 = 70 dBc (10-MHz tone spacing)
- fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
- Dual-Band Digital Up-converter per DAC
- 6, 8, 10, 12, 16, 18, 20 or 24x Interpolation
- 4 Independent NCOs With 48-Bit Resolution
- JESD204B Interface, Subclass 1
- Support for Multichip Synchronization
- Maximum Lane Rate: 12.5 Gbps
- Single-Ended Output With Integrated Balun Covering 700 MHz to 3800 MHz
- Internal PLL and VCO
- DAC38RF86/96: fC(VCO) = 8.85 GHz
- DAC38RF87/97: fC(VCO) = 5.90 GHz
- Power Dissipation: 1.4 to 2.2 W/ch
- Power Supplies: –1.8 V, 1 V, 1.8 V
- Package: 10 x 10 mm BGA, 0.8 mm Pitch, 144-Balls
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Description
The DAC38RF86/96 is a family of high-performance, dual-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. The DAC38RF87/97 is also a family of high-performance, dual-channel, 14-bit, 6-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 3 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.
The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. A GSM compliant low phase noise PLL/VCO is integrated to simplify the DAC sampling clock generation by allowing the use of a lower frequency reference clock
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL datasheet (Rev. B) | Jul. 31, 2017 |
Application note | Impact of Power-Supply Noise on Phase Noise Performance of RF DACs | Jun. 13, 2018 | |
Application note | Eye Scan Testing with the DAC38RFxx | Aug. 10, 2017 | |
Application note | Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information | Aug. 02, 2017 | |
Application note | DAC38RF8x Test Modes | Jul. 25, 2017 | |
Technical article | Digital signal processing in RF sampling DACs – part 2 | Apr. 04, 2017 | |
Technical article | Digital signal processing in RF sampling DACs - part 1 | Feb. 13, 2017 | |
User guide | Efficient Power Supply Scheme for RF-Sampling DAC Reference Design | Aug. 22, 2016 | |
Technical article | RF sampling: digital mixers make mixing fun | Sep. 17, 2015 | |
Technical article | How our high-speed DAC summation block can help you | Apr. 02, 2014 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
- Supports up to 12.5-Gbps SerDes signaling rate across FMC
- Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
- AC-coupled output with integrated impedance transformer (...)
Software development
Features
- Compatible with JEDEC JESD204a/b/c protocols
- Supports subclass 1 deterministic latency and multidevice synchronization
- Supported lane rates
- Up to 16.375 Gbps in 8b/10b mode
- Up to 20 Gbps in 64b/66b mode
- Supports all protocol related error detection and reporting features
- Integrated transport layer (...)
Design tools & simulation
Reference designs
Design files
-
download TIDA-01215 BOM.pdf (257KB) -
download TIDA-01215 Assembly Drawing.pdf (114KB) -
download TIDA-01215 PCB.pdf (2454KB) -
download TIDA-01215 CAD Files.zip (2164KB) -
download TIDA-01215 Gerber.zip (978KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
FCBGA (AAV) | 144 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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