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DAC38RF96

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Dual-Channel, 14-Bit, 9-GSPS, 12x-24x Interpolating, 9 GHz GSM PLL Digital-to-Analog Converter (DAC)

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Dual-Channel, 14-Bit, 9-GSPS, 12x-24x Interpolating, 9 GHz GSM PLL Digital-to-Analog Converter (DAC)

DAC38RF96

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Data sheet Order now

Product details

Parameters

Resolution (Bits) 14 Sample/update rate (MSPS) 9000 DACs (#) 2 Interpolation 12x, 16x, 18x, 20x, 24x Power consumption (Typ) (mW) 3800 Operating temperature range (C) -40 to 85 open-in-new Find other Transmitters

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other Transmitters

Features

  • 14-Bit Resolution
  • Maximum DAC Sample Rate:
    • 9.0 GSPS (DAC38RF86, DAC38RF96)
    • 6.2 GSPS (DAC38RF87, DAC38RF97)
  • Key Specifications:
    • RF Full-Scale Output Power at 2.1 GHz:0 dBm
    • Spectral Performance, DAC38RF87/97
      • fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
        • WCDMA ACLR: 73 dBc
        • WCDMA alt-ACLR: 77 dBc
    • Spectral Performance, DAC38RF86/96
      • fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
        • 20 MHz LTE ACLR: 66 dBc
      • fDAC = 9 GSPS, fOUT = 1.8 GHz, –6 dBFS
        • IMD3 = 70 dBc (10-MHz tone spacing)
  • Dual-Band Digital Up-converter per DAC
    • 6, 8, 10, 12, 16, 18, 20 or 24x Interpolation
    • 4 Independent NCOs With 48-Bit Resolution
  • JESD204B Interface, Subclass 1
    • Support for Multichip Synchronization
    • Maximum Lane Rate: 12.5 Gbps
  • Single-Ended Output With Integrated Balun Covering 700 MHz to 3800 MHz
  • Internal PLL and VCO
    • DAC38RF86/96: fC(VCO) = 8.85 GHz
    • DAC38RF87/97: fC(VCO) = 5.90 GHz
  • Power Dissipation: 1.4 to 2.2 W/ch
  • Power Supplies: –1.8 V, 1 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm Pitch, 144-Balls

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Description

The DAC38RF86/96 is a family of high-performance, dual-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. The DAC38RF87/97 is also a family of high-performance, dual-channel, 14-bit, 6-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 3 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.

The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. A GSM compliant low phase noise PLL/VCO is integrated to simplify the DAC sampling clock generation by allowing the use of a lower frequency reference clock

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Technical documentation

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Type Title Date
* Datasheet DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL datasheet (Rev. B) Jul. 31, 2017
Application notes Impact of Power-Supply Noise on Phase Noise Performance of RF DACs Jun. 13, 2018
Application notes Eye Scan Testing with the DAC38RFxx Aug. 10, 2017
Application notes Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information Aug. 02, 2017
Application notes DAC38RF8x Test Modes Jul. 25, 2017
User guides Efficient Power Supply Scheme for RF-Sampling DAC Reference Design Aug. 22, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description
The DAC38RF86 evaluation module (EVM) is the circuit board for evaluating DAC38RF86 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC connector also (...)
Features
  • Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (...)
View details

Design tools & simulation

SIMULATION MODELS Download
SLAM304.ZIP (70 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
document-generic Schematic document-generic User guide

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FCBGA (AAV) 144 View options

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